2010-08-10 03:11:02 +00:00
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< p > STM32F10x Connectivity Line HAL subsystem low level driver header.
< a href = "#_details" > More...< / a > < / p >
< p > < a href = "hal__lld__f105__f107_8h_source.html" > Go to the source code of this file.< / a > < / p >
2010-11-22 05:53:37 +00:00
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Defines< / h2 > < / td > < / tr >
2010-08-10 03:11:02 +00:00
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga65c12bc7160ab579eaeee40ec2915110" > STM32_HSICLK< / a > 8000000< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga90421650b988332462db9a08815efb6f" > STM32_LSICLK< / a > 40000< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga6a49bf4388f3acf15661252b3bb7547b" > STM32_SW_HSI< / a > (0 < < 0)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gab5b581bd1ff4fd48fc8c5f093ca776ca" > STM32_SW_HSE< / a > (1 < < 0)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga8bc74f08245bf796555d33a86afd9fc4" > STM32_SW_PLL< / a > (2 < < 0)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gabf2bcd341b2140b7a82ff24b92f6af68" > STM32_HPRE_DIV1< / a > (0 < < 4)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga6dfcd5149eb88f1681b4defc77f4d8b2" > STM32_HPRE_DIV2< / a > (8 < < 4)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gaeb5f7cce4d1b6646f7e48d2784aade1c" > STM32_HPRE_DIV4< / a > (9 < < 4)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gaaa6b23363a848239b048cde5b565e2d5" > STM32_HPRE_DIV8< / a > (10 < < 4)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gaab6772439c76981e1c1d23bf97ec3910" > STM32_HPRE_DIV16< / a > (11 < < 4)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga152f3c2eabcc96019194c85bb2f7f2af" > STM32_HPRE_DIV64< / a > (12 < < 4)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga6ea1e82317d266fa344d6787f485e991" > STM32_HPRE_DIV128< / a > (13 < < 4)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga7099ae3ddeb74537f4a34f1e36730dbe" > STM32_HPRE_DIV256< / a > (14 < < 4)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gaac6d223ccd51614bd3c8f354b16e4671" > STM32_HPRE_DIV512< / a > (15 < < 4)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga3c9ece8fc206039d5723f8016adb789d" > STM32_PPRE1_DIV1< / a > (0 < < 8)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gae205bae3cec6b45723d687bc2b7a4e38" > STM32_PPRE1_DIV2< / a > (4 < < 8)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga18b34bc52ebebd209fffb01002b2bc98" > STM32_PPRE1_DIV4< / a > (5 < < 8)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gab7b100956dae0246dd9faa0a54010b17" > STM32_PPRE1_DIV8< / a > (6 < < 8)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga750b0ba24dbebb1fac1a3b2330666350" > STM32_PPRE1_DIV16< / a > (7 < < 8)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga9883bc736b03534d09789f13a6026c31" > STM32_PPRE2_DIV1< / a > (0 < < 11)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga55e0199e60c0551b8fae6b8eb49d6364" > STM32_PPRE2_DIV2< / a > (4 < < 11)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gaa85c01042fcee21da997473f4f42ba78" > STM32_PPRE2_DIV4< / a > (5 < < 11)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga0db040c759cc09cee6261301a952d862" > STM32_PPRE2_DIV8< / a > (6 < < 11)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gaf986782e091335aeaf0235635d20353d" > STM32_PPRE2_DIV16< / a > (7 < < 11)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gaedf6c315cac4eed84eefb906f11909d5" > STM32_ADCPRE_DIV2< / a > (0 < < 14)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gac85f817c97ee65cef48408aae15a4275" > STM32_ADCPRE_DIV4< / a > (1 < < 14)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gad628210302793a5ffdd7a92515c2d3a1" > STM32_ADCPRE_DIV6< / a > (2 < < 14)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gacc4296ec001b1f54da48a503c68af27a" > STM32_ADCPRE_DIV8< / a > (3 < < 14)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gac8438d5c9b3c6bfd0346e1026b8055fc" > STM32_PLLSRC_HSI< / a > (0 < < 16)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga92a499ebef58406ab8a3fbd22ff76938" > STM32_PLLSRC_PREDIV1< / a > (1 < < 16)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga69f9922a2c51301f69ea204b69462bad" > STM32_OTGFSPRE_DIV2< / a > (1 < < 22)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga920fca24655662d92ce59f276b202935" > STM32_OTGFSPRE_DIV3< / a > (0 < < 22)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga89cb88c836f543f0133cb923d24b8ac2" > STM32_MCO_NOCLOCK< / a > (0 < < 24)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga88dd4d9fea9a7de30ff26dfc73b2dca7" > STM32_MCO_SYSCLK< / a > (4 < < 24)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gaa208624a69b4a031b7ce4b9bf41a0dac" > STM32_MCO_HSI< / a > (5 < < 24)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga881bbb9fb274aaa98a69c6fcc64a92ab" > STM32_MCO_HSE< / a > (6 < < 24)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga1c0494e40e6a7a032b259209fb69a802" > STM32_MCO_PLLDIV2< / a > (7 < < 24)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gaba58c889c2c87f44aa19b81855d90870" > STM32_MCO_PLL2< / a > (8 < < 24)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gafd2c052b8cb82b9d4f751afe49361c82" > STM32_MCO_PLL3DIV2< / a > (9 < < 24)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gae87f8f079c9a356d6b613e890842b187" > STM32_MCO_XT1< / a > (10 < < 24)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga351d3550fe3338ba2dbba564079e9380" > STM32_MCO_PLL3< / a > (11 < < 24)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gab980c2814dda4c3f03e4d4ac18e339c8" > STM32_PREDIV1SRC_HSE< / a > (0 < < 16)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga495a1e77396146b55b5f311b9d33316f" > STM32_PREDIV1SRC_PLL2< / a > (1 < < 16)< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gad4c8a013e3354da6d132cdb91a481c3c" > WWDG_IRQHandler< / a > Vector40< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga045476dfaec8c84f5e16b06b937c0c18" > PVD_IRQHandler< / a > Vector44< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga3668bf2c1d66bea024e3ff1cc7f9952c" > TAMPER_IRQHandler< / a > Vector48< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gaeadad366a84e3b496a18ef919a28342b" > RTC_IRQHandler< / a > Vector4C< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga3cca2eaebb146655fb72e09adee7839d" > FLASH_IRQHandler< / a > Vector50< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga5a6d083fa78461da86a717b28973e009" > RCC_IRQHandler< / a > Vector54< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gac468127e2887086eeafd0fc5044c8c1f" > EXTI0_IRQHandler< / a > Vector58< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga0580c4052329cca57bede85ffff29de5" > EXTI1_IRQHandler< / a > Vector5C< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gae39f987c5ace4c480d23ea000ed53f6e" > EXTI2_IRQHandler< / a > Vector60< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga6227b0b9333e766db47c3e86d57b8a4f" > EXTI3_IRQHandler< / a > Vector64< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gab7dcb33a5cf9254fd25f8619c6c92ab8" > EXTI4_IRQHandler< / a > Vector68< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga3f7debe9fc2548ab6640825967110101" > DMA1_Ch1_IRQHandler< / a > Vector6C< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga37d95c99d84753e4efe4909bbaae4fa1" > DMA1_Ch2_IRQHandler< / a > Vector70< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gaa3a67d36319fc3c153999ebbb0e0cd49" > DMA1_Ch3_IRQHandler< / a > Vector74< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga76bb91040587d17a396ccb31395aa0e5" > DMA1_Ch4_IRQHandler< / a > Vector78< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gadbe5dfd4aed18b04f864d5fbed32f438" > DMA1_Ch5_IRQHandler< / a > Vector7C< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga39b427886b2c2d2c7ce3be9537c1f6a2" > DMA1_Ch6_IRQHandler< / a > Vector80< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gaecfa962ef95ba5a06ad60ac57e8a54ec" > DMA1_Ch7_IRQHandler< / a > Vector84< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gabc7315be5ac997b8f347fe1e22f58adf" > ADC1_2_IRQHandler< / a > Vector88< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga4fdbecfed2cdeadfec6210f7ec510fbc" > CAN1_TX_IRQHandler< / a > Vector8C< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga40873fbdcb268642576f45babaad5c2e" > CAN1_RX0_IRQHandler< / a > Vector90< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga8550c9680a59f697a018b283878b0648" > CAN1_RX1_IRQHandler< / a > Vector94< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gab6a0b35d117d66c63172d56a59ce2e20" > CAN1_SCE_IRQHandler< / a > Vector98< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gab2efac0867c3c975ea4ea586013b10ce" > EXTI9_5_IRQHandler< / a > Vector9C< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga2f33687cec484ac054656b3a9daca2c1" > TIM1_BRK_IRQHandler< / a > VectorA0< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga578b4afc3dd6695f66e1b7a116c33d41" > TIM1_UP_IRQHandler< / a > VectorA4< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga029af7575a43b2c3c6b50c62571ed21c" > TIM1_TRG_COM_IRQHandler< / a > VectorA8< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga3f167d3dabac4824347885babe86926f" > TIM1_CC_IRQHandler< / a > VectorAC< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga499bdce3f1172d391e9565e9f9d07a76" > TIM2_IRQHandler< / a > VectorB0< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga8e5c20e41d6d555efd718fc29037cc26" > TIM3_IRQHandler< / a > VectorB4< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga582fbd8d35d9280347b55cd12f65c213" > TIM4_IRQHandler< / a > VectorB8< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga83e61d3d4eb31c12a4369f6b1d9fa742" > I2C1_EV_IRQHandler< / a > VectorBC< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gad8e382b9ce2bb267c7414c7185637654" > I2C1_ER_IRQHandler< / a > VectorC0< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga0b8dacb7ac76cfc954fd0db2d5e53025" > I2C2_EV_IRQHandler< / a > VectorC4< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga1a98d05b127fa293a1210397bda82007" > I2C2_ER_IRQHandler< / a > VectorC8< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gadc38983c3ec1357840b21472ff1a2147" > SPI1_IRQHandler< / a > VectorCC< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gaaace6fa425ba2038de9ce01755070057" > SPI2_IRQHandler< / a > VectorD0< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga23182c2feafd217668e6b37c126512a1" > USART1_IRQHandler< / a > VectorD4< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga484cf268e20400bfa2cf159fd86b98be" > USART2_IRQHandler< / a > VectorD8< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga8a246e61ab1022b289c251e48f7094aa" > USART3_IRQHandler< / a > VectorDC< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga94d705608b3377724d368a6ce381c735" > EXTI15_10_IRQHandler< / a > VectorE0< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga649ba5a31ccb8936b7bb9be165160be4" > RTCAlarm_IRQHandler< / a > VectorE4< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga8d10057f3ad0cec6a12f2f593ef8e4c0" > OTG_FS_WKUP_IRQHandler< / a > VectorE8< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gab9fe80492ed4e0fa1fd6faf58bd58e4b" > TIM5_IRQHandler< / a > Vector108< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gad9e1203f13593d969234331ceb55d7d2" > SPI3_IRQHandler< / a > Vector10C< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gac4b19b89f21dd7c2510cf3ad18f30550" > UART4_IRQHandler< / a > Vector110< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga3b377c7a7064b3dad2e2ef423f786786" > UART5_IRQHandler< / a > Vector114< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gae30e35a563a952a284f3f54d7f164ccd" > TIM6_IRQHandler< / a > Vector118< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gaf58f7701209700015c8090b7904e5e3e" > TIM7_IRQHandler< / a > Vector11C< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga59e42b422ce23eb466d067abbd0098ea" > DMA2_Ch1_IRQHandler< / a > Vector120< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gae86b2cc4ca778cf1922b28e0fa0957d8" > DMA2_Ch2_IRQHandler< / a > Vector124< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gad3cdd76c6987693a2aeeb7ceb0c470dc" > DMA2_Ch3_IRQHandler< / a > Vector128< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga83dd1dcc65ce982a3a8dd3c7c5fdd113" > DMA2_Ch4_IRQHandler< / a > Vector12C< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga6621b255e85340e1c387bb1813aae2c5" > DMA2_Ch5_IRQHandler< / a > Vector130< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga9c4edc08be5bb6da369dcfa6e8904e8c" > ETH_IRQHandler< / a > Vector134< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga37e42fa5ac97c2b11a675203babde70d" > ETH_WKUP_IRQHandler< / a > Vector138< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga0032aa0dc56f382b429d42689cd328b4" > CAN2_TX_IRQHandler< / a > Vector13C< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga1fd3a1d20f78823270967f8d8595850b" > CAN2_RX0_IRQHandler< / a > Vector140< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga43e709ac3b25920cf21b816943432a38" > CAN2_RX1_IRQHandler< / a > Vector144< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gac20ce4961b11559841c17ba37d472cd6" > CAN2_SCE_IRQHandler< / a > Vector148< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga102dbe2f5d20558c66a47ebe99b4eb59" > OTG_FS_IRQHandler< / a > Vector14C< / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga29204b81c265dd6e124fbcf12a2c8d6f" > STM32_SW< / a > STM32_SW_PLL< / td > < / tr >
< tr > < td class = "mdescLeft" > < / td > < td class = "mdescRight" > Main clock source selection. < a href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga29204b81c265dd6e124fbcf12a2c8d6f" > < / a > < br / > < / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga811cfbd049f0ab00976def9593849d32" > STM32_PLLSRC< / a > STM32_PLLSRC_PREDIV1< / td > < / tr >
< tr > < td class = "mdescLeft" > < / td > < td class = "mdescRight" > Clock source for the PLL. < a href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga811cfbd049f0ab00976def9593849d32" > < / a > < br / > < / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gad5d0895fa37888c0446d8caf0121e172" > STM32_PREDIV1SRC< / a > STM32_PREDIV1SRC_PLL2< / td > < / tr >
< tr > < td class = "mdescLeft" > < / td > < td class = "mdescRight" > PREDIV1 clock source. < a href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gad5d0895fa37888c0446d8caf0121e172" > < / a > < br / > < / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga698d65e5cf1da8551890221a2189bc88" > STM32_PREDIV1_VALUE< / a > 5< / td > < / tr >
< tr > < td class = "mdescLeft" > < / td > < td class = "mdescRight" > PREDIV1 division factor. < a href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga698d65e5cf1da8551890221a2189bc88" > < / a > < br / > < / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga0015fc8f73017358a7025ba57a265a11" > STM32_PLLMUL_VALUE< / a > 9< / td > < / tr >
< tr > < td class = "mdescLeft" > < / td > < td class = "mdescRight" > PLL multiplier value. < a href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga0015fc8f73017358a7025ba57a265a11" > < / a > < br / > < / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga8cfdffd3cdc62840504ae644898f3b7f" > STM32_PREDIV2_VALUE< / a > 5< / td > < / tr >
< tr > < td class = "mdescLeft" > < / td > < td class = "mdescRight" > PREDIV2 division factor. < a href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga8cfdffd3cdc62840504ae644898f3b7f" > < / a > < br / > < / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gaa203a24b063db3b89deefe370fcca6c9" > STM32_PLL2MUL_VALUE< / a > 8< / td > < / tr >
< tr > < td class = "mdescLeft" > < / td > < td class = "mdescRight" > PLL2 multiplier value. < a href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gaa203a24b063db3b89deefe370fcca6c9" > < / a > < br / > < / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga035ea0d8259c0f89306c6a7d344705f2" > STM32_HPRE< / a > STM32_HPRE_DIV1< / td > < / tr >
< tr > < td class = "mdescLeft" > < / td > < td class = "mdescRight" > AHB prescaler value. < a href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga035ea0d8259c0f89306c6a7d344705f2" > < / a > < br / > < / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga5f9c3734d5d06c9ccd5214af5c78c4f8" > STM32_PPRE1< / a > STM32_PPRE1_DIV2< / td > < / tr >
< tr > < td class = "mdescLeft" > < / td > < td class = "mdescRight" > APB1 prescaler value. < a href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga5f9c3734d5d06c9ccd5214af5c78c4f8" > < / a > < br / > < / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga3670f3886d02bb3010016bbf0db0db83" > STM32_PPRE2< / a > STM32_PPRE2_DIV2< / td > < / tr >
< tr > < td class = "mdescLeft" > < / td > < td class = "mdescRight" > APB2 prescaler value. < a href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga3670f3886d02bb3010016bbf0db0db83" > < / a > < br / > < / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga671b452f988ee9b64e128fad72f656e6" > STM32_ADCPRE< / a > STM32_ADCPRE_DIV4< / td > < / tr >
< tr > < td class = "mdescLeft" > < / td > < td class = "mdescRight" > ADC prescaler value. < a href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga671b452f988ee9b64e128fad72f656e6" > < / a > < br / > < / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga5b24026a48ef156dcb642b6e55a68e02" > STM32_MCO< / a > STM32_MCO_NOCLOCK< / td > < / tr >
< tr > < td class = "mdescLeft" > < / td > < td class = "mdescRight" > MCO pin setting. < a href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga5b24026a48ef156dcb642b6e55a68e02" > < / a > < br / > < / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga3cd0a9d4caf6456edd91d03068d2c1a6" > STM32_PREDIV1< / a > ((STM32_PREDIV1_VALUE - 1) < < 0)< / td > < / tr >
< tr > < td class = "mdescLeft" > < / td > < td class = "mdescRight" > PREDIV1 field. < a href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga3cd0a9d4caf6456edd91d03068d2c1a6" > < / a > < br / > < / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gadeffe5c986a74375f482ec77d2492865" > STM32_PREDIV2< / a > ((STM32_PREDIV2_VALUE - 1) < < 4)< / td > < / tr >
< tr > < td class = "mdescLeft" > < / td > < td class = "mdescRight" > PREDIV2 field. < a href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gadeffe5c986a74375f482ec77d2492865" > < / a > < br / > < / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga9889ca83d58a738f5758b4c300433f2a" > STM32_PLLMUL< / a > ((STM32_PLLMUL_VALUE - 2) < < 18)< / td > < / tr >
< tr > < td class = "mdescLeft" > < / td > < td class = "mdescRight" > PLLMUL field. < a href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga9889ca83d58a738f5758b4c300433f2a" > < / a > < br / > < / td > < / tr >
2010-11-22 05:53:37 +00:00
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga10d77f6e8d390a8a80ce68bfba91bf18" > STM32_PLL2MUL< / a > ((STM32_PLL2MUL_VALUE - 2) < < 8)< / td > < / tr >
2010-08-10 03:11:02 +00:00
< tr > < td class = "mdescLeft" > < / td > < td class = "mdescRight" > PLL2MUL field. < a href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga10d77f6e8d390a8a80ce68bfba91bf18" > < / a > < br / > < / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gae15492b9d08df4e93f8ce887edd47cfb" > STM32_PLL2CLKIN< / a > (STM32_HSECLK / STM32_PREDIV2_VALUE)< / td > < / tr >
< tr > < td class = "mdescLeft" > < / td > < td class = "mdescRight" > PLL2 input frequency. < a href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gae15492b9d08df4e93f8ce887edd47cfb" > < / a > < br / > < / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga42b9244074aa701666ee2062231c300d" > STM32_PLL2CLKOUT< / a > (STM32_PLL2CLKIN * STM32_PLL2MUL_VALUE)< / td > < / tr >
< tr > < td class = "mdescLeft" > < / td > < td class = "mdescRight" > PLL2 output clock frequency. < a href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga42b9244074aa701666ee2062231c300d" > < / a > < br / > < / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga84b992d7cf08100f320f3806b38063fd" > STM32_PREDIV1CLK< / a > STM32_PLL2CLKOUT< / td > < / tr >
< tr > < td class = "mdescLeft" > < / td > < td class = "mdescRight" > PREDIV1 input frequency. < a href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga84b992d7cf08100f320f3806b38063fd" > < / a > < br / > < / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga0b32be6543b6d55b0505288f268ddbe1" > STM32_PLLCLKIN< / a > (STM32_PREDIV1CLK / STM32_PREDIV1_VALUE)< / td > < / tr >
< tr > < td class = "mdescLeft" > < / td > < td class = "mdescRight" > PLL input clock frequency. < a href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga0b32be6543b6d55b0505288f268ddbe1" > < / a > < br / > < / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga551b4e93d2b76245c4b912ebfc54f9f3" > STM32_PLLCLKOUT< / a > (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)< / td > < / tr >
< tr > < td class = "mdescLeft" > < / td > < td class = "mdescRight" > PLL output clock frequency. < a href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga551b4e93d2b76245c4b912ebfc54f9f3" > < / a > < br / > < / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga81594f71c9bc1c1fde4e5207e5133777" > STM32_SYSCLK< / a > STM32_PLLCLKOUT< / td > < / tr >
< tr > < td class = "mdescLeft" > < / td > < td class = "mdescRight" > System clock source. < a href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga81594f71c9bc1c1fde4e5207e5133777" > < / a > < br / > < / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga918128f20df10ac68bd73605007bccf1" > STM32_HCLK< / a > (STM32_SYSCLK / 1)< / td > < / tr >
< tr > < td class = "mdescLeft" > < / td > < td class = "mdescRight" > AHB frequency. < a href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga918128f20df10ac68bd73605007bccf1" > < / a > < br / > < / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga79d8b0164de9c4437da78024b0ed94cb" > STM32_PCLK1< / a > (STM32_HCLK / 1)< / td > < / tr >
< tr > < td class = "mdescLeft" > < / td > < td class = "mdescRight" > APB1 frequency. < a href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga79d8b0164de9c4437da78024b0ed94cb" > < / a > < br / > < / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga2a19a811dd0dadfed94695a579997cec" > STM32_PCLK2< / a > (STM32_HCLK / 1)< / td > < / tr >
< tr > < td class = "mdescLeft" > < / td > < td class = "mdescRight" > APB2 frequency. < a href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga2a19a811dd0dadfed94695a579997cec" > < / a > < br / > < / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga62f559490a97de4746d6963d946e1e37" > STM32_ADCCLK< / a > (STM32_PCLK2 / 2)< / td > < / tr >
< tr > < td class = "mdescLeft" > < / td > < td class = "mdescRight" > ADC frequency. < a href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga62f559490a97de4746d6963d946e1e37" > < / a > < br / > < / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga8d53f5e948e73dc86013349c17f742f3" > STM32_TIMCLK1< / a > (STM32_PCLK1 * 1)< / td > < / tr >
< tr > < td class = "mdescLeft" > < / td > < td class = "mdescRight" > Timers 2, 3, 4, 5, 6, 7 clock. < a href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga8d53f5e948e73dc86013349c17f742f3" > < / a > < br / > < / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gacacec831f4aa8037c710ab56c7a73686" > STM32_TIMCLK2< / a > (STM32_PCLK2 * 1)< / td > < / tr >
< tr > < td class = "mdescLeft" > < / td > < td class = "mdescRight" > Timer 1 clock. < a href = "group___s_t_m32_f10_x___c_l___h_a_l.html#gacacec831f4aa8037c710ab56c7a73686" > < / a > < br / > < / td > < / tr >
< tr > < td class = "memItemLeft" align = "right" valign = "top" > #define < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga59b3885d4e2a3f63cfeb9ae58b6da563" > STM32_FLASHBITS< / a > 0x00000010< / td > < / tr >
< tr > < td class = "mdescLeft" > < / td > < td class = "mdescRight" > Flash settings. < a href = "group___s_t_m32_f10_x___c_l___h_a_l.html#ga59b3885d4e2a3f63cfeb9ae58b6da563" > < / a > < br / > < / td > < / tr >
< / table >
< hr / > < a name = "_details" > < / a > < h2 > Detailed Description< / h2 >
< p > STM32F10x Connectivity Line HAL subsystem low level driver header. < / p >
< p > Definition in file < a class = "el" href = "hal__lld__f105__f107_8h_source.html" > hal_lld_f105_f107.h< / a > .< / p >
< / div >
< hr size = "1" > < address style = "text-align: right;" > < small >
2010-11-30 04:54:43 +00:00
Generated on Sun Nov 28 2010 14:09:50 for ChibiOS/RT by < a href = "http://www.doxygen.org/index.html" > < img src = "doxygen.png" alt = "doxygen" align = "middle" border = "0" > < / a > 1.7.1< / small > < / address >
2010-08-10 03:11:02 +00:00
< / body >
< / html >