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Upgrade Chopstx
This commit is contained in:
NIIBE Yutaka
parent
f89b9ef8b7
commit
91222b5e22
@ -1,3 +1,8 @@
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2014-12-11 Niibe Yutaka <gniibe@fsij.org>
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* chopstx: Upgrade to 0.04.
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* src/syc.c: Update from 0.04.
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2014-12-10 Niibe Yutaka <gniibe@fsij.org>
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* src/ecc-cdh.c: Remove as smartcard only does
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2
chopstx
2
chopstx
@ -1 +1 @@
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Subproject commit f344d926c1afafb9368a19e45db40fc312928a3c
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Subproject commit 23893d9b73ebc28ff111d21827122677c27bee55
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69
src/sys.c
69
src/sys.c
@ -1,7 +1,7 @@
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/*
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* sys.c - system routines for the initial page for STM32F103.
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*
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* Copyright (C) 2013 Flying Stone Technology
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* Copyright (C) 2013, 2014 Flying Stone Technology
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* Author: NIIBE Yutaka <gniibe@fsij.org>
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*
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* Copying and distribution of this file, with or without modification,
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@ -24,7 +24,9 @@
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#define STM32_USB_IRQ_PRIORITY 11
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#define STM32_SW_HSI (0 << 0)
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#define STM32_SW_PLL (2 << 0)
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#define STM32_PLLSRC_HSI (0 << 16)
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#define STM32_PLLSRC_HSE (1 << 16)
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#define STM32_PLLXTPRE_DIV1 (0 << 17)
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@ -32,6 +34,7 @@
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#define STM32_HPRE_DIV1 (0 << 4)
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#define STM32_PPRE1_DIV1 (0 << 8)
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#define STM32_PPRE1_DIV2 (4 << 8)
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#define STM32_PPRE2_DIV1 (0 << 11)
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@ -44,23 +47,23 @@
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#define STM32_MCO_NOCLOCK (0 << 24)
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#define STM32_SW STM32_SW_PLL
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#define STM32_PLLSRC STM32_PLLSRC_HSE
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#define STM32_HPRE STM32_HPRE_DIV1
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#define STM32_PPRE1 STM32_PPRE1_DIV2
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#define STM32_PLLSRC STM32_PLLSRC_HSE
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#define STM32_FLASHBITS 0x00000012
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#define STM32_PLLCLKIN (STM32_HSECLK / 1)
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#define STM32_SW STM32_SW_PLL
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#define STM32_HPRE STM32_HPRE_DIV1
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#define STM32_PPRE2 STM32_PPRE2_DIV1
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#define STM32_ADCPRE STM32_ADCPRE_DIV6
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#define STM32_MCOSEL STM32_MCO_NOCLOCK
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#define STM32_USBPRE STM32_USBPRE_DIV1P5
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#define STM32_PLLCLKIN (STM32_HSECLK / 1)
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#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18)
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#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
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#define STM32_SYSCLK STM32_PLLCLKOUT
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#define STM32_HCLK (STM32_SYSCLK / 1)
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#define STM32_FLASHBITS 0x00000012
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struct NVIC {
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uint32_t ISER[8];
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uint32_t unused1[24];
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@ -92,8 +95,10 @@ nvic_enable_vector (uint32_t n, uint32_t prio)
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#define PERIPH_BASE 0x40000000
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#define APBPERIPH_BASE PERIPH_BASE
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#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
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#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
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#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
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struct RCC {
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volatile uint32_t CR;
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@ -127,6 +132,18 @@ static struct RCC *const RCC = ((struct RCC *const)RCC_BASE);
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#define RCC_AHBENR_CRCEN 0x0040
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#define RCC_APB2RSTR_AFIORST 0x00000001
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#define RCC_APB2RSTR_IOPARST 0x00000004
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#define RCC_APB2RSTR_IOPBRST 0x00000008
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#define RCC_APB2RSTR_IOPCRST 0x00000010
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#define RCC_APB2RSTR_IOPDRST 0x00000020
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#define RCC_APB2ENR_AFIOEN 0x00000001
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#define RCC_APB2ENR_IOPAEN 0x00000004
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#define RCC_APB2ENR_IOPBEN 0x00000008
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#define RCC_APB2ENR_IOPCEN 0x00000010
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#define RCC_APB2ENR_IOPDEN 0x00000020
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struct FLASH {
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volatile uint32_t ACR;
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volatile uint32_t KEYR;
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@ -149,7 +166,8 @@ clock_init (void)
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RCC->CR |= RCC_CR_HSION;
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while (!(RCC->CR & RCC_CR_HSIRDY))
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;
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RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION;
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/* Reset HSEON, HSEBYP, CSSON, and PLLON, not touching RCC_CR_HSITRIM */
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RCC->CR &= (RCC_CR_HSITRIM | RCC_CR_HSION);
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RCC->CFGR = 0;
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
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;
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@ -169,6 +187,10 @@ clock_init (void)
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RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE
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| STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
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/*
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* We don't touch RCC->CR2, RCC->CFGR2, RCC->CFGR3, and RCC->CIR.
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*/
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/* Flash setup */
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FLASH->ACR = STM32_FLASHBITS;
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@ -181,18 +203,6 @@ clock_init (void)
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;
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}
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#define RCC_APB2RSTR_AFIORST 0x00000001
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#define RCC_APB2RSTR_IOPARST 0x00000004
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#define RCC_APB2RSTR_IOPBRST 0x00000008
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#define RCC_APB2RSTR_IOPCRST 0x00000010
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#define RCC_APB2RSTR_IOPDRST 0x00000020
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#define RCC_APB2ENR_AFIOEN 0x00000001
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#define RCC_APB2ENR_IOPAEN 0x00000004
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#define RCC_APB2ENR_IOPBEN 0x00000008
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#define RCC_APB2ENR_IOPCEN 0x00000010
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#define RCC_APB2ENR_IOPDEN 0x00000020
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struct AFIO
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{
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@ -231,8 +241,10 @@ struct GPIO {
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#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
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#define GPIOE ((struct GPIO *) GPIOE_BASE)
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static struct GPIO *const GPIO_USB = ((struct GPIO *const) GPIO_USB_BASE);
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static struct GPIO *const GPIO_LED = ((struct GPIO *const) GPIO_LED_BASE);
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#ifdef GPIO_USB_BASE
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static struct GPIO *const GPIO_USB = ((struct GPIO *const) GPIO_USB_BASE);
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#endif
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#ifdef GPIO_OTHER_BASE
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static struct GPIO *const GPIO_OTHER = ((struct GPIO *const) GPIO_OTHER_BASE);
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#endif
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@ -241,8 +253,8 @@ static void
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gpio_init (void)
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{
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/* Enable GPIO clock. */
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RCC->APB2ENR |= RCC_APB2ENR_IOP_EN;
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RCC->APB2RSTR = RCC_APB2RSTR_IOP_RST;
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RCC->APB2ENR |= RCC_ENR_IOP_EN;
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RCC->APB2RSTR = RCC_RSTR_IOP_RST;
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RCC->APB2RSTR = 0;
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#ifdef AFIO_MAPR_SOMETHING
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@ -578,9 +590,12 @@ reset (void)
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{
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extern const unsigned long *FT0, *FT1, *FT2;
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/*
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* This code may not be at the start of flash ROM, because of DFU.
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* So, we take the address from PC.
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*/
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asm volatile ("cpsid i\n\t" /* Mask all interrupts. */
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"mov.w r0, #0xed00\n\t" /* r0 = SCR */
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"movt r0, #0xe000\n\t"
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"ldr r0, 1f\n\t" /* r0 = SCR */
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"mov r1, pc\n\t" /* r1 = (PC + 0x1000) & ~0x0fff */
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"mov r2, #0x1000\n\t"
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"add r1, r1, r2\n\t"
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@ -590,7 +605,9 @@ reset (void)
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"ldr r0, [r1], #4\n\t"
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"msr MSP, r0\n\t" /* Main (exception handler) stack. */
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"ldr r0, [r1]\n\t" /* Reset handler. */
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"bx r0\n"
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"bx r0\n\t"
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".align 2\n"
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"1: .word 0xe000ed00"
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: /* no output */ : /* no input */ : "memory");
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/* Never reach here. */
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