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SPI flash support starts for FST-01
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@ -1,3 +1,8 @@
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2012-07-06 Niibe Yutaka <gniibe@fsij.org>
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* boards/FST_01/board.h (VAL_GPIOACRL): Change for SPI flash.
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* tool/stlinkv2.py (stlinkv2.setup_gpio): Likewise.
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2012-07-05 Niibe Yutaka <gniibe@fsij.org>
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* src/call-rsa.c (rsa_sign, rsa_decrypt): Don't need to setup N.
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@ -97,12 +97,16 @@
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* PA0 - input with pull-up (TIM2_CH1)
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* PA1 - input with pull-down (TIM2_CH2)
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* PA2 - input with pull-up (TIM2_CH3)
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* PA4 - Push pull output (SPI1_NSS)
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* PA5 - Alternate Push pull output (SPI1_SCK)
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* PA6 - Alternate Push pull output (SPI1_MISO)
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* PA7 - Alternate Push pull output (SPI1_MOSI)
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* PA11 - input with pull-up (USBDM)
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* PA12 - input with pull-up (USBDP)
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* Everything input with pull-up except:
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* PA10 - Push pull output (USB 1:ON 0:OFF)
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*/
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#define VAL_GPIOACRL 0x88888888 /* PA7...PA0 */
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#define VAL_GPIOACRL 0xBBB38888 /* PA7...PA0 */
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#define VAL_GPIOACRH 0x88888388 /* PA15...PA8 */
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#define VAL_GPIOAODR 0xFFFFFFFD
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@ -217,19 +217,22 @@ class stlinkv2(object):
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# For FST-01-00 and FST-01: LED on, USB off
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def setup_gpio(self):
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apb2enr = self.read_memory_u32(0x40021018)
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apb2enr = apb2enr | 4 | 8 # Enable port A and B
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apb2enr = apb2enr | 4 | 8 | 0x1000 # Enable port A, port B, and SPI1
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self.write_memory_u32(0x40021018, apb2enr) # RCC->APB2ENR
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self.write_memory_u32(0x4002100c, 4|8) # RCC->APB2RSTR
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self.write_memory_u32(0x4002100c, 4|8|0x1000) # RCC->APB2RSTR
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self.write_memory_u32(0x4002100c, 0)
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self.write_memory_u32(GPIOA+0x0c, 0xfffffbff) # ODR
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self.write_memory_u32(GPIOA+0x04, 0x88888383) # CRH
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self.write_memory_u32(GPIOA+0x00, 0x88888888) # CRL
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self.write_memory_u32(GPIOA+0x00, 0xBBB38888) # CRL
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self.write_memory_u32(GPIOB+0x0c, 0xffffffff) # ODR
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self.write_memory_u32(GPIOB+0x04, 0x88888883) # CRH
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self.write_memory_u32(GPIOB+0x00, 0x88888888) # CRL
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# For FST-01-00 and FST-01: LED off, USB off
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def finish_gpio(self):
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apb2enr = self.read_memory_u32(0x40021018)
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apb2enr = apb2enr & ~(4 | 8 | 0x1000)
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self.write_memory_u32(0x40021018, apb2enr) # RCC->APB2ENR
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self.write_memory_u32(GPIOA+0x0c, 0xfffffaff) # ODR
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self.write_memory_u32(GPIOB+0x0c, 0xfffffffe) # ODR
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