ChibiOS/RT Architecture - Reference Manual - Guides |
00001 /* 00002 ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. 00003 00004 This file is part of ChibiOS/RT. 00005 00006 ChibiOS/RT is free software; you can redistribute it and/or modify 00007 it under the terms of the GNU General Public License as published by 00008 the Free Software Foundation; either version 3 of the License, or 00009 (at your option) any later version. 00010 00011 ChibiOS/RT is distributed in the hope that it will be useful, 00012 but WITHOUT ANY WARRANTY; without even the implied warranty of 00013 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00014 GNU General Public License for more details. 00015 00016 You should have received a copy of the GNU General Public License 00017 along with this program. If not, see <http://www.gnu.org/licenses/>. 00018 00019 --- 00020 00021 A special exception to the GPL can be applied should you wish to distribute 00022 a combined work that includes ChibiOS/RT, without being obliged to provide 00023 the source code for any proprietary components. See the file exception.txt 00024 for full details of how and when the exception can be applied. 00025 */ 00026 00027 /* 00028 * Parts of this file are borrowed by the Linux include file linux/mii.h: 00029 * Copyright (C) 1996, 1999, 2001 David S. Miller (davem@redhat.com) 00030 */ 00031 00032 /*-* 00033 * @file mii.h 00034 * @brief MII Driver macros and structures. 00035 * 00036 * @addtogroup MII 00037 * @{ 00038 */ 00039 00040 #ifndef _MII_H_ 00041 #define _MII_H_ 00042 00043 /* 00044 * Generic MII registers. Note, not all registers are present on all PHY 00045 * devices and some extra registers may be present. 00046 */ 00047 #define MII_BMCR 0x00 /**< Basic mode control register. */ 00048 #define MII_BMSR 0x01 /**< Basic mode status register. */ 00049 #define MII_PHYSID1 0x02 /**< PHYS ID 1. */ 00050 #define MII_PHYSID2 0x03 /**< PHYS ID 2. */ 00051 #define MII_ADVERTISE 0x04 /**< Advertisement control reg. */ 00052 #define MII_LPA 0x05 /**< Link partner ability reg. */ 00053 #define MII_EXPANSION 0x06 /**< Expansion register. */ 00054 #define MII_CTRL1000 0x09 /**< 1000BASE-T control. */ 00055 #define MII_STAT1000 0x0a /**< 1000BASE-T status. */ 00056 #define MII_ESTATUS 0x0f /**< Extended Status. */ 00057 #define MII_DCOUNTER 0x12 /**< Disconnect counter. */ 00058 #define MII_FCSCOUNTER 0x13 /**< False carrier counter. */ 00059 #define MII_NWAYTEST 0x14 /**< N-way auto-neg test reg. */ 00060 #define MII_RERRCOUNTER 0x15 /**< Receive error counter. */ 00061 #define MII_SREVISION 0x16 /**< Silicon revision. */ 00062 #define MII_RESV1 0x17 /**< Reserved. */ 00063 #define MII_LBRERROR 0x18 /**< Lpback, rx, bypass error. */ 00064 #define MII_PHYADDR 0x19 /**< PHY address. */ 00065 #define MII_RESV2 0x1a /**< Reserved. */ 00066 #define MII_TPISTATUS 0x1b /**< TPI status for 10mbps. */ 00067 #define MII_NCONFIG 0x1c /**< Network interface config. */ 00068 00069 /* 00070 * Basic mode control register. 00071 */ 00072 #define BMCR_RESV 0x003f /**< Unused. */ 00073 #define BMCR_SPEED1000 0x0040 /**< MSB of Speed (1000). */ 00074 #define BMCR_CTST 0x0080 /**< Collision test. */ 00075 #define BMCR_FULLDPLX 0x0100 /**< Full duplex. */ 00076 #define BMCR_ANRESTART 0x0200 /**< Auto negotiation restart. */ 00077 #define BMCR_ISOLATE 0x0400 /**< Disconnect DP83840 from MII. */ 00078 #define BMCR_PDOWN 0x0800 /**< Powerdown. */ 00079 #define BMCR_ANENABLE 0x1000 /**< Enable auto negotiation. */ 00080 #define BMCR_SPEED100 0x2000 /**< Select 100Mbps. */ 00081 #define BMCR_LOOPBACK 0x4000 /**< TXD loopback bits. */ 00082 #define BMCR_RESET 0x8000 /**< Reset. */ 00083 00084 /* 00085 * Basic mode status register. 00086 */ 00087 #define BMSR_ERCAP 0x0001 /**< Ext-reg capability. */ 00088 #define BMSR_JCD 0x0002 /**< Jabber detected. */ 00089 #define BMSR_LSTATUS 0x0004 /**< Link status. */ 00090 #define BMSR_ANEGCAPABLE 0x0008 /**< Able to do auto-negotiation. */ 00091 #define BMSR_RFAULT 0x0010 /**< Remote fault detected. */ 00092 #define BMSR_ANEGCOMPLETE 0x0020 /**< Auto-negotiation complete. */ 00093 #define BMSR_RESV 0x00c0 /**< Unused. */ 00094 #define BMSR_ESTATEN 0x0100 /**< Extended Status in R15. */ 00095 #define BMSR_100HALF2 0x0200 /**< Can do 100BASE-T2 HDX. */ 00096 #define BMSR_100FULL2 0x0400 /**< Can do 100BASE-T2 FDX. */ 00097 #define BMSR_10HALF 0x0800 /**< Can do 10mbps, half-duplex. */ 00098 #define BMSR_10FULL 0x1000 /**< Can do 10mbps, full-duplex. */ 00099 #define BMSR_100HALF 0x2000 /**< Can do 100mbps, half-duplex. */ 00100 #define BMSR_100FULL 0x4000 /**< Can do 100mbps, full-duplex. */ 00101 #define BMSR_100BASE4 0x8000 /**< Can do 100mbps, 4k packets. */ 00102 00103 /* 00104 * Advertisement control register. 00105 */ 00106 #define ADVERTISE_SLCT 0x001f /**< Selector bits. */ 00107 #define ADVERTISE_CSMA 0x0001 /**< Only selector supported. */ 00108 #define ADVERTISE_10HALF 0x0020 /**< Try for 10mbps half-duplex. */ 00109 #define ADVERTISE_1000XFULL 0x0020 /**< Try for 1000BASE-X full-duplex.*/ 00110 #define ADVERTISE_10FULL 0x0040 /**< Try for 10mbps full-duplex. */ 00111 #define ADVERTISE_1000XHALF 0x0040 /**< Try for 1000BASE-X half-duplex.*/ 00112 #define ADVERTISE_100HALF 0x0080 /**< Try for 100mbps half-duplex. */ 00113 #define ADVERTISE_1000XPAUSE 0x0080 /**< Try for 1000BASE-X pause. */ 00114 #define ADVERTISE_100FULL 0x0100 /**< Try for 100mbps full-duplex. */ 00115 #define ADVERTISE_1000XPSE_ASYM 0x0100 /**< Try for 1000BASE-X asym pause. */ 00116 #define ADVERTISE_100BASE4 0x0200 /**< Try for 100mbps 4k packets. */ 00117 #define ADVERTISE_PAUSE_CAP 0x0400 /**< Try for pause. */ 00118 #define ADVERTISE_PAUSE_ASYM 0x0800 /**< Try for asymetric pause. */ 00119 #define ADVERTISE_RESV 0x1000 /**< Unused. */ 00120 #define ADVERTISE_RFAULT 0x2000 /**< Say we can detect faults. */ 00121 #define ADVERTISE_LPACK 0x4000 /**< Ack link partners response. */ 00122 #define ADVERTISE_NPAGE 0x8000 /**< Next page bit. */ 00123 00124 #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ 00125 ADVERTISE_CSMA) 00126 #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ 00127 ADVERTISE_100HALF | ADVERTISE_100FULL) 00128 00129 /* 00130 * Link partner ability register. 00131 */ 00132 #define LPA_SLCT 0x001f /**< Same as advertise selector. */ 00133 #define LPA_10HALF 0x0020 /**< Can do 10mbps half-duplex. */ 00134 #define LPA_1000XFULL 0x0020 /**< Can do 1000BASE-X full-duplex. */ 00135 #define LPA_10FULL 0x0040 /**< Can do 10mbps full-duplex. */ 00136 #define LPA_1000XHALF 0x0040 /**< Can do 1000BASE-X half-duplex. */ 00137 #define LPA_100HALF 0x0080 /**< Can do 100mbps half-duplex. */ 00138 #define LPA_1000XPAUSE 0x0080 /**< Can do 1000BASE-X pause. */ 00139 #define LPA_100FULL 0x0100 /**< Can do 100mbps full-duplex. */ 00140 #define LPA_1000XPAUSE_ASYM 0x0100 /**< Can do 1000BASE-X pause asym. */ 00141 #define LPA_100BASE4 0x0200 /**< Can do 100mbps 4k packets. */ 00142 #define LPA_PAUSE_CAP 0x0400 /**< Can pause. */ 00143 #define LPA_PAUSE_ASYM 0x0800 /**< Can pause asymetrically. */ 00144 #define LPA_RESV 0x1000 /**< Unused. */ 00145 #define LPA_RFAULT 0x2000 /**< Link partner faulted. */ 00146 #define LPA_LPACK 0x4000 /**< Link partner acked us. */ 00147 #define LPA_NPAGE 0x8000 /**< Next page bit. */ 00148 00149 #define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) 00150 #define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) 00151 00152 /* 00153 * Expansion register for auto-negotiation. 00154 */ 00155 #define EXPANSION_NWAY 0x0001 /**< Can do N-way auto-nego. */ 00156 #define EXPANSION_LCWP 0x0002 /**< Got new RX page code word. */ 00157 #define EXPANSION_ENABLENPAGE 0x0004 /**< This enables npage words. */ 00158 #define EXPANSION_NPCAPABLE 0x0008 /**< Link partner supports npage. */ 00159 #define EXPANSION_MFAULTS 0x0010 /**< Multiple faults detected. */ 00160 #define EXPANSION_RESV 0xffe0 /**< Unused. */ 00161 00162 #define ESTATUS_1000_TFULL 0x2000 /**< Can do 1000BT Full. */ 00163 #define ESTATUS_1000_THALF 0x1000 /**< Can do 1000BT Half. */ 00164 00165 /* 00166 * N-way test register. 00167 */ 00168 #define NWAYTEST_RESV1 0x00ff /**< Unused. */ 00169 #define NWAYTEST_LOOPBACK 0x0100 /**< Enable loopback for N-way. */ 00170 #define NWAYTEST_RESV2 0xfe00 /**< Unused. */ 00171 00172 /* 00173 * 1000BASE-T Control register. 00174 */ 00175 #define ADVERTISE_1000FULL 0x0200 /**< Advertise 1000BASE-T full duplex.*/ 00176 #define ADVERTISE_1000HALF 0x0100 /**< Advertise 1000BASE-T half duplex.*/ 00177 00178 /* 00179 * 1000BASE-T Status register. 00180 */ 00181 #define LPA_1000LOCALRXOK 0x2000 /**< Link partner local receiver status.*/ 00182 #define LPA_1000REMRXOK 0x1000 /**< Link partner remote receiver status.*/ 00183 #define LPA_1000FULL 0x0800 /**< Link partner 1000BASE-T full duplex.*/ 00184 #define LPA_1000HALF 0x0400 /**< Link partner 1000BASE-T half duplex.*/ 00185 00186 /* 00187 * PHY identifiers. 00188 */ 00189 #define MII_DM9161_ID 0x0181b8a0 00190 #define MII_AM79C875_ID 0x00225540 00191 #define MII_KS8721_ID 0x00221610 00192 00193 #endif /* _MII_H_ */ 00194 00195 /*-* @} */