ChibiOS/RT Architecture - Reference Manual - Guides |
00001 /* 00002 ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. 00003 00004 This file is part of ChibiOS/RT. 00005 00006 ChibiOS/RT is free software; you can redistribute it and/or modify 00007 it under the terms of the GNU General Public License as published by 00008 the Free Software Foundation; either version 3 of the License, or 00009 (at your option) any later version. 00010 00011 ChibiOS/RT is distributed in the hope that it will be useful, 00012 but WITHOUT ANY WARRANTY; without even the implied warranty of 00013 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00014 GNU General Public License for more details. 00015 00016 You should have received a copy of the GNU General Public License 00017 along with this program. If not, see <http://www.gnu.org/licenses/>. 00018 00019 --- 00020 00021 A special exception to the GPL can be applied should you wish to distribute 00022 a combined work that includes ChibiOS/RT, without being obliged to provide 00023 the source code for any proprietary components. See the file exception.txt 00024 for full details of how and when the exception can be applied. 00025 */ 00026 00027 /** 00028 * @file ARMCMx/nvic.h 00029 * @brief Cortex-Mx NVIC support macros and structures. 00030 * 00031 * @addtogroup ARMCMx_NVIC 00032 * @{ 00033 */ 00034 00035 #ifndef _NVIC_H_ 00036 #define _NVIC_H_ 00037 00038 /* 00039 * System vector constants for @p NVICSetSystemHandlerPriority(). 00040 */ 00041 #define HANDLER_MEM_MANAGE 0 /**< MEM MANAGE vector id. */ 00042 #define HANDLER_BUS_FAULT 1 /**< BUS FAULT vector id. */ 00043 #define HANDLER_USAGE_FAULT 2 /**< USAGE FAULT vector id. */ 00044 #define HANDLER_RESERVED_3 3 00045 #define HANDLER_RESERVED_4 4 00046 #define HANDLER_RESERVED_5 5 00047 #define HANDLER_RESERVED_6 6 00048 #define HANDLER_SVCALL 7 /**< SVCALL vector id. */ 00049 #define HANDLER_DEBUG_MONITOR 8 /**< DEBUG MONITOR vector id. */ 00050 #define HANDLER_RESERVED_9 9 00051 #define HANDLER_PENDSV 10 /**< PENDSV vector id. */ 00052 #define HANDLER_SYSTICK 11 /**< SYS TCK vector id. */ 00053 00054 typedef volatile uint8_t IOREG8; /**< 8 bits I/O register type. */ 00055 typedef volatile uint32_t IOREG32; /**< 32 bits I/O register type. */ 00056 00057 /** 00058 * @brief NVIC ITCR register. 00059 */ 00060 #define NVIC_ITCR (*((IOREG32 *)0xE000E004)) 00061 00062 /** 00063 * @brief NVIC STIR register. 00064 */ 00065 #define NVIC_STIR (*((IOREG32 *)0xE000EF00)) 00066 00067 /** 00068 * @brief Structure representing the SYSTICK I/O space. 00069 */ 00070 typedef struct { 00071 IOREG32 CSR; 00072 IOREG32 RVR; 00073 IOREG32 CVR; 00074 IOREG32 CBVR; 00075 } CM3_ST; 00076 00077 /** 00078 * @brief SYSTICK peripheral base address. 00079 */ 00080 #define STBase ((CM3_ST *)0xE000E010) 00081 #define ST_CSR (STBase->CSR) 00082 #define ST_RVR (STBase->RVR) 00083 #define ST_CVR (STBase->CVR) 00084 #define ST_CBVR (STBase->CBVR) 00085 00086 #define CSR_ENABLE_MASK (0x1 << 0) 00087 #define ENABLE_OFF_BITS (0 << 0) 00088 #define ENABLE_ON_BITS (1 << 0) 00089 #define CSR_TICKINT_MASK (0x1 << 1) 00090 #define TICKINT_DISABLED_BITS (0 << 1) 00091 #define TICKINT_ENABLED_BITS (1 << 1) 00092 #define CSR_CLKSOURCE_MASK (0x1 << 2) 00093 #define CLKSOURCE_EXT_BITS (0 << 2) 00094 #define CLKSOURCE_CORE_BITS (1 << 2) 00095 #define CSR_COUNTFLAG_MASK (0x1 << 16) 00096 00097 #define RVR_RELOAD_MASK (0xFFFFFF << 0) 00098 00099 #define CVR_CURRENT_MASK (0xFFFFFF << 0) 00100 00101 #define CBVR_TENMS_MASK (0xFFFFFF << 0) 00102 #define CBVR_SKEW_MASK (0x1 << 30) 00103 #define CBVR_NOREF_MASK (0x1 << 31) 00104 00105 /** 00106 * @brief Structure representing the NVIC I/O space. 00107 */ 00108 typedef struct { 00109 IOREG32 ISER[8]; 00110 IOREG32 unused1[24]; 00111 IOREG32 ICER[8]; 00112 IOREG32 unused2[24]; 00113 IOREG32 ISPR[8]; 00114 IOREG32 unused3[24]; 00115 IOREG32 ICPR[8]; 00116 IOREG32 unused4[24]; 00117 IOREG32 IABR[8]; 00118 IOREG32 unused5[56]; 00119 IOREG32 IPR[60]; 00120 } CM3_NVIC; 00121 00122 /** 00123 * @brief NVIC peripheral base address. 00124 */ 00125 #define NVICBase ((CM3_NVIC *)0xE000E100) 00126 #define NVIC_ISER(n) (NVICBase->ISER[n]) 00127 #define NVIC_ICER(n) (NVICBase->ICER[n]) 00128 #define NVIC_ISPR(n) (NVICBase->ISPR[n]) 00129 #define NVIC_ICPR(n) (NVICBase->ICPR[n]) 00130 #define NVIC_IABR(n) (NVICBase->IABR[n]) 00131 #define NVIC_IPR(n) (NVICBase->IPR[n]) 00132 00133 /** 00134 * @brief Structure representing the System Control Block I/O space. 00135 */ 00136 typedef struct { 00137 IOREG32 CPUID; 00138 IOREG32 ICSR; 00139 IOREG32 VTOR; 00140 IOREG32 AIRCR; 00141 IOREG32 SCR; 00142 IOREG32 CCR; 00143 IOREG32 SHPR[3]; 00144 IOREG32 SHCSR; 00145 IOREG32 CFSR; 00146 IOREG32 HFSR; 00147 IOREG32 DFSR; 00148 IOREG32 MMFAR; 00149 IOREG32 BFAR; 00150 IOREG32 AFSR; 00151 } CM3_SCB; 00152 00153 /** 00154 * @brief SCB peripheral base address. 00155 */ 00156 #define SCBBase ((CM3_SCB *)0xE000ED00) 00157 #define SCB_CPUID (SCBBase->CPUID) 00158 #define SCB_ICSR (SCBBase->ICSR) 00159 #define SCB_VTOR (SCBBase->VTOR) 00160 #define SCB_AIRCR (SCBBase->AIRCR) 00161 #define SCB_SCR (SCBBase->SCR) 00162 #define SCB_CCR (SCBBase->CCR) 00163 #define SCB_SHPR(n) (SCBBase->SHPR[n]) 00164 #define SCB_SHCSR (SCBBase->SHCSR) 00165 #define SCB_CFSR (SCBBase->CFSR) 00166 #define SCB_HFSR (SCBBase->HFSR) 00167 #define SCB_DFSR (SCBBase->DFSR) 00168 #define SCB_MMFAR (SCBBase->MMFAR) 00169 #define SCB_BFAR (SCBBase->BFAR) 00170 #define SCB_AFSR (SCBBase->AFSR) 00171 00172 #define ICSR_VECTACTIVE_MASK (0x1FF << 0) 00173 #define ICSR_RETTOBASE (0x1 << 11) 00174 #define ICSR_VECTPENDING_MASK (0x1FF << 12) 00175 #define ICSR_ISRPENDING (0x1 << 22) 00176 #define ICSR_ISRPREEMPT (0x1 << 23) 00177 #define ICSR_PENDSTCLR (0x1 << 25) 00178 #define ICSR_PENDSTSET (0x1 << 26) 00179 #define ICSR_PENDSVCLR (0x1 << 27) 00180 #define ICSR_PENDSVSET (0x1 << 28) 00181 #define ICSR_NMIPENDSET (0x1 << 31) 00182 00183 #define AIRCR_VECTKEY 0x05FA0000 00184 #define AIRCR_PRIGROUP_MASK (0x7 << 8) 00185 #define AIRCR_PRIGROUP(n) ((n) << 8) 00186 00187 #ifdef __cplusplus 00188 extern "C" { 00189 #endif 00190 void NVICEnableVector(uint32_t n, uint32_t prio); 00191 void NVICDisableVector(uint32_t n); 00192 void NVICSetSystemHandlerPriority(uint32_t handler, uint32_t prio); 00193 #ifdef __cplusplus 00194 } 00195 #endif 00196 00197 #endif /* _NVIC_H_ */ 00198 00199 /** @} */