ChibiOS/RT Architecture - Reference Manual - Guides |
00001 /* 00002 ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. 00003 00004 This file is part of ChibiOS/RT. 00005 00006 ChibiOS/RT is free software; you can redistribute it and/or modify 00007 it under the terms of the GNU General Public License as published by 00008 the Free Software Foundation; either version 3 of the License, or 00009 (at your option) any later version. 00010 00011 ChibiOS/RT is distributed in the hope that it will be useful, 00012 but WITHOUT ANY WARRANTY; without even the implied warranty of 00013 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00014 GNU General Public License for more details. 00015 00016 You should have received a copy of the GNU General Public License 00017 along with this program. If not, see <http://www.gnu.org/licenses/>. 00018 00019 --- 00020 00021 A special exception to the GPL can be applied should you wish to distribute 00022 a combined work that includes ChibiOS/RT, without being obliged to provide 00023 the source code for any proprietary components. See the file exception.txt 00024 for full details of how and when the exception can be applied. 00025 */ 00026 00027 /** 00028 * @file lpc214x.h 00029 * @brief LPC214x register definitions. 00030 */ 00031 00032 #ifndef _LPC214X_H_ 00033 #define _LPC214X_H_ 00034 00035 typedef volatile uint8_t IOREG8; 00036 typedef volatile uint16_t IOREG16; 00037 typedef volatile uint32_t IOREG32; 00038 00039 /* 00040 * System. 00041 */ 00042 #define MEMMAP (*((IOREG32 *)0xE01FC040)) 00043 #define PCON (*((IOREG32 *)0xE01FC0C0)) 00044 #define PCONP (*((IOREG32 *)0xE01FC0C4)) 00045 #define VPBDIV (*((IOREG32 *)0xE01FC100)) 00046 #define EXTINT (*((IOREG32 *)0xE01FC140)) 00047 #define INTWAKE (*((IOREG32 *)0xE01FC144)) 00048 #define EXTMODE (*((IOREG32 *)0xE01FC148)) 00049 #define EXTPOLAR (*((IOREG32 *)0xE01FC14C)) 00050 #define RSID (*((IOREG32 *)0xE01FC180)) 00051 #define CSPR (*((IOREG32 *)0xE01FC184)) 00052 #define SCS (*((IOREG32 *)0xE01FC1A0)) 00053 00054 #define VPD_D4 0 00055 #define VPD_D1 1 00056 #define VPD_D2 2 00057 #define VPD_RESERVED 3 00058 00059 #define PCTIM0 (1 << 1) 00060 #define PCTIM1 (1 << 2) 00061 #define PCUART0 (1 << 3) 00062 #define PCUART1 (1 << 4) 00063 #define PCPWM0 (1 << 5) 00064 #define PCI2C0 (1 << 7) 00065 #define PCSPI0 (1 << 8) 00066 #define PCRTC (1 << 9) 00067 #define PCSPI1 (1 << 10) 00068 #define PCAD0 (1 << 12) 00069 #define PCI2C1 (1 << 19) 00070 #define PCAD1 (1 << 20) 00071 #define PCUSB (1 << 31) 00072 #define PCALL (PCTIM0 | PCTIM1 | PCUART0 | PCUART1 | \ 00073 PCPWM0 | PCI2C0 | PCSPI0 | PCRTC | PCSPI1 | \ 00074 PCAD0 | PCI2C1 | PCAD1 | PCUSB) 00075 00076 #define EINT0 1 00077 #define EINT1 2 00078 #define EINT2 4 00079 #define EINT3 8 00080 00081 #define EXTWAKE0 1 00082 #define EXTWAKE1 2 00083 #define EXTWAKE2 4 00084 #define EXTWAKE3 8 00085 #define USBWAKE 0x20 00086 #define BODWAKE 0x4000 00087 #define RTCWAKE 0x8000 00088 00089 #define EXTMODE0 1 00090 #define EXTMODE1 2 00091 #define EXTMODE2 4 00092 #define EXTMODE3 8 00093 00094 #define EXTPOLAR0 1 00095 #define EXTPOLAR1 2 00096 #define EXTPOLAR2 4 00097 #define EXTPOLAR3 8 00098 00099 typedef struct { 00100 IOREG32 PLL_CON; 00101 IOREG32 PLL_CFG; 00102 IOREG32 PLL_STAT; 00103 IOREG32 PLL_FEED; 00104 } PLL; 00105 00106 #define PLL0Base ((PLL *)0xE01FC080) 00107 #define PLL1Base ((PLL *)0xE01FC0A0) 00108 #define PLL0CON (PLL0Base->PLL_CON) 00109 #define PLL0CFG (PLL0Base->PLL_CFG) 00110 #define PLL0STAT (PLL0Base->PLL_STAT) 00111 #define PLL0FEED (PLL0Base->PLL_FEED) 00112 #define PLL1CON (PLL1Base->PLL_CON) 00113 #define PLL1CFG (PLL1Base->PLL_CFG) 00114 #define PLL1STAT (PLL1Base->PLL_STAT) 00115 #define PLL1FEED (PLL1Base->PLL_FEED) 00116 00117 /* 00118 * Pins. 00119 */ 00120 typedef struct { 00121 IOREG32 PS_SEL0; 00122 IOREG32 PS_SEL1; 00123 IOREG32 _dummy[3]; 00124 IOREG32 PS_SEL2; 00125 } PS; 00126 00127 #define PSBase ((PS *)0xE002C000) 00128 #define PINSEL0 (PSBase->PS_SEL0) 00129 #define PINSEL1 (PSBase->PS_SEL1) 00130 #define PINSEL2 (PSBase->PS_SEL2) 00131 00132 /* 00133 * VIC 00134 */ 00135 #define SOURCE_WDT 0 00136 #define SOURCE_ARMCore0 2 00137 #define SOURCE_ARMCore1 3 00138 #define SOURCE_Timer0 4 00139 #define SOURCE_Timer1 5 00140 #define SOURCE_UART0 6 00141 #define SOURCE_UART1 7 00142 #define SOURCE_PWM0 8 00143 #define SOURCE_I2C0 9 00144 #define SOURCE_SPI0 10 00145 #define SOURCE_SPI1 11 00146 #define SOURCE_PLL 12 00147 #define SOURCE_RTC 13 00148 #define SOURCE_EINT0 14 00149 #define SOURCE_EINT1 15 00150 #define SOURCE_EINT2 16 00151 #define SOURCE_EINT3 17 00152 #define SOURCE_ADC0 18 00153 #define SOURCE_I2C1 19 00154 #define SOURCE_BOD 20 00155 #define SOURCE_ADC1 21 00156 #define SOURCE_USB 22 00157 00158 #define INTMASK(n) (1 << (n)) 00159 #define ALLINTMASK (INTMASK(SOURCE_WDT) | INTMASK(SOURCE_ARMCore0) | \ 00160 INTMASK(SOURCE_ARMCore1) | INTMASK(SOURCE_Timer0) | \ 00161 INTMASK(SOURCE_Timer1) | INTMASK(SOURCE_UART0) | \ 00162 INTMASK(SOURCE_UART1) | INTMASK(SOURCE_PWM0) | \ 00163 INTMASK(SOURCE_I2C0) | INTMASK(SOURCE_SPI0) | \ 00164 INTMASK(SOURCE_SPI1) | INTMASK(SOURCE_PLL) | \ 00165 INTMASK(SOURCE_RTC) | INTMASK(SOURCE_EINT0) | \ 00166 INTMASK(SOURCE_EINT1) | INTMASK(SOURCE_EINT2) | \ 00167 INTMASK(SOURCE_EINT3) | INTMASK(SOURCE_ADC0) | \ 00168 INTMASK(SOURCE_I2C1) | INTMASK(SOURCE_BOD) | \ 00169 INTMASK(SOURCE_ADC1) | INTMASK(SOURCE_USB)) 00170 00171 typedef struct { 00172 IOREG32 VIC_IRQStatus; 00173 IOREG32 VIC_FIQStatus; 00174 IOREG32 VIC_RawIntr; 00175 IOREG32 VIC_IntSelect; 00176 IOREG32 VIC_IntEnable; 00177 IOREG32 VIC_IntEnClear; 00178 IOREG32 VIC_SoftInt; 00179 IOREG32 VIC_SoftIntClear; 00180 IOREG32 VIC_Protection; 00181 IOREG32 unused1[3]; 00182 IOREG32 VIC_VectAddr; 00183 IOREG32 VIC_DefVectAddr; 00184 IOREG32 unused2[50]; 00185 IOREG32 VIC_VectAddrs[16]; 00186 IOREG32 unused3[48]; 00187 IOREG32 VIC_VectCntls[16]; 00188 } VIC; 00189 00190 #define VICBase ((VIC *)0xFFFFF000) 00191 #define VICVectorsBase ((IOREG32 *)0xFFFFF100) 00192 #define VICControlsBase ((IOREG32 *)0xFFFFF200) 00193 00194 #define VICIRQStatus (VICBase->VIC_IRQStatus) 00195 #define VICFIQStatus (VICBase->VIC_FIQStatus) 00196 #define VICRawIntr (VICBase->VIC_RawIntr) 00197 #define VICIntSelect (VICBase->VIC_IntSelect) 00198 #define VICIntEnable (VICBase->VIC_IntEnable) 00199 #define VICIntEnClear (VICBase->VIC_IntEnClear) 00200 #define VICSoftInt (VICBase->VIC_SoftInt) 00201 #define VICSoftIntClear (VICBase->VIC_SoftIntClear) 00202 #define VICProtection (VICBase->VIC_Protection) 00203 #define VICVectAddr (VICBase->VIC_VectAddr) 00204 #define VICDefVectAddr (VICBase->VIC_DefVectAddr) 00205 00206 #define VICVectAddrs(n) (VICBase->VIC_VectAddrs[n]) 00207 #define VICVectCntls(n) (VICBase->VIC_VectCntls[n]) 00208 00209 /* 00210 * MAM. 00211 */ 00212 typedef struct { 00213 IOREG32 MAM_Control; 00214 IOREG32 MAM_Timing; 00215 } MAM; 00216 00217 #define MAMBase ((MAM *)0xE01FC000) 00218 #define MAMCR (MAMBase->MAM_Control) 00219 #define MAMTIM (MAMBase->MAM_Timing) 00220 00221 /* 00222 * GPIO - FIO. 00223 */ 00224 typedef struct { 00225 IOREG32 IO_PIN; 00226 IOREG32 IO_SET; 00227 IOREG32 IO_DIR; 00228 IOREG32 IO_CLR; 00229 } GPIO; 00230 00231 #define GPIO0Base ((GPIO *)0xE0028000) 00232 #define IO0PIN (GPIO0Base->IO_PIN) 00233 #define IO0SET (GPIO0Base->IO_SET) 00234 #define IO0DIR (GPIO0Base->IO_DIR) 00235 #define IO0CLR (GPIO0Base->IO_CLR) 00236 00237 #define GPIO1Base ((GPIO *)0xE0028010) 00238 #define IO1PIN (GPIO1Base->IO_PIN) 00239 #define IO1SET (GPIO1Base->IO_SET) 00240 #define IO1DIR (GPIO1Base->IO_DIR) 00241 #define IO1CLR (GPIO1Base->IO_CLR) 00242 00243 typedef struct { 00244 IOREG32 FIO_DIR; 00245 IOREG32 unused1; 00246 IOREG32 unused2; 00247 IOREG32 unused3; 00248 IOREG32 FIO_MASK; 00249 IOREG32 FIO_PIN; 00250 IOREG32 FIO_SET; 00251 IOREG32 FIO_CLR; 00252 } FIO; 00253 00254 #define FIO0Base ((FIO *)0x3FFFC000) 00255 #define FIO0DIR (FIO0Base->FIO_DIR) 00256 #define FIO0MASK (FIO0Base->FIO_MASK) 00257 #define FIO0PIN (FIO0Base->FIO_PIN) 00258 #define FIO0SET (FIO0Base->FIO_SET) 00259 #define FIO0CLR (FIO0Base->FIO_CLR) 00260 00261 #define FIO1Base ((FIO *)0x3FFFC020) 00262 #define FIO1DIR (FIO1Base->FIO_DIR) 00263 #define FIO1MASK (FIO1Base->FIO_MASK) 00264 #define FIO1PIN (FIO1Base->FIO_PIN) 00265 #define FIO1SET (FIO1Base->FIO_SET) 00266 #define FIO1CLR (FIO1Base->FIO_CLR) 00267 00268 /* 00269 * UART. 00270 */ 00271 typedef struct { 00272 union { 00273 IOREG32 UART_RBR; 00274 IOREG32 UART_THR; 00275 IOREG32 UART_DLL; 00276 }; 00277 union { 00278 IOREG32 UART_IER; 00279 IOREG32 UART_DLM; 00280 }; 00281 union { 00282 IOREG32 UART_IIR; 00283 IOREG32 UART_FCR; 00284 }; 00285 IOREG32 UART_LCR; 00286 IOREG32 UART_MCR; // UART1 only 00287 IOREG32 UART_LSR; 00288 IOREG32 unused18; 00289 IOREG32 UART_SCR; 00290 IOREG32 UART_ACR; 00291 IOREG32 unused24; 00292 IOREG32 UART_FDR; 00293 IOREG32 unused2C; 00294 IOREG32 UART_TER; 00295 } UART; 00296 00297 #define U0Base ((UART *)0xE000C000) 00298 #define U0RBR (U0Base->UART_RBR) 00299 #define U0THR (U0Base->UART_THR) 00300 #define U0DLL (U0Base->UART_DLL) 00301 #define U0IER (U0Base->UART_IER) 00302 #define U0DLM (U0Base->UART_DLM) 00303 #define U0IIR (U0Base->UART_IIR) 00304 #define U0FCR (U0Base->UART_FCR) 00305 #define U0LCR (U0Base->UART_LCR) 00306 #define U0LSR (U0Base->UART_LSR) 00307 #define U0SCR (U0Base->UART_SCR) 00308 #define U0ACR (U0Base->UART_ACR) 00309 #define U0FDR (U0Base->UART_FDR) 00310 #define U0TER (U0Base->UART_TER) 00311 00312 #define U1Base ((UART *)0xE0010000) 00313 #define U1RBR (U1Base->UART_RBR) 00314 #define U1THR (U1Base->UART_THR) 00315 #define U1DLL (U1Base->UART_DLL) 00316 #define U1IER (U1Base->UART_IER) 00317 #define U1DLM (U1Base->UART_DLM) 00318 #define U1IIR (U1Base->UART_IIR) 00319 #define U1FCR (U1Base->UART_FCR) 00320 #define U1MCR (U1Base->UART_MCR) 00321 #define U1LCR (U1Base->UART_LCR) 00322 #define U1LSR (U1Base->UART_LSR) 00323 #define U1SCR (U1Base->UART_SCR) 00324 #define U1ACR (U1Base->UART_ACR) 00325 #define U1FDR (U1Base->UART_FDR) 00326 #define U1TER (U1Base->UART_TER) 00327 00328 #define IIR_SRC_MASK 0x0F 00329 #define IIR_SRC_NONE 0x01 00330 #define IIR_SRC_TX 0x02 00331 #define IIR_SRC_RX 0x04 00332 #define IIR_SRC_ERROR 0x06 00333 #define IIR_SRC_TIMEOUT 0x0C 00334 00335 #define IER_RBR 1 00336 #define IER_THRE 2 00337 #define IER_STATUS 4 00338 00339 #define IIR_INT_PENDING 1 00340 00341 #define LCR_WL5 0 00342 #define LCR_WL6 1 00343 #define LCR_WL7 2 00344 #define LCR_WL8 3 00345 #define LCR_STOP1 0 00346 #define LCR_STOP2 4 00347 #define LCR_NOPARITY 0 00348 #define LCR_PARITYODD 0x08 00349 #define LCR_PARITYEVEN 0x18 00350 #define LCR_PARITYONE 0x28 00351 #define LCR_PARITYZERO 0x38 00352 #define LCR_BREAK_ON 0x40 00353 #define LCR_DLAB 0x80 00354 00355 #define FCR_ENABLE 1 00356 #define FCR_RXRESET 2 00357 #define FCR_TXRESET 4 00358 #define FCR_TRIGGER0 0 00359 #define FCR_TRIGGER1 0x40 00360 #define FCR_TRIGGER2 0x80 00361 #define FCR_TRIGGER3 0xC0 00362 00363 #define LSR_RBR_FULL 1 00364 #define LSR_OVERRUN 2 00365 #define LSR_PARITY 4 00366 #define LSR_FRAMING 8 00367 #define LSR_BREAK 0x10 00368 #define LSR_THRE 0x20 00369 #define LSR_TEMT 0x40 00370 #define LSR_RXFE 0x80 00371 00372 #define TER_ENABLE 0x80 00373 00374 /* 00375 * SSP. 00376 */ 00377 typedef struct { 00378 IOREG32 SSP_CR0; 00379 IOREG32 SSP_CR1; 00380 IOREG32 SSP_DR; 00381 IOREG32 SSP_SR; 00382 IOREG32 SSP_CPSR; 00383 IOREG32 SSP_IMSC; 00384 IOREG32 SSP_RIS; 00385 IOREG32 SSP_MIS; 00386 IOREG32 SSP_ICR; 00387 } SSP; 00388 00389 #define SSPBase ((SSP *)0xE0068000) 00390 #define SSPCR0 (SSPBase->SSP_CR0) 00391 #define SSPCR1 (SSPBase->SSP_CR1) 00392 #define SSPDR (SSPBase->SSP_DR) 00393 #define SSPSR (SSPBase->SSP_SR) 00394 #define SSPCPSR (SSPBase->SSP_CPSR) 00395 #define SSPIMSC (SSPBase->SSP_IMSC) 00396 #define SSPRIS (SSPBase->SSP_RIS) 00397 #define SSPMIS (SSPBase->SSP_MIS) 00398 #define SSPICR (SSPBase->SSP_ICR) 00399 00400 #define CR0_DSS4BIT 3 00401 #define CR0_DSS5BIT 4 00402 #define CR0_DSS6BIT 5 00403 #define CR0_DSS7BIT 6 00404 #define CR0_DSS8BIT 7 00405 #define CR0_DSS9BIT 8 00406 #define CR0_DSS10BIT 9 00407 #define CR0_DSS11BIT 0xA 00408 #define CR0_DSS12BIT 0xB 00409 #define CR0_DSS13BIT 0xC 00410 #define CR0_DSS14BIT 0xD 00411 #define CR0_DSS15BIT 0xE 00412 #define CR0_DSS16BIT 0xF 00413 #define CR0_FRFSPI 0 00414 #define CR0_FRFSSI 0x10 00415 #define CR0_FRFMW 0x20 00416 #define CR0_CPOL 0x40 00417 #define CR0_CPHA 0x80 00418 #define CR0_CLOCKRATE(n) ((n) << 8) 00419 00420 #define CR1_LBM 1 00421 #define CR1_SSE 2 00422 #define CR1_MS 4 00423 #define CR1_SOD 8 00424 00425 #define SR_TFE 1 00426 #define SR_TNF 2 00427 #define SR_RNE 4 00428 #define SR_RFF 8 00429 #define SR_BSY 0x10 00430 00431 #define IMSC_ROR 1 00432 #define IMSC_RT 2 00433 #define IMSC_RX 4 00434 #define IMSC_TX 8 00435 00436 #define RIS_ROR 1 00437 #define RIS_RT 2 00438 #define RIS_RX 4 00439 #define RIS_TX 8 00440 00441 #define MIS_ROR 1 00442 #define MIS_RT 2 00443 #define MIS_RX 4 00444 #define MIS_TX 8 00445 00446 #define ICR_ROR 1 00447 #define ICR_RT 2 00448 00449 /* 00450 * Timers/Counters. 00451 */ 00452 typedef struct { 00453 IOREG32 TC_IR; 00454 IOREG32 TC_TCR; 00455 IOREG32 TC_TC; 00456 IOREG32 TC_PR; 00457 IOREG32 TC_PC; 00458 IOREG32 TC_MCR; 00459 IOREG32 TC_MR0; 00460 IOREG32 TC_MR1; 00461 IOREG32 TC_MR2; 00462 IOREG32 TC_MR3; 00463 IOREG32 TC_CCR; 00464 IOREG32 TC_CR0; 00465 IOREG32 TC_CR1; 00466 IOREG32 TC_CR2; 00467 IOREG32 TC_CR3; 00468 IOREG32 TC_EMR; 00469 IOREG32 TC_CTCR; 00470 } TC; 00471 00472 #define T0Base ((TC *)0xE0004000) 00473 #define T0IR (T0Base->TC_IR) 00474 #define T0TCR (T0Base->TC_TCR) 00475 #define T0TC (T0Base->TC_TC) 00476 #define T0PR (T0Base->TC_PR) 00477 #define T0PC (T0Base->TC_PC) 00478 #define T0MCR (T0Base->TC_MCR) 00479 #define T0MR0 (T0Base->TC_MR0) 00480 #define T0MR1 (T0Base->TC_MR1) 00481 #define T0MR2 (T0Base->TC_MR2) 00482 #define T0MR3 (T0Base->TC_MR3) 00483 #define T0CCR (T0Base->TC_CCR) 00484 #define T0CR0 (T0Base->TC_CR0) 00485 #define T0CR1 (T0Base->TC_CR1) 00486 #define T0CR2 (T0Base->TC_CR2) 00487 #define T0CR3 (T0Base->TC_CR3) 00488 #define T0EMR (T0Base->TC_EMR) 00489 #define T0CTCR (T0Base->TC_CTCR) 00490 00491 #define T1Base ((TC *)0xE0008000) 00492 #define T1IR (T1Base->TC_IR) 00493 #define T1TCR (T1Base->TC_TCR) 00494 #define T1TC (T1Base->TC_TC) 00495 #define T1PR (T1Base->TC_PR) 00496 #define T1PC (T1Base->TC_PC) 00497 #define T1MCR (T1Base->TC_MCR) 00498 #define T1MR0 (T1Base->TC_MR0) 00499 #define T1MR1 (T1Base->TC_MR1) 00500 #define T1MR2 (T1Base->TC_MR2) 00501 #define T1MR3 (T1Base->TC_MR3) 00502 #define T1CCR (T1Base->TC_CCR) 00503 #define T1CR0 (T1Base->TC_CR0) 00504 #define T1CR1 (T1Base->TC_CR1) 00505 #define T1CR2 (T1Base->TC_CR2) 00506 #define T1CR3 (T1Base->TC_CR3) 00507 #define T1EMR (T1Base->TC_EMR) 00508 #define T1CTCR (T1Base->TC_CTCR) 00509 00510 /* 00511 * Watchdog. 00512 */ 00513 typedef struct { 00514 IOREG32 WD_MOD; 00515 IOREG32 WD_TC; 00516 IOREG32 WD_FEED; 00517 IOREG32 WD_TV; 00518 } WD; 00519 00520 #define WDBase ((WD *)0xE0000000) 00521 #define WDMOD (WDBase->WD_MOD) 00522 #define WDTC (WDBase->WD_TC) 00523 #define WDFEED (WDBase->WD_FEED) 00524 #define WDTV (WDBase->WD_TV) 00525 00526 /* 00527 * DAC. 00528 */ 00529 #define DACR (*((IOREG32 *)0xE006C000)) 00530 00531 #endif /* _LPC214X_H_ */ 00532