ChibiOS/RT Architecture - Reference Manual - Guides |
00001 /* 00002 ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. 00003 00004 This file is part of ChibiOS/RT. 00005 00006 ChibiOS/RT is free software; you can redistribute it and/or modify 00007 it under the terms of the GNU General Public License as published by 00008 the Free Software Foundation; either version 3 of the License, or 00009 (at your option) any later version. 00010 00011 ChibiOS/RT is distributed in the hope that it will be useful, 00012 but WITHOUT ANY WARRANTY; without even the implied warranty of 00013 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00014 GNU General Public License for more details. 00015 00016 You should have received a copy of the GNU General Public License 00017 along with this program. If not, see <http://www.gnu.org/licenses/>. 00018 00019 --- 00020 00021 A special exception to the GPL can be applied should you wish to distribute 00022 a combined work that includes ChibiOS/RT, without being obliged to provide 00023 the source code for any proprietary components. See the file exception.txt 00024 for full details of how and when the exception can be applied. 00025 */ 00026 00027 /** 00028 * @file STM32/hal_lld_f103.h 00029 * @brief STM32F103 HAL subsystem low level driver header. 00030 * 00031 * @addtogroup STM32F103_HAL 00032 * @{ 00033 */ 00034 00035 #ifndef _HAL_LLD_F103_H_ 00036 #define _HAL_LLD_F103_H_ 00037 00038 /*===========================================================================*/ 00039 /* Driver constants. */ 00040 /*===========================================================================*/ 00041 00042 #define STM32_HSICLK 8000000 /**< High speed internal clock. */ 00043 #define STM32_LSICLK 40000 /**< Low speed internal clock. */ 00044 00045 /* RCC_CFGR register bits definitions.*/ 00046 #define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */ 00047 #define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */ 00048 #define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */ 00049 00050 #define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */ 00051 #define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */ 00052 #define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */ 00053 #define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */ 00054 #define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */ 00055 #define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */ 00056 #define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */ 00057 #define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */ 00058 #define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */ 00059 00060 #define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */ 00061 #define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */ 00062 #define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */ 00063 #define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */ 00064 #define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */ 00065 00066 #define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */ 00067 #define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */ 00068 #define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */ 00069 #define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */ 00070 #define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */ 00071 00072 #define STM32_ADCPRE_DIV2 (0 << 14) /**< HCLK divided by 2. */ 00073 #define STM32_ADCPRE_DIV4 (1 << 14) /**< HCLK divided by 4. */ 00074 #define STM32_ADCPRE_DIV6 (2 << 14) /**< HCLK divided by 6. */ 00075 #define STM32_ADCPRE_DIV8 (3 << 14) /**< HCLK divided by 8. */ 00076 00077 #define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */ 00078 #define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */ 00079 00080 #define STM32_PLLXTPRE_DIV1 (0 << 17) /**< HSE divided by 1. */ 00081 #define STM32_PLLXTPRE_DIV2 (1 << 17) /**< HSE divided by 2. */ 00082 00083 #define STM32_MCO_NOCLOCK (0 << 24) /**< No clock on MCO pin. */ 00084 #define STM32_MCO_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */ 00085 #define STM32_MCO_HSI (5 << 24) /**< HSI clock on MCO pin. */ 00086 #define STM32_MCO_HSE (6 << 24) /**< HSE clock on MCO pin. */ 00087 #define STM32_MCO_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */ 00088 00089 /*===========================================================================*/ 00090 /* Platform specific friendly IRQ names. */ 00091 /*===========================================================================*/ 00092 00093 #define WWDG_IRQHandler Vector40 /**< Window Watchdog. */ 00094 #define PVD_IRQHandler Vector44 /**< PVD through EXTI Line 00095 detect. */ 00096 #define TAMPER_IRQHandler Vector48 /**< Tamper. */ 00097 #define RTC_IRQHandler Vector4C /**< RTC. */ 00098 #define FLASH_IRQHandler Vector50 /**< Flash. */ 00099 #define RCC_IRQHandler Vector54 /**< RCC. */ 00100 #define EXTI0_IRQHandler Vector58 /**< EXTI Line 0. */ 00101 #define EXTI1_IRQHandler Vector5C /**< EXTI Line 1. */ 00102 #define EXTI2_IRQHandler Vector60 /**< EXTI Line 2. */ 00103 #define EXTI3_IRQHandler Vector64 /**< EXTI Line 3. */ 00104 #define EXTI4_IRQHandler Vector68 /**< EXTI Line 4. */ 00105 #define DMA1_Ch1_IRQHandler Vector6C /**< DMA1 Channel 1. */ 00106 #define DMA1_Ch2_IRQHandler Vector70 /**< DMA1 Channel 2. */ 00107 #define DMA1_Ch3_IRQHandler Vector74 /**< DMA1 Channel 3. */ 00108 #define DMA1_Ch4_IRQHandler Vector78 /**< DMA1 Channel 4. */ 00109 #define DMA1_Ch5_IRQHandler Vector7C /**< DMA1 Channel 5. */ 00110 #define DMA1_Ch6_IRQHandler Vector80 /**< DMA1 Channel 6. */ 00111 #define DMA1_Ch7_IRQHandler Vector84 /**< DMA1 Channel 7. */ 00112 #define ADC1_2_IRQHandler Vector88 /**< ADC1_2. */ 00113 #define CAN1_TX_IRQHandler Vector8C /**< CAN1 TX. */ 00114 #define USB_HP_IRQHandler Vector8C /**< USB High Priority, CAN1 TX.*/ 00115 #define CAN1_RX0_IRQHandler Vector90 /**< CAN1 RX0. */ 00116 #define USB_LP_IRQHandler Vector90 /**< USB Low Priority, CAN1 RX0.*/ 00117 #define CAN1_RX1_IRQHandler Vector94 /**< CAN1 RX1. */ 00118 #define CAN1_SCE_IRQHandler Vector98 /**< CAN1 SCE. */ 00119 #define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */ 00120 #define TIM1_BRK_IRQHandler VectorA0 /**< TIM1 Break. */ 00121 #define TIM1_UP_IRQHandler VectorA4 /**< TIM1 Update. */ 00122 #define TIM1_TRG_COM_IRQHandler VectorA8 /**< TIM1 Trigger and 00123 Commutation. */ 00124 #define TIM1_CC_IRQHandler VectorAC /**< TIM1 Capture Compare. */ 00125 #define TIM2_IRQHandler VectorB0 /**< TIM2. */ 00126 #define TIM3_IRQHandler VectorB4 /**< TIM3. */ 00127 #if defined(STM32F10X_MD) || defined(STM32F10X_HD) || defined(__DOXYGEN__) 00128 #define TIM4_IRQHandler VectorB8 /**< TIM4. */ 00129 #endif 00130 #define I2C1_EV_IRQHandler VectorBC /**< I2C1 Event. */ 00131 #define I2C1_ER_IRQHandler VectorC0 /**< I2C1 Error. */ 00132 #if defined(STM32F10X_MD) || defined(STM32F10X_HD) || defined(__DOXYGEN__) 00133 #define I2C2_EV_IRQHandler VectorC4 /**< I2C2 Event. */ 00134 #define I2C2_ER_IRQHandler VectorC8 /**< I2C2 Error. */ 00135 #endif 00136 #define SPI1_IRQHandler VectorCC /**< SPI1. */ 00137 #if defined(STM32F10X_MD) || defined(STM32F10X_HD) || defined(__DOXYGEN__) 00138 #define SPI2_IRQHandler VectorD0 /**< SPI2. */ 00139 #endif 00140 #define USART1_IRQHandler VectorD4 /**< USART1. */ 00141 #define USART2_IRQHandler VectorD8 /**< USART2. */ 00142 #if defined(STM32F10X_MD) || defined(STM32F10X_HD) || defined(__DOXYGEN__) 00143 #define USART3_IRQHandler VectorDC /**< USART3. */ 00144 #endif 00145 #define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */ 00146 #define RTCAlarm_IRQHandler VectorE4 /**< RTC Alarm through EXTI. */ 00147 #define USBWakeUp_IRQHandler VectorE8 /**< USB Wakeup from suspend. */ 00148 #if defined(STM32F10X_HD) || defined(__DOXYGEN__) 00149 #define TIM8_BRK_IRQHandler VectorEC /**< TIM8 Break. */ 00150 #define TIM8_UP_IRQHandler VectorF0 /**< TIM8 Update. */ 00151 #define TIM8_TRG_COM_IRQHandler VectorF4 /**< TIM8 Trigger and 00152 Commutation. */ 00153 #define TIM8_CC_IRQHandler VectorF8 /**< TIM8 Capture Compare. */ 00154 #define ADC3_IRQHandler VectorFC /**< ADC3. */ 00155 #define FSMC_IRQHandler Vector100 /**< FSMC. */ 00156 #define SDIO_IRQHandler Vector104 /**< SDIO. */ 00157 #define TIM5_IRQHandler Vector108 /**< TIM5. */ 00158 #define SPI3_IRQHandler Vector10C /**< SPI3. */ 00159 #define UART4_IRQHandler Vector110 /**< UART4. */ 00160 #define UART5_IRQHandler Vector114 /**< UART5. */ 00161 #define TIM6_IRQHandler Vector118 /**< TIM6. */ 00162 #define TIM7_IRQHandler Vector11C /**< TIM7. */ 00163 #define DMA2_Ch1_IRQHandler Vector120 /**< DMA2 Channel1. */ 00164 #define DMA2_Ch2_IRQHandler Vector124 /**< DMA2 Channel2. */ 00165 #define DMA2_Ch3_IRQHandler Vector128 /**< DMA2 Channel3. */ 00166 #define DMA2_Ch4_5_IRQHandler Vector12C /**< DMA2 Channel4 & Channel5. */ 00167 #endif 00168 00169 /*===========================================================================*/ 00170 /* Driver pre-compile time settings. */ 00171 /*===========================================================================*/ 00172 00173 /** 00174 * @brief Main clock source selection. 00175 * @note If the selected clock source is not the PLL then the PLL is not 00176 * initialized and started. 00177 * @note The default value is calculated for a 72MHz system clock from 00178 * a 8MHz crystal using the PLL. 00179 */ 00180 #if !defined(STM32_SW) || defined(__DOXYGEN__) 00181 #define STM32_SW STM32_SW_PLL 00182 #endif 00183 00184 /** 00185 * @brief Clock source for the PLL. 00186 * @note This setting has only effect if the PLL is selected as the 00187 * system clock source. 00188 * @note The default value is calculated for a 72MHz system clock from 00189 * a 8MHz crystal using the PLL. 00190 */ 00191 #if !defined(STM32_PLLSRC) || defined(__DOXYGEN__) 00192 #define STM32_PLLSRC STM32_PLLSRC_HSE 00193 #endif 00194 00195 /** 00196 * @brief Crystal PLL pre-divider. 00197 * @note This setting has only effect if the PLL is selected as the 00198 * system clock source. 00199 * @note The default value is calculated for a 72MHz system clock from 00200 * a 8MHz crystal using the PLL. 00201 */ 00202 #if !defined(STM32_PLLXTPRE) || defined(__DOXYGEN__) 00203 #define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 00204 #endif 00205 00206 /** 00207 * @brief PLL multiplier value. 00208 * @note The allowed range is 2...16. 00209 * @note The default value is calculated for a 72MHz system clock from 00210 * a 8MHz crystal using the PLL. 00211 */ 00212 #if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__) 00213 #define STM32_PLLMUL_VALUE 9 00214 #endif 00215 00216 /** 00217 * @brief AHB prescaler value. 00218 * @note The default value is calculated for a 72MHz system clock from 00219 * a 8MHz crystal using the PLL. 00220 */ 00221 #if !defined(STM32_HPRE) || defined(__DOXYGEN__) 00222 #define STM32_HPRE STM32_HPRE_DIV1 00223 #endif 00224 00225 /** 00226 * @brief APB1 prescaler value. 00227 */ 00228 #if !defined(STM32_PPRE1) || defined(__DOXYGEN__) 00229 #define STM32_PPRE1 STM32_PPRE1_DIV2 00230 #endif 00231 00232 /** 00233 * @brief APB2 prescaler value. 00234 */ 00235 #if !defined(STM32_PPRE2) || defined(__DOXYGEN__) 00236 #define STM32_PPRE2 STM32_PPRE2_DIV2 00237 #endif 00238 00239 /** 00240 * @brief ADC prescaler value. 00241 */ 00242 #if !defined(STM32_ADCPRE) || defined(__DOXYGEN__) 00243 #define STM32_ADCPRE STM32_ADCPRE_DIV4 00244 #endif 00245 00246 /** 00247 * @brief MCO pin setting. 00248 */ 00249 #if !defined(STM32_MCO) || defined(__DOXYGEN__) 00250 #define STM32_MCO STM32_MCO_NOCLOCK 00251 #endif 00252 00253 /*===========================================================================*/ 00254 /* Derived constants and error checks. */ 00255 /*===========================================================================*/ 00256 00257 /* HSE prescaler setting check.*/ 00258 #if (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV1) && \ 00259 (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV2) 00260 #error "invalid STM32_PLLXTPRE value specified" 00261 #endif 00262 /** 00263 * @brief PLLMUL field. 00264 */ 00265 #if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) || \ 00266 defined(__DOXYGEN__) 00267 #define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18) 00268 #else 00269 #error "invalid STM32_PLLMUL_VALUE value specified" 00270 #endif 00271 00272 /** 00273 * @brief PLL input clock frequency. 00274 */ 00275 #if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) 00276 #if STM32_PLLXTPRE == STM32_PLLXTPRE_DIV1 00277 #define STM32_PLLCLKIN (STM32_HSECLK / 1) 00278 #else 00279 #define STM32_PLLCLKIN (STM32_HSECLK / 2) 00280 #endif 00281 #elif STM32_PLLSRC == STM32_PLLSRC_HSI 00282 #define STM32_PLLCLKIN (STM32_HSICLK / 2) 00283 #else 00284 #error "invalid STM32_PLLSRC value specified" 00285 #endif 00286 00287 /* PLL input frequency range check.*/ 00288 #if (STM32_PLLCLKIN < 3000000) || (STM32_PLLCLKIN > 12000000) 00289 #error "STM32_PLLCLKIN outside acceptable range (3...12MHz)" 00290 #endif 00291 00292 /** 00293 * @brief PLL output clock frequency. 00294 */ 00295 #define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE) 00296 00297 /* PLL output frequency range check.*/ 00298 #if (STM32_PLLCLKOUT < 16000000) || (STM32_PLLCLKOUT > 72000000) 00299 #error "STM32_PLLCLKOUT outside acceptable range (16...72MHz)" 00300 #endif 00301 00302 /** 00303 * @brief System clock source. 00304 */ 00305 #if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__) 00306 #define STM32_SYSCLK STM32_PLLCLKOUT 00307 #elif (STM32_SW == STM32_SW_HSI) 00308 #define STM32_SYSCLK STM32_HSICLK 00309 #elif (STM32_SW == STM32_SW_HSE) 00310 #define STM32_SYSCLK STM32_HSECLK 00311 #else 00312 #error "invalid STM32_SYSCLK_SW value specified" 00313 #endif 00314 00315 /* Check on the system clock.*/ 00316 #if STM32_SYSCLK > 72000000 00317 #error "STM32_SYSCLK above maximum rated frequency (72MHz)" 00318 #endif 00319 00320 /** 00321 * @brief AHB frequency. 00322 */ 00323 #if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__) 00324 #define STM32_HCLK (STM32_SYSCLK / 1) 00325 #elif STM32_HPRE == STM32_HPRE_DIV2 00326 #define STM32_HCLK (STM32_SYSCLK / 2) 00327 #elif STM32_HPRE == STM32_HPRE_DIV4 00328 #define STM32_HCLK (STM32_SYSCLK / 4) 00329 #elif STM32_HPRE == STM32_HPRE_DIV8 00330 #define STM32_HCLK (STM32_SYSCLK / 8) 00331 #elif STM32_HPRE == STM32_HPRE_DIV16 00332 #define STM32_HCLK (STM32_SYSCLK / 16) 00333 #elif STM32_HPRE == STM32_HPRE_DIV64 00334 #define STM32_HCLK (STM32_SYSCLK / 64) 00335 #elif STM32_HPRE == STM32_HPRE_DIV128 00336 #define STM32_HCLK (STM32_SYSCLK / 128) 00337 #elif STM32_HPRE == STM32_HPRE_DIV256 00338 #define STM32_HCLK (STM32_SYSCLK / 256) 00339 #elif STM32_HPRE == STM32_HPRE_DIV512 00340 #define STM32_HCLK (STM32_SYSCLK / 512) 00341 #else 00342 #error "invalid STM32_HPRE value specified" 00343 #endif 00344 00345 /* AHB frequency check.*/ 00346 #if STM32_HCLK > 72000000 00347 #error "STM32_HCLK exceeding maximum frequency (72MHz)" 00348 #endif 00349 00350 /** 00351 * @brief APB1 frequency. 00352 */ 00353 #if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) 00354 #define STM32_PCLK1 (STM32_HCLK / 1) 00355 #elif STM32_PPRE1 == STM32_PPRE1_DIV2 00356 #define STM32_PCLK1 (STM32_HCLK / 2) 00357 #elif STM32_PPRE1 == STM32_PPRE1_DIV4 00358 #define STM32_PCLK1 (STM32_HCLK / 4) 00359 #elif STM32_PPRE1 == STM32_PPRE1_DIV8 00360 #define STM32_PCLK1 (STM32_HCLK / 8) 00361 #elif STM32_PPRE1 == STM32_PPRE1_DIV16 00362 #define STM32_PCLK1 (STM32_HCLK / 16) 00363 #else 00364 #error "invalid STM32_PPRE1 value specified" 00365 #endif 00366 00367 /* APB1 frequency check.*/ 00368 #if STM32_PCLK2 > 36000000 00369 #error "STM32_PCLK1 exceeding maximum frequency (36MHz)" 00370 #endif 00371 00372 /** 00373 * @brief APB2 frequency. 00374 */ 00375 #if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) 00376 #define STM32_PCLK2 (STM32_HCLK / 1) 00377 #elif STM32_PPRE2 == STM32_PPRE2_DIV2 00378 #define STM32_PCLK2 (STM32_HCLK / 2) 00379 #elif STM32_PPRE2 == STM32_PPRE2_DIV4 00380 #define STM32_PCLK2 (STM32_HCLK / 4) 00381 #elif STM32_PPRE2 == STM32_PPRE2_DIV8 00382 #define STM32_PCLK2 (STM32_HCLK / 8) 00383 #elif STM32_PPRE2 == STM32_PPRE2_DIV16 00384 #define STM32_PCLK2 (STM32_HCLK / 16) 00385 #else 00386 #error "invalid STM32_PPRE2 value specified" 00387 #endif 00388 00389 /* APB2 frequency check.*/ 00390 #if STM32_PCLK2 > 72000000 00391 #error "STM32_PCLK2 exceeding maximum frequency (72MHz)" 00392 #endif 00393 00394 /** 00395 * @brief ADC frequency. 00396 */ 00397 #if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__) 00398 #define STM32_ADCCLK (STM32_PCLK2 / 2) 00399 #elif STM32_ADCPRE == STM32_ADCPRE_DIV4 00400 #define STM32_ADCCLK (STM32_PCLK2 / 4) 00401 #elif STM32_ADCPRE == STM32_ADCPRE_DIV6 00402 #define STM32_ADCCLK (STM32_PCLK2 / 6) 00403 #elif STM32_ADCPRE == STM32_ADCPRE_DIV8 00404 #define STM32_ADCCLK (STM32_PCLK2 / 8) 00405 #else 00406 #error "invalid STM32_ADCPRE value specified" 00407 #endif 00408 00409 /* ADC frequency check.*/ 00410 #if STM32_ADCCLK > 14000000 00411 #error "STM32_ADCCLK exceeding maximum frequency (14MHz)" 00412 #endif 00413 00414 /** 00415 * @brief Timers 2, 3, 4, 5, 6, 7, 12, 13, 14 clock. 00416 */ 00417 #if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) 00418 #define STM32_TIMCLK1 (STM32_PCLK1 * 1) 00419 #else 00420 #define STM32_TIMCLK1 (STM32_PCLK1 * 2) 00421 #endif 00422 00423 /** 00424 * @brief Timers 1, 8, 9, 10 and 11 clock. 00425 */ 00426 #if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) 00427 #define STM32_TIMCLK2 (STM32_PCLK2 * 1) 00428 #else 00429 #define STM32_TIMCLK2 (STM32_PCLK2 * 2) 00430 #endif 00431 00432 /** 00433 * @brief Flash settings. 00434 */ 00435 #if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__) 00436 #define STM32_FLASHBITS 0x00000010 00437 #elif STM32_HCLK <= 48000000 00438 #define STM32_FLASHBITS 0x00000011 00439 #else 00440 #define STM32_FLASHBITS 0x00000012 00441 #endif 00442 00443 #endif /* _HAL_LLD_F103_H_ */ 00444 00445 /** @} */