ChibiOS/RT Architecture - Reference Manual - Guides |
00001 /**************************************************************************/ 00002 00003 /* FILE NAME: mpc563xm.h COPYRIGHT (c) Freescale 2008,2009 */ 00004 /* VERSION: 2.0 All Rights Reserved */ 00005 /* */ 00006 /* DESCRIPTION: */ 00007 /* This file contain all of the register and bit field definitions for */ 00008 /* MPC563xM. This version supports revision 1.0 and later. */ 00009 /*========================================================================*/ 00010 /* UPDATE HISTORY */ 00011 /* REV AUTHOR DATE DESCRIPTION OF CHANGE */ 00012 /* --- ----------- --------- --------------------- */ 00013 /* 1.0 G. Emerson 31/OCT/07 Initial version. */ 00014 /* 1.1 G. Emerson 20/DEC/07 Added SYSDIV HLT HLTACK */ 00015 /* Added ESYNCR1 ESYNCR2 SYNFMMR */ 00016 /* 1.2 G. Emerson 31/JAN/08 Change eMIOS channels so there are 24. */ 00017 /* 8 channels in the middle of the range */ 00018 /* do not exist */ 00019 /* 1.3 G. Emerson 30/JUL/08 FLEXCAN - Supports FIFO and Buffer. */ 00020 /* RXIMR added */ 00021 /* FMPLL - Added FMPLL.SYNFMMR.B.BSY */ 00022 /* SIU - Added SIU.ISEL0-3 */ 00023 /* EMIOS - Added EMIOS.CH[x].ALTCADR.R */ 00024 /* MCM - Replaced ECSM with MCM */ 00025 /* removing SWT registers as defined at */ 00026 /* seperate memory location. PFLASH */ 00027 /* registers pre-fixed with P*. Added PCT,*/ 00028 /* PLREV, PLAMC, PLASC, IOPMC, MRSR, MWCR.*/ 00029 /* PBRIDGE - Removed as no PBRIDGE */ 00030 /* registers. */ 00031 /* INTC - Updated number of PSR from */ 00032 /* 358 to 360. */ 00033 /* mpc5500_spr.h - Added RI to MSR and NMI*/ 00034 /* to MSCR. */ 00035 /* 1.4 G. Emerson 30/SEP/08 Add SIU.MIDR2 */ 00036 /* Changes to SIU.MIDR as per RM. */ 00037 /* 1.5 May 2009 Changes to match documentation, removed*/ 00038 /* Not released */ 00039 /* 1.6 K. Odenthal 03/June/09 Update for 1.5M version of the MPC563xM*/ 00040 /* & R. Dees */ 00041 /* INTC - All Processor 0 regs matched to previous */ 00042 /* version */ 00043 /* INTC - BCR renamed to MCR to match previous */ 00044 /* version */ 00045 /* INTC - VTES_PRC1 and HVEN_PRC1 added to MCR */ 00046 /* INTC - CPR_PRC1, IACKR_PRC1 and EOIR_PRC1 */ 00047 /* registers added */ 00048 /* INTC - 512 PSR registers instead of 364 */ 00049 /* ECSM - (Internal - mcm -> ecsm in the source files*/ 00050 /* for generating the header file */ 00051 /* ECSM - All bits and regs got an additional "p" in */ 00052 /* the name in the user manual for "Platform" */ 00053 /* -> deleted to match */ 00054 /* ECSM - SWTCR, SWTSR and SWTIR don't exist in */ 00055 /* MPC563xM -> deleted */ 00056 /* ECSM - PROTECTION in the URM is one bitfield, */ 00057 /* in mop5534 this are four: PROT1-4 -> */ 00058 /* changed to match */ 00059 /* EMCM - removed undocumented registers */ 00060 /* ECSM - RAM ECC Syndrome is new in MPC563xM -> added */ 00061 /* XBAR - removed AMPR and ASGPCR registers */ 00062 /* XBAR - removed HPE bits for nonexistant masters */ 00063 /* EBI - added: D16_31, AD_MUX and SETA bits */ 00064 /* EBI - Added reserved register at address 0x4. */ 00065 /* EBI - Corrected number of chip selects in for both*/ 00066 /* the EBI_CS and the CAL_EBI_CS */ 00067 /* SIU - corrected number of GPDO registers and */ 00068 /* allowed for maximum PCR registers. */ 00069 /* SWT - add KEY bit to CR, correct WND (from WNO) */ 00070 /* SWT - add SK register */ 00071 /* PMC - moved bits from CFGR to Status Register (SR)*/ 00072 /* PMC - Added SR */ 00073 /* DECFIL - Added new bits DSEL, IBIE, OBIE, EDME, */ 00074 /* TORE, & TRFE to MCR. Added IBIC, OBIC, */ 00075 /* DIVRC, IBIF, OBIF, DIVR to MSR. */ 00076 /* changed OUTTEG to OUTTAG in OB */ 00077 /* Change COEF to TAG in TAG register */ 00078 /* EQADC - removed REDLCCR - not supported */ 00079 /* FLASH - Aligned register and bit names with legacy*/ 00080 /* 1.7 K. Odenthal 10/November/09 */ 00081 /* SIU - changed PCR[n].PA from 3 bit to 4 bit */ 00082 /* eTPU - changed WDTR_A.WDM from 1 bit to 2 bits */ 00083 /* DECFIL - changed COEF.R and TAP.R from 16 bit to */ 00084 /* 32 bit */ 00085 /* 2.0 K. Odenthal 12/February/2010 */ 00086 /* TSENS - Temperature Sensor Module added to */ 00087 /* header file */ 00088 /* ANSI C Compliance - Register structures have a */ 00089 /* Bitfield Tag ('B') tag only if there is */ 00090 /* at least one Bitfiels defined. Empty */ 00091 /* tags like 'vuint32_t:32;' are not */ 00092 /* allowed. */ 00093 /* DECFIL - removed MXCR register. This register is */ 00094 /* not supported on this part */ 00095 /* SIU - SWT_SEL bit added in SIU DIRER register */ 00096 /* EDMA - removed HRSL, HRSH and GPOR registers. */ 00097 /* Those registers are not supported in */ 00098 /* that part. */ 00099 /* ESCI - removed LDBG and DSF bits from LCR */ 00100 /* registers. Those bits are not supported */ 00101 /* in that part. */ 00102 /* Those registers are not supported in */ 00103 /* that part. */ 00104 /**************************************************************************/ 00105 /*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/ 00106 00107 #ifndef _MPC563M_H_ 00108 #define _MPC563M_H_ 00109 00110 #include "typedefs.h" 00111 00112 #ifdef __cplusplus 00113 extern "C" { 00114 00115 #endif /* 00116 */ 00117 00118 #ifdef __MWERKS__ 00119 #pragma push 00120 #pragma ANSI_strict off 00121 #endif /* 00122 */ 00123 00124 /****************************************************************************/ 00125 /* MODULE : FMPLL */ 00126 /****************************************************************************/ 00127 struct FMPLL_tag { 00128 union { 00129 vuint32_t R; 00130 struct { 00131 vuint32_t:1; 00132 vuint32_t PREDIV:3; 00133 vuint32_t MFD:5; 00134 vuint32_t:1; 00135 vuint32_t RFD:3; 00136 vuint32_t LOCEN:1; 00137 vuint32_t LOLRE:1; 00138 vuint32_t LOCRE:1; 00139 vuint32_t:1; /* Reserved in MPC563xM 00140 00141 Deleted for legacy header version [mpc5534.h]: 00142 00143 <vuint32_t DISCLK:1> */ 00144 vuint32_t LOLIRQ:1; 00145 vuint32_t LOCIRQ:1; 00146 vuint32_t:13; /* Reserved in MPC563xM 00147 00148 Deleted for legacy header version [mpc5534.h]: 00149 00150 <vuint32_t RATE:1 > 00151 00152 <vuint32_t DEPTH:2> 00153 00154 <vuint32_t EXP:10 > */ 00155 } B; 00156 } SYNCR; 00157 union { 00158 vuint32_t R; 00159 struct { 00160 vuint32_t:22; 00161 vuint32_t LOLF:1; 00162 vuint32_t LOC:1; 00163 vuint32_t MODE:1; 00164 vuint32_t PLLSEL:1; 00165 vuint32_t PLLREF:1; 00166 vuint32_t LOCKS:1; 00167 vuint32_t LOCK:1; 00168 vuint32_t LOCF:1; 00169 vuint32_t:2; /* Reserved in MPC563xM 00170 00171 Deleted for legacy header version [mpc5534.h]: 00172 00173 <vuint32_t CALDONE:1> 00174 00175 <vuint32_t CALPASS:1> */ 00176 } B; 00177 } SYNSR; 00178 union { 00179 vuint32_t R; 00180 struct { 00181 vuint32_t EMODE:1; 00182 vuint32_t CLKCFG:3; 00183 vuint32_t:8; 00184 vuint32_t EPREDIV:4; 00185 vuint32_t:9; 00186 vuint32_t EMFD:7; 00187 } B; 00188 } ESYNCR1; /* Enhanced Synthesizer Control Register 1 (ESYNCR1) (new in MPC563xM) Offset 0x0008 */ 00189 union { 00190 vuint32_t R; 00191 struct { 00192 vuint32_t:8; 00193 vuint32_t LOCEN:1; 00194 vuint32_t LOLRE:1; 00195 vuint32_t LOCRE:1; 00196 vuint32_t LOLIRQ:1; 00197 vuint32_t LOCIRQ:1; 00198 vuint32_t:17; 00199 vuint32_t ERFD:2; 00200 } B; 00201 } ESYNCR2; /* Enhanced Synthesizer Control Register 2 (ESYNCR2) (new in MPC563xM) Offset 0x000C */ 00202 int32_t FMPLL_reserved0[2]; 00203 union { 00204 vuint32_t R; 00205 struct { 00206 vuint32_t BSY:1; 00207 vuint32_t MODEN:1; 00208 vuint32_t MODSEL:1; 00209 vuint32_t MODPERIOD:13; 00210 vuint32_t:1; 00211 vuint32_t INCSTEP:15; 00212 } B; 00213 } SYNFMMR; /* Synthesizer FM Modulation Register (SYNFMMR) (new in MPC563xM) Offset 0x0018 */ 00214 }; 00215 /****************************************************************************/ 00216 /* MODULE : EBI */ 00217 /****************************************************************************/ 00218 struct CS_tag { 00219 union { 00220 vuint32_t R; 00221 struct { 00222 vuint32_t BA:17; /* */ 00223 vuint32_t:3; /* */ 00224 vuint32_t PS:1; /* */ 00225 vuint32_t:3; /* */ 00226 vuint32_t AD_MUX:1; /* new in MPC563xM */ 00227 vuint32_t BL:1; /* */ 00228 vuint32_t WEBS:1; /* */ 00229 vuint32_t TBDIP:1; /* */ 00230 vuint32_t:1; /* */ 00231 vuint32_t SETA:1; /* new in MPC563xM */ 00232 vuint32_t BI:1; /* */ 00233 vuint32_t V:1; /* */ 00234 } B; 00235 } BR; /* <URM>EBI_BR</URM> */ 00236 union { 00237 vuint32_t R; 00238 struct { 00239 vuint32_t AM:17; /* */ 00240 vuint32_t:7; /* */ 00241 vuint32_t SCY:4; /* */ 00242 vuint32_t:1; /* */ 00243 vuint32_t BSCY:2; /* */ 00244 vuint32_t:1; /* */ 00245 } B; 00246 } OR; /* <URM>EBI_OR</URM> */ 00247 }; 00248 struct CAL_CS_tag { 00249 union { 00250 vuint32_t R; 00251 struct { 00252 vuint32_t BA:17; /* */ 00253 vuint32_t:3; /* */ 00254 vuint32_t PS:1; /* */ 00255 vuint32_t:3; /* */ 00256 vuint32_t AD_MUX:1; /* new in MPC563xM */ 00257 vuint32_t BL:1; /* */ 00258 vuint32_t WEBS:1; /* */ 00259 vuint32_t TBDIP:1; /* */ 00260 vuint32_t:1; /* */ 00261 vuint32_t SETA:1; /* new in MPC563xM */ 00262 vuint32_t BI:1; /* */ 00263 vuint32_t V:1; /* */ 00264 } B; 00265 } BR; /* <URM>EBI_CAL_BR</URM> */ 00266 00267 union { 00268 vuint32_t R; 00269 struct { 00270 vuint32_t AM:17; /* */ 00271 vuint32_t:7; /* */ 00272 vuint32_t SCY:4; /* */ 00273 vuint32_t:1; /* */ 00274 vuint32_t BSCY:2; /* */ 00275 vuint32_t:1; /* */ 00276 } B; 00277 } OR; /* <URM>EBI_CAL_OR</URM> */ 00278 00279 }; 00280 00281 struct EBI_tag { 00282 union { 00283 vuint32_t R; 00284 struct { 00285 vuint32_t:5; /* */ 00286 vuint32_t SIZEEN:1; /* <URM>SIZEN</URM> */ 00287 vuint32_t SIZE:2; /* */ 00288 vuint32_t:8; /* */ 00289 vuint32_t ACGE:1; /* */ 00290 vuint32_t EXTM:1; /* */ 00291 vuint32_t EARB:1; /* */ 00292 vuint32_t EARP:2; /* */ 00293 vuint32_t:4; /* */ 00294 vuint32_t MDIS:1; /* */ 00295 vuint32_t:3; /* */ 00296 vuint32_t D16_31:1; /* new in MPC563xM */ 00297 vuint32_t AD_MUX:1; /* new in MPC563xM */ 00298 vuint32_t DBM:1; /* */ 00299 } B; 00300 } MCR; /* EBI Module Configuration Register (MCR) <URM>EBI_MCR</URM> @baseaddress + 0x00 */ 00301 00302 uint32_t EBI_reserved1[1]; 00303 00304 union { 00305 vuint32_t R; 00306 struct { 00307 vuint32_t:30; /* */ 00308 vuint32_t TEAF:1; /* */ 00309 vuint32_t BMTF:1; /* */ 00310 } B; 00311 } TESR; /* EBI Transfer Error Status Register (TESR) <URM>EBI_TESR</URM> @baseaddress + 0x08 */ 00312 00313 union { 00314 vuint32_t R; 00315 struct { 00316 vuint32_t:16; /* */ 00317 vuint32_t BMT:8; /* */ 00318 vuint32_t BME:1; /* */ 00319 vuint32_t:7; /* */ 00320 } B; 00321 } BMCR; /* <URM>EBI_BMCR</URM> @baseaddress + 0x0C */ 00322 00323 struct CS_tag CS[4]; 00324 00325 uint32_t EBI_reserved2[4]; 00326 00327 /* Calibration registers */ 00328 struct CAL_CS_tag CAL_CS[4]; 00329 00330 }; /* end of EBI_tag */ 00331 /****************************************************************************/ 00332 /* MODULE : FLASH */ 00333 /****************************************************************************/ 00334 /* 3 flash modules implemented. */ 00335 /* HBL and HBS not used in Bank 0 / Array 0 */ 00336 /* LML, SLL, LMS, PFCR1, PFAPR, PFCR2, and PFCR3 not used in */ 00337 /* Bank 1 / Array 1 or Bank 1 / Array 3 */ 00338 /****************************************************************************/ 00339 struct FLASH_tag { 00340 union { /* Module Configuration Register (MCR)@baseaddress + 0x00 */ 00341 vuint32_t R; 00342 struct { 00343 vuint32_t EDC:1; /* ECC Data Correction (Read/Clear) */ 00344 vuint32_t:4; /* Reserved */ 00345 vuint32_t SIZE:3; /* Array Size (Read Only) */ 00346 vuint32_t:1; /* Reserved */ 00347 vuint32_t LAS:3; /* Low Address Space (Read Only) */ 00348 vuint32_t:3; /* Reserved */ 00349 vuint32_t MAS:1; /* Mid Address Space (Read Only) */ 00350 vuint32_t EER:1; /* ECC Event Error (Read/Clear) *//* <LEGACY> BBEPE and EPE </LEGACY> */ 00351 vuint32_t RWE:1; /* Read While Write Event Error (Read/Clear) */ 00352 vuint32_t:2; /* Reserved */ 00353 vuint32_t PEAS:1; /* Program/Erase Access Space (Read Only) */ 00354 vuint32_t DONE:1; /* Status (Read Only) */ 00355 vuint32_t PEG:1; /* Program/Erase Good (Read Only) */ 00356 vuint32_t:4; /* Reserved *//* <LEGACY> RSD PEG STOP RSVD </LEGACY> */ 00357 vuint32_t PGM:1; /* Program (Read/Write) */ 00358 vuint32_t PSUS:1; /* Program Suspend (Read/Write) */ 00359 vuint32_t ERS:1; /* Erase (Read/Write) */ 00360 vuint32_t ESUS:1; /* Erase Suspend (Read/Write) */ 00361 vuint32_t EHV:1; /* Enable High Voltage (Read/Write) */ 00362 } B; 00363 } MCR; 00364 00365 union { /* Low/Mid-Address Space Block Locking Register (LML)@baseaddress + 0x04 */ 00366 vuint32_t R; 00367 struct { 00368 vuint32_t LME:1; /* Low/Mid address space block enable (Read Only) */ 00369 vuint32_t:10; /* Reserved */ 00370 vuint32_t SLOCK:1; /*<URM>SLK</URM> *//* Shadow address space block lock (Read/Write) */ 00371 vuint32_t:2; /* Reserved */ 00372 vuint32_t MLOCK:2; /*<URM>MLK</URM> *//* Mid address space block lock (Read/Write) */ 00373 vuint32_t:8; /* Reserved */ 00374 vuint32_t LLOCK:8; /*<URM>LLK</URM> *//* Low address space block lock (Read/Write) */ 00375 } B; 00376 } LMLR; /*<URM>LML</URM> */ 00377 00378 union { /* High-Address Space Block Locking Register (HBL) - @baseaddress + 0x08 */ 00379 vuint32_t R; 00380 struct { 00381 vuint32_t HBE:1; /* High address space Block Enable (Read Only) */ 00382 vuint32_t:27; /* Reserved */ 00383 vuint32_t HBLOCK:4; /* High address space block lock (Read/Write) */ 00384 } B; 00385 } HLR; /*<URM>HBL</URM> */ 00386 00387 union { /* Secondary Low/Mid-Address Space Block Locking Register (SLL)@baseaddress + 0x0C */ 00388 vuint32_t R; 00389 struct { 00390 vuint32_t SLE:1; /* Secondary low/mid address space block enable (Read Only) */ 00391 vuint32_t:10; /* Reserved */ 00392 vuint32_t SSLOCK:1; /*<URM>SSLK</URM> *//* Secondary shadow address space block lock (Read/Write) */ 00393 vuint32_t:2; /* Reserved */ 00394 vuint32_t SMLOCK:2; /*<URM>SMK</URM> *//* Secondary mid address space block lock (Read/Write) */ 00395 vuint32_t:8; /* Reserved */ 00396 vuint32_t SLLOCK:8; /*<URM>SLK</URM> *//* Secondary low address space block lock (Read/Write) */ 00397 } B; 00398 } SLMLR; /*<URM>SLL</URM> */ 00399 00400 union { /* Low/Mid-Address Space Block Select Register (LMS)@baseaddress + 0x10 */ 00401 vuint32_t R; 00402 struct { 00403 vuint32_t:14; /* Reserved */ 00404 vuint32_t MSEL:2; /*<URM>MSL</URM> *//* Mid address space block select (Read/Write) */ 00405 vuint32_t:8; /* Reserved */ 00406 vuint32_t LSEL:8; /*<URM>LSL</URM> *//* Low address space block select (Read/Write) */ 00407 } B; 00408 } LMSR; /*<URM>LMS</URM> */ 00409 00410 union { /* High-Address Space Block Select Register (HBS) - not used@baseaddress + 0x14 */ 00411 vuint32_t R; 00412 struct { 00413 vuint32_t:28; /* Reserved */ 00414 vuint32_t HBSEL:4; /*<URM>HSL</URM> *//* High address space block select (Read/Write) */ 00415 } B; 00416 } HSR; /*<URM>HBS</URM> */ 00417 00418 union { /* Address Register (ADR)@baseaddress + 0x18 */ 00419 vuint32_t R; 00420 struct { 00421 vuint32_t SAD:1; /* Shadow address (Read Only) */ 00422 vuint32_t:10; /* Reserved */ 00423 vuint32_t ADDR:18; /*<URM>AD</URM> *//* Address 20-3 (Read Only) */ 00424 vuint32_t:3; /* Reserved */ 00425 } B; 00426 } AR; /*<URM>ADR</URM> */ 00427 00428 union { /* @baseaddress + 0x1C */ 00429 vuint32_t R; 00430 struct { 00431 vuint32_t:7; /* Reserved */ 00432 vuint32_t GCE:1; /* Global Configuration Enable (Read/Write) */ 00433 vuint32_t:4; /* Reserved */ 00434 vuint32_t M3PFE:1; /* Master 3 Prefetch Enable (Read/Write) */ 00435 vuint32_t M2PFE:1; /* Master 2 Prefetch Enable (Read/Write) */ 00436 vuint32_t M1PFE:1; /* Master 1 Prefetch Enable (Read/Write) */ 00437 vuint32_t M0PFE:1; /* Master 0 Prefetch Enable (Read/Write) */ 00438 vuint32_t APC:3; /* Address Pipelining Control (Read/Write) */ 00439 vuint32_t WWSC:2; /* Write Wait State Control (Read/Write) */ 00440 vuint32_t RWSC:3; /* Read Wait State Control (Read/Write) */ 00441 vuint32_t:1; /* Reserved */ 00442 vuint32_t DPFEN:1; /*<URM>DPFE</URM> *//* Data Prefetch Enable (Read/Write) */ 00443 vuint32_t:1; /* Reserved */ 00444 vuint32_t IPFEN:1; /*<URM>IPFE</URM> *//* Instruction Prefetch Enable (Read/Write) */ 00445 vuint32_t:1; /* Reserved */ 00446 vuint32_t PFLIM:2; /* Prefetch Limit (Read/Write) */ 00447 vuint32_t BFEN:1; /*<URM>BFE</URM> *//* Buffer Enable (Read/Write) */ 00448 } B; 00449 } BIUCR; /*<URM>PFCR1</URM> */ 00450 00451 union { /* @baseaddress + 0x20 */ 00452 vuint32_t R; 00453 struct { 00454 vuint32_t:24; /* Reserved */ 00455 vuint32_t M3AP:2; /* Master 3 Access Protection (Read/Write) */ 00456 vuint32_t M2AP:2; /* Master 2 Access Protection (Read/Write) */ 00457 vuint32_t M1AP:2; /* Master 1 Access Protection (Read/Write) */ 00458 vuint32_t M0AP:2; /* Master 0 Access Protection (Read/Write) */ 00459 } B; 00460 } BIUAPR; /*<URM>PFAPR</URM> */ 00461 00462 union { /* @baseaddress + 0x24 */ 00463 vuint32_t R; 00464 struct { 00465 vuint32_t LBCFG:2; /* Line Buffer Configuration (Read/Write) */ 00466 vuint32_t:30; /* Reserved */ 00467 } B; 00468 } BIUCR2; 00469 00470 union { /* @baseaddress + 0x28 */ 00471 vuint32_t R; 00472 struct { 00473 vuint32_t:25; /* Reserved */ 00474 vuint32_t B1_DPFE:1; /* Bank1 Data Prefetch Enable (Read/Write) */ 00475 vuint32_t:1; /* Reserved */ 00476 vuint32_t B1_IPFE:1; /* Bank1 Instruction Prefetch Enable (Read/Write) */ 00477 vuint32_t:1; /* Reserved */ 00478 vuint32_t B1_PFLIM:2; /* Bank1 Prefetch Limit (Read/Write) */ 00479 vuint32_t B1_BFE:1; /* Bank1 Buffer Enable (Read/Write) */ 00480 } B; 00481 } PFCR3; 00482 00483 int32_t FLASH_reserverd_89[4]; 00484 00485 union { /* User Test 0 (UT0) register@baseaddress + 0x3c */ 00486 vuint32_t R; 00487 struct { 00488 vuint32_t UTE:1; /* User test enable (Read/Clear) */ 00489 vuint32_t SBCE:1; /* Single bit correction enable (Read/Clear) */ 00490 vuint32_t:6; /* Reserved */ 00491 vuint32_t DSI:8; /* Data syndrome input (Read/Write) */ 00492 vuint32_t:9; /* Reserved */ 00493 vuint32_t:1; /* Reserved (Read/Write) */ 00494 vuint32_t MRE:1; /* Margin Read Enable (Read/Write) */ 00495 vuint32_t MRV:1; /* Margin Read Value (Read/Write) */ 00496 vuint32_t EIE:1; /* ECC data Input Enable (Read/Write) */ 00497 vuint32_t AIS:1; /* Array Integrity Sequence (Read/Write) */ 00498 vuint32_t AIE:1; /* Array Integrity Enable (Read/Write) */ 00499 vuint32_t AID:1; /* Array Integrity Done (Read Only) */ 00500 } B; 00501 } UT0; 00502 00503 union { /* User Test 1 (UT1) register@baseaddress + 0x40 */ 00504 vuint32_t R; 00505 struct { 00506 vuint32_t DAI:32; /* Data Array Input (Read/Write) */ 00507 } B; 00508 } UT1; 00509 00510 union { /* User Test 2 (UT2) register@baseaddress + 0x44 */ 00511 vuint32_t R; 00512 struct { 00513 vuint32_t DAI:32; /* Data Array Input (Read/Write) */ 00514 } B; 00515 } UT2; 00516 00517 union { /* User Multiple Input Signature Register 0-5 (UMISR[5])@baseaddress + 0x48 */ 00518 vuint32_t R; 00519 struct { 00520 vuint32_t MS:32; /* Multiple input Signature (Read/Write) */ 00521 } B; 00522 } UMISR[5]; 00523 00524 }; /* end of FLASH_tag */ 00525 /****************************************************************************/ 00526 /* MODULE : SIU */ 00527 /****************************************************************************/ 00528 struct SIU_tag { 00529 union { 00530 vuint32_t R; 00531 struct { 00532 vuint32_t S_F:1; /* Identifies the Manufacturer <URM>S/F</URM> */ 00533 vuint32_t FLASH_SIZE_1:4; /* Define major Flash memory size (see Table 15-4 for details) <URM>Flash Size 1</URM> */ 00534 vuint32_t FLASH_SIZE_2:4; /* Define Flash memory size, small granularity (see Table 15-5 for details) <URM>Flash Size 1</URM> */ 00535 vuint32_t TEMP_RANGE:2; /* Define maximum operating range <URM>Temp Range</URM> */ 00536 vuint32_t:1; /* Reserved for future enhancements */ 00537 vuint32_t MAX_FREQ:2; /* Define maximum device speed <URM>Max Freq</URM> */ 00538 vuint32_t:1; /* Reserved for future enhancements */ 00539 vuint32_t SUPPLY:1; /* Defines if the part is 5V or 3V <URM>Supply</URM> */ 00540 vuint32_t PART_NUMBER:8; /* Contain the ASCII representation of the character that indicates the product <URM>Part Number</URM> */ 00541 vuint32_t TBD:1; /* 1-bit field defined by SoC to describe optional feature, e.g., additional SPI */ 00542 vuint32_t:2; /* Reserved for future enhancements */ 00543 vuint32_t EE:1; /* Indicates if Data Flash is present */ 00544 vuint32_t:3; /* Reserved for future enhancements */ 00545 vuint32_t FR:1; /* Indicates if Data FlexRay is present */ 00546 } B; 00547 } MIDR2; /* MCU ID Register 2 <URM>SIU_MIDR2</URM> @baseaddress + 0x4 */ 00548 00549 union { 00550 vuint32_t R; 00551 struct { 00552 vuint32_t PARTNUM:16; /* Device part number: 0x5633 */ 00553 vuint32_t CSP:1; /* CSP configuration (new in MPC563xM) */ 00554 vuint32_t PKG:5; /* Indicate the package the die is mounted in. (new in MPC563xM) */ 00555 vuint32_t:2; /* Reserved */ 00556 vuint32_t MASKNUM:8; /* MCU major mask number; updated for each complete resynthesis. MCU minor mask number; updated for each mask revision */ 00557 } B; 00558 } MIDR; /* MCU ID Register (MIDR) <URM>SIU_MIDR</URM> @baseaddress + 0x8 */ 00559 00560 union { 00561 vuint32_t R; 00562 } TST; /* SIU Test Register (SIU_TST) <URM>SIU_TST</URM> @baseaddress + 0xC */ 00563 00564 union { 00565 vuint32_t R; 00566 struct { 00567 vuint32_t PORS:1; /* Power-On Reset Status */ 00568 vuint32_t ERS:1; /* External Reset Status */ 00569 vuint32_t LLRS:1; /* Loss of Lock Reset Status */ 00570 vuint32_t LCRS:1; /* Loss of Clock Reset Status */ 00571 vuint32_t WDRS:1; /* Watchdog Timer/Debug Reset Status */ 00572 vuint32_t CRS:1; /* Checkstop Reset Status */ 00573 vuint32_t SWTRS:1; /* Software Watchdog Timer Reset Status (new in MPC563xM) */ 00574 vuint32_t:7; /* */ 00575 vuint32_t SSRS:1; /* Software System Reset Status */ 00576 vuint32_t SERF:1; /* Software External Reset Flag */ 00577 vuint32_t WKPCFG:1; /* Weak Pull Configuration Pin Status */ 00578 vuint32_t:11; /* */ 00579 vuint32_t ABR:1; /* Auto Baud Rate (new in MPC563xM) */ 00580 vuint32_t BOOTCFG:2; /* Reset Configuration Pin Status */ 00581 vuint32_t RGF:1; /* RESET Glitch Flag */ 00582 } B; 00583 } RSR; /* Reset Status Register (SIU_RSR) <URM>SIU_RSR</URM> @baseaddress + 0x10 */ 00584 00585 union { 00586 vuint32_t R; 00587 struct { 00588 vuint32_t SSR:1; /* Software System Reset */ 00589 vuint32_t SER:1; /* Software External Reset */ 00590 vuint32_t:14; /* */ 00591 vuint32_t CRE:1; /* Checkstop Reset Enable */ 00592 vuint32_t:15; /* */ 00593 } B; 00594 } SRCR; /* System Reset Control Register (SRCR) <URM>SIU_SRCR</URM> @baseaddress + 0x14 */ 00595 00596 union { 00597 vuint32_t R; 00598 struct { 00599 vuint32_t NMI:1; /* Non-Maskable Interrupt Flag (new in MPC563xM) */ 00600 vuint32_t:7; /* */ 00601 vuint32_t SWT:1; /* Software Watch Dog Timer Interrupt Flag, from platform (new in MPC563xM) */ 00602 vuint32_t:7; /* */ 00603 vuint32_t EIF15:1; /* External Interrupt Request Flag x */ 00604 vuint32_t EIF14:1; /* External Interrupt Request Flag x */ 00605 vuint32_t EIF13:1; /* External Interrupt Request Flag x */ 00606 vuint32_t EIF12:1; /* External Interrupt Request Flag x */ 00607 vuint32_t EIF11:1; /* External Interrupt Request Flag x */ 00608 vuint32_t EIF10:1; /* External Interrupt Request Flag x */ 00609 vuint32_t EIF9:1; /* External Interrupt Request Flag x */ 00610 vuint32_t EIF8:1; /* External Interrupt Request Flag x */ 00611 vuint32_t:3; /* (reserved in MPC563xM) */ 00612 vuint32_t EIF4:1; /* External Interrupt Request Flag x */ 00613 vuint32_t EIF3:1; /* External Interrupt Request Flag x */ 00614 vuint32_t:2; /* (reserved in MPC563xM) */ 00615 vuint32_t EIF0:1; /* External Interrupt Request Flag x */ 00616 } B; 00617 } EISR; /* SIU External Interrupt Status Register (EISR) <URM>SIU_EISR</URM> @baseaddress + 0x18 */ 00618 00619 union { 00620 vuint32_t R; 00621 struct { 00622 vuint32_t NMI_SEL:1; /* NMI Interrupt Platform Input Selection (new in MPC563xM) */ 00623 vuint32_t:7; /* */ 00624 vuint32_t SWT_SEL:1; 00625 vuint32_t:7; 00626 vuint32_t EIRE15:1; /* External DMA/Interrupt Request Enable x */ 00627 vuint32_t EIRE14:1; /* External DMA/Interrupt Request Enable x */ 00628 vuint32_t EIRE13:1; /* External DMA/Interrupt Request Enable x */ 00629 vuint32_t EIRE12:1; /* External DMA/Interrupt Request Enable x */ 00630 vuint32_t EIRE11:1; /* External DMA/Interrupt Request Enable x */ 00631 vuint32_t EIRE10:1; /* External DMA/Interrupt Request Enable x */ 00632 vuint32_t EIRE9:1; /* External DMA/Interrupt Request Enable x */ 00633 vuint32_t EIRE8:1; /* External DMA/Interrupt Request Enable x */ 00634 vuint32_t EIRE7:1; /* External DMA/Interrupt Request Enable x */ 00635 vuint32_t EIRE6:1; /* External DMA/Interrupt Request Enable x */ 00636 vuint32_t EIRE5:1; /* External DMA/Interrupt Request Enable x */ 00637 vuint32_t EIRE4:1; /* External DMA/Interrupt Request Enable x */ 00638 vuint32_t EIRE3:1; /* External DMA/Interrupt Request Enable x */ 00639 vuint32_t EIRE2:1; /* External DMA/Interrupt Request Enable x */ 00640 vuint32_t EIRE1:1; /* External DMA/Interrupt Request Enable x */ 00641 vuint32_t EIRE0:1; /* External DMA/Interrupt Request Enable x */ 00642 } B; 00643 } DIRER; /* DMA/Interrupt Request Enable Register (DIRER) <URM>SIU_DIRER</URM> @baseaddress + 0x1C */ 00644 00645 union { 00646 vuint32_t R; 00647 struct { 00648 vuint32_t:28; /* */ 00649 vuint32_t DIRS3:1; /* DMA/Interrupt Request Select x */ 00650 vuint32_t:2; /* reserved in MPC563xM */ 00651 vuint32_t DIRS0:1; /* DMA/Interrupt Request Select x */ 00652 } B; 00653 } DIRSR; /* DMA/Interrupt Request Select Register (DIRSR) <URM>SIU_DIRSR</URM> @baseaddress + 0x20 */ 00654 00655 union { 00656 vuint32_t R; 00657 struct { 00658 vuint32_t:16; /* */ 00659 vuint32_t OVF15:1; /* Overrun Flag x */ 00660 vuint32_t OVF14:1; /* Overrun Flag x */ 00661 vuint32_t OVF13:1; /* Overrun Flag x */ 00662 vuint32_t OVF12:1; /* Overrun Flag x */ 00663 vuint32_t OVF11:1; /* Overrun Flag x */ 00664 vuint32_t OVF10:1; /* Overrun Flag x */ 00665 vuint32_t OVF9:1; /* Overrun Flag x */ 00666 vuint32_t OVF8:1; /* Overrun Flag x */ 00667 vuint32_t:3; /* reserved in MPC563xM */ 00668 vuint32_t OVF4:1; /* Overrun Flag x */ 00669 vuint32_t OVF3:1; /* Overrun Flag x */ 00670 vuint32_t:2; /* reserved in MPC563xM */ 00671 vuint32_t OVF0:1; /* Overrun Flag x */ 00672 } B; 00673 } OSR; /* Overrun Status Register (OSR) <URM>SIU_OSR</URM> @baseaddress + 0x24 */ 00674 00675 union { 00676 vuint32_t R; 00677 struct { 00678 vuint32_t:16; /* */ 00679 vuint32_t ORE15:1; /* Overrun Request Enable x */ 00680 vuint32_t ORE14:1; /* Overrun Request Enable x */ 00681 vuint32_t ORE13:1; /* Overrun Request Enable x */ 00682 vuint32_t ORE12:1; /* Overrun Request Enable x */ 00683 vuint32_t ORE11:1; /* Overrun Request Enable x */ 00684 vuint32_t ORE10:1; /* Overrun Request Enable x */ 00685 vuint32_t ORE9:1; /* Overrun Request Enable x */ 00686 vuint32_t ORE8:1; /* Overrun Request Enable x */ 00687 vuint32_t:3; /* reserved in MPC563xM */ 00688 vuint32_t ORE4:1; /* Overrun Request Enable x */ 00689 vuint32_t ORE3:1; /* Overrun Request Enable x */ 00690 vuint32_t:2; /* reserved in MPC563xM */ 00691 vuint32_t ORE0:1; /* Overrun Request Enable x */ 00692 } B; 00693 } ORER; /* Overrun Request Enable Register (ORER) <URM>SIU_ORER</URM> @baseaddress + 0x28 */ 00694 00695 union { 00696 vuint32_t R; 00697 struct { 00698 vuint32_t NMIRE:1; /* NMI Rising-Edge Event Enable x (new in MPC563xM) */ 00699 vuint32_t:15; /* reserved in MPC563xM */ 00700 vuint32_t IREE15:1; /* IRQ Rising-Edge Event Enable x */ 00701 vuint32_t IREE14:1; /* IRQ Rising-Edge Event Enable x */ 00702 vuint32_t IREE13:1; /* IRQ Rising-Edge Event Enable x */ 00703 vuint32_t IREE12:1; /* IRQ Rising-Edge Event Enable x */ 00704 vuint32_t IREE11:1; /* IRQ Rising-Edge Event Enable x */ 00705 vuint32_t IREE10:1; /* IRQ Rising-Edge Event Enable x */ 00706 vuint32_t IREE9:1; /* IRQ Rising-Edge Event Enable x */ 00707 vuint32_t IREE8:1; /* IRQ Rising-Edge Event Enable x */ 00708 vuint32_t:3; /* reserved in MPC563xM */ 00709 vuint32_t IREE4:1; /* IRQ Rising-Edge Event Enable x */ 00710 vuint32_t IREE3:1; /* IRQ Rising-Edge Event Enable x */ 00711 vuint32_t:2; /* reserved in MPC563xM */ 00712 vuint32_t IREE0:1; /* IRQ Rising-Edge Event Enable x */ 00713 } B; 00714 } IREER; /* External IRQ Rising-Edge Event Enable Register (IREER) <URM>SIU_IREER</URM> @baseaddress + 0x2C */ 00715 00716 union { 00717 vuint32_t R; 00718 struct { 00719 vuint32_t NMIFE:1; /* NMI Falling-Edge Event Enable x (new in MPC563xM) */ 00720 vuint32_t Reserverd:15; /* */ 00721 vuint32_t IFEE15:1; /* IRQ Falling-Edge Event Enable x */ 00722 vuint32_t IFEE14:1; /* IRQ Falling-Edge Event Enable x */ 00723 vuint32_t IFEE13:1; /* IRQ Falling-Edge Event Enable x */ 00724 vuint32_t IFEE12:1; /* IRQ Falling-Edge Event Enable x */ 00725 vuint32_t IFEE11:1; /* IRQ Falling-Edge Event Enable x */ 00726 vuint32_t IFEE10:1; /* IRQ Falling-Edge Event Enable x */ 00727 vuint32_t IFEE9:1; /* IRQ Falling-Edge Event Enable x */ 00728 vuint32_t IFEE8:1; /* IRQ Falling-Edge Event Enable x */ 00729 vuint32_t:3; /* reserved in MPC563xM */ 00730 vuint32_t IFEE4:1; /* IRQ Falling-Edge Event Enable x */ 00731 vuint32_t IFEE3:1; /* IRQ Falling-Edge Event Enable x */ 00732 vuint32_t:2; /* reserved in MPC563xM */ 00733 vuint32_t IFEE0:1; /* IRQ Falling-Edge Event Enable x */ 00734 } B; 00735 } IFEER; /* External IRQ Falling-Edge Event Enable Regi (IFEER) <URM>SIU_IFEER</URM> @baseaddress + 0x30 */ 00736 00737 union { 00738 vuint32_t R; 00739 struct { 00740 vuint32_t:28; /* */ 00741 vuint32_t DFL:4; /* Digital Filter Length */ 00742 } B; 00743 } IDFR; /* External IRQ Digital Filter Register (IDFR) <URM>SIU_IDFR</URM> @baseaddress + 0x40 */ 00744 00745 int32_t SIU_reserverd_153[3]; 00746 00747 union { 00748 vuint16_t R; 00749 struct { 00750 vuint16_t:2; /* */ 00751 vuint16_t PA:4; /* */ 00752 vuint16_t OBE:1; /* */ 00753 vuint16_t IBE:1; /* */ 00754 vuint16_t DSC:2; /* */ 00755 vuint16_t ODE:1; /* */ 00756 vuint16_t HYS:1; /* */ 00757 vuint16_t SRC:2; /* */ 00758 vuint16_t WPE:1; /* */ 00759 vuint16_t WPS:1; /* */ 00760 } B; 00761 } PCR[512]; /* Pad Configuration Register (PCR) <URM>SIU_PCR</URM> @baseaddress + 0x600 */ 00762 00763 int32_t SIU_reserverd_164[112]; 00764 00765 union { 00766 vuint8_t R; 00767 struct { 00768 vuint8_t:7; /* */ 00769 vuint8_t PDO:1; /* */ 00770 } B; 00771 } GPDO[512]; /* GPIO Pin Data Output Register (GPDO) <URM>SIU_GDPO</URM> @baseaddress + 0x800 */ 00772 00773 union { 00774 vuint8_t R; 00775 struct { 00776 vuint8_t:7; /* */ 00777 vuint8_t PDI:1; /* */ 00778 } B; 00779 } GPDI[256]; /* GPIO Pin Data Input Register (GDPI) <URM>SIU_GDPI</URM> @baseaddress + 0x900 */ 00780 00781 union { 00782 vuint32_t R; 00783 struct { 00784 vuint32_t TSEL5:2; /* eQADC Trigger 5 Input */ 00785 vuint32_t TSEL4:2; /* eQADC Trigger 4 Input */ 00786 vuint32_t TSEL3:2; /* eQADC Trigger 3 Input */ 00787 vuint32_t TSEL2:2; /* eQADC Trigger 4 Input */ 00788 vuint32_t TSEL1:2; /* eQADC Trigger 1 Input */ 00789 vuint32_t TSEL0:2; /* eQADC Trigger 0 Input */ 00790 vuint32_t:20; /* */ 00791 } B; 00792 } ETISR; /* eQADC Trigger Input Select Register (ETISR) <URM>SIU_ETISR</URM> @baseaddress + 0x904 */ 00793 00794 union { 00795 vuint32_t R; 00796 struct { 00797 vuint32_t ESEL15:2; /* External IRQ Input Select x */ 00798 vuint32_t ESEL14:2; /* External IRQ Input Select x */ 00799 vuint32_t ESEL13:2; /* External IRQ Input Select x */ 00800 vuint32_t ESEL12:2; /* External IRQ Input Select x */ 00801 vuint32_t ESEL11:2; /* External IRQ Input Select x */ 00802 vuint32_t ESEL10:2; /* External IRQ Input Select x */ 00803 vuint32_t ESEL9:2; /* External IRQ Input Select x */ 00804 vuint32_t ESEL8:2; /* External IRQ Input Select x */ 00805 vuint32_t ESEL7:2; /* External IRQ Input Select x */ 00806 vuint32_t ESEL6:2; /* External IRQ Input Select x */ 00807 vuint32_t ESEL5:2; /* External IRQ Input Select x */ 00808 vuint32_t ESEL4:2; /* External IRQ Input Select x */ 00809 vuint32_t ESEL3:2; /* External IRQ Input Select x */ 00810 vuint32_t ESEL2:2; /* External IRQ Input Select x */ 00811 vuint32_t ESEL1:2; /* External IRQ Input Select x */ 00812 vuint32_t ESEL0:2; /* External IRQ Input Select x */ 00813 } B; 00814 } EIISR; /* External IRQ Input Select Register (EIISR) <URM>SIU_EIISR</URM> @baseaddress + 0x908 */ 00815 00816 union { 00817 vuint32_t R; 00818 struct { 00819 vuint32_t:8; /* reserved in MPC563xM */ 00820 vuint32_t SINSELB:2; /* DSPI_B Data Input Select <URM>SIN-SELB</URM> */ 00821 vuint32_t SSSELB:2; /* DSPI_B Slave Select Input Select <URM>SS-SELB</URM> */ 00822 vuint32_t SCKSELB:2; /* DSPI_B Clock Input Select <URM>SCK-SELB</URM> */ 00823 vuint32_t TRIGSELB:2; /* DSPI_B Trigger Input Select <URM>TRIG-SELB</URM> */ 00824 vuint32_t SINSELC:2; /* DSPI_C Data Input Select <URM>SIN-SELC</URM> */ 00825 vuint32_t SSSELC:2; /* DSPI_C Slave Select Input Select <URM>SSSELC</URM> */ 00826 vuint32_t SCKSELC:2; /* DSPI_C Clock Input Select <URM>SCK-SELC</URM> */ 00827 vuint32_t TRIGSELC:2; /* DSPI_C Trigger Input Select <URM>TRIG-SELC</URM> */ 00828 vuint32_t:8; /* reserved in MPC563xM */ 00829 } B; 00830 } DISR; /* DSPI Input Select Register (DISR) <URM>SIU_DISR</URM> @baseaddress + 0x90c */ 00831 00832 union { 00833 vuint32_t R; 00834 struct { 00835 vuint32_t:2; /* */ 00836 vuint32_t ETSEL5:5; /* eQADC queue X Enhanced Trigger Selection <URM>eTSEL5</URM> */ 00837 vuint32_t ETSEL4:5; /* eQADC queue X Enhanced Trigger Selection <URM>eTSEL4</URM> */ 00838 vuint32_t ETSEL3:5; /* eQADC queue X Enhanced Trigger Selection <URM>eTSEL3</URM> */ 00839 vuint32_t ETSEL2:5; /* eQADC queue X Enhanced Trigger Selection <URM>eTSEL2</URM> */ 00840 vuint32_t ETSEL1:5; /* eQADC queue X Enhanced Trigger Selection <URM>eTSEL1</URM> */ 00841 vuint32_t ETSEL0:5; /* eQADC queue X Enhanced Trigger Selection <URM>eTSEL0</URM> */ 00842 } B; 00843 } ISEL3; /* MUX Select Register 3 (ISEL3) (new in MPC563xM) <URM>SIU_ISEL3</URM> @baseaddress + 0x920 */ 00844 00845 int32_t SIU_reserverd_214[4]; 00846 00847 union { 00848 vuint32_t R; 00849 struct { 00850 vuint32_t:11; /* */ 00851 vuint32_t ESEL5:1; /* <URM>eSEL5</URM> */ 00852 vuint32_t:3; /* */ 00853 vuint32_t ESEL4:1; /* <URM>eSEL4</URM> */ 00854 vuint32_t:3; /* */ 00855 vuint32_t ESEL3:1; /* <URM>eSEL3</URM> */ 00856 vuint32_t:3; /* */ 00857 vuint32_t ESEL2:1; /* <URM>eSEL2</URM> */ 00858 vuint32_t:3; /* */ 00859 vuint32_t ESEL1:1; /* <URM>eSEL1</URM> */ 00860 vuint32_t:3; /* */ 00861 vuint32_t ESEL0:1; /* <URM>eSEL0</URM> */ 00862 } B; 00863 } ISEL8; /* MUX Select Register 8 (ISEL8) (new in MPC563xM) <URM>SIU_ISEL8</URM> @baseaddress + 0x924 */ 00864 00865 union { 00866 vuint32_t R; 00867 struct { 00868 vuint32_t:27; /* */ 00869 vuint32_t ETSEL0A:5; /* <URM>eTSEL0A</URM> */ 00870 } B; 00871 } ISEL9; /* MUX Select Register 9(ISEL9) <URM>SIU_ISEL9</URM> @baseaddress + 0x980 */ 00872 00873 int32_t SIU_reserverd_230[22]; 00874 00875 union { 00876 vuint32_t R; 00877 struct { 00878 vuint32_t:14; /* */ 00879 vuint32_t MATCH:1; /* Compare Register Match */ 00880 vuint32_t DISNEX:1; /* Disable Nexus */ 00881 vuint32_t:14; /* */ 00882 vuint32_t CRSE:1; /* Calibration Reflection Suppression Enable (new in MPC563xM) */ 00883 vuint32_t:1; /* */ 00884 } B; 00885 } CCR; /* Chip Configuration Register (CCR) <URM>SIU_CCR</URM> @baseaddress + 0x984 */ 00886 00887 union { 00888 vuint32_t R; 00889 struct { 00890 vuint32_t:28; /* The ENGDIV bit is reserved in MPC563xM */ 00891 vuint32_t EBTS:1; /* External Bus Tap Select */ 00892 vuint32_t:1; /* */ 00893 vuint32_t EBDF:2; /* External Bus Division Factor */ 00894 } B; 00895 } ECCR; /* External Clock Control Register (ECCR) <URM>SIU_ECCR</URM> @baseaddress + 0x988 */ 00896 00897 union { 00898 vuint32_t R; 00899 } CARH; /* Compare A High Register (CARH) <URM>SIU_CMPAH</URM> @baseaddress + 0x98C */ 00900 00901 union { 00902 vuint32_t R; 00903 } CARL; /* Compare A Low Register (CARL) <URM>SIU_CMPAL</URM> @baseaddress + 0x990 */ 00904 00905 union { 00906 vuint32_t R; 00907 } CBRH; /* Compare B High Register (CBRH) <URM>SIU_CMPBH</URM> @baseaddress + 0x994 */ 00908 00909 union { 00910 vuint32_t R; 00911 } CBRL; /* Compare B Low Register (CBRL) <URM>SIU_CMPBL</URM> @baseaddress + 0x9A0 */ 00912 00913 int32_t SIU_reserverd_250[2]; 00914 00915 union { 00916 vuint32_t R; 00917 struct { 00918 vuint32_t:27; /* Reserved */ 00919 vuint32_t BYPASS:1; /* Bypass bit <URM>BY-PASS</URM> */ 00920 vuint32_t SYSCLKDIV:2; /* System Clock Divide <URM>SYS-CLKDIV</URM> */ 00921 vuint32_t:2; /* Reserved */ 00922 } B; 00923 } SYSDIV; /* System Clock Register (SYSDIV) (new in MPC563xM) <URM>SIU_SYSDIV</URM> @baseaddress + 0x9A4 */ 00924 00925 union { 00926 vuint32_t R; 00927 struct { 00928 vuint32_t CPUSTP:1; /* CPU stop request. When asserted, a stop request is sent to the following modules: */ 00929 vuint32_t:2; /* Reserved */ 00930 vuint32_t SWTSTP:1; /* SWT stop request. When asserted, a stop request is sent to the Software Watchdog */ 00931 vuint32_t:1; /* Reserved */ 00932 vuint32_t TPUSTP:1; /* eTPU stop request. When asserted, a stop request is sent to the eTPU module. */ 00933 vuint32_t NPCSTP:1; /* Nexus stop request. When asserted, a stop request is sent to the Nexus Controller. */ 00934 vuint32_t EBISTP:1; /* EBI stop request. When asserted, a stop request is sent to the external bus */ 00935 vuint32_t ADCSTP:1; /* eQADC stop request. When asserted, a stop request is sent to the eQADC module. */ 00936 vuint32_t:1; /* Reserved */ 00937 vuint32_t MIOSSTP:1; /* Stop mode request */ 00938 vuint32_t DFILSTP:1; /* Decimation filter stop request. When asserted, a stop request is sent to the */ 00939 vuint32_t:1; /* Reserved */ 00940 vuint32_t PITSTP:1; /* PIT stop request. When asserted, a stop request is sent to the periodical internal */ 00941 vuint32_t:3; /* Reserved */ 00942 vuint32_t CNCSTP:1; /* FlexCAN C stop request. When asserted, a stop request is sent to the FlexCAN C */ 00943 vuint32_t:1; /* Reserved */ 00944 vuint32_t CNASTP:1; /* FlexCAN A stop request. When asserted, a stop request is sent to the FlexCAN A */ 00945 vuint32_t:1; /* Reserved */ 00946 vuint32_t SPICSTP:1; /* DSPI C stop request. When asserted, a stop request is sent to the DSPI C. */ 00947 vuint32_t SPIBSTP:1; /* DSPI B stop request. When asserted, a stop request is sent to the DSPI B. */ 00948 vuint32_t:7; /* Reserved */ 00949 vuint32_t SCIBSTP:1; /* eSCI B stop request. When asserted, a stop request is sent to the eSCI B module. */ 00950 vuint32_t SCIASTP:1; /* eSCI A stop request. When asserted, a stop request is sent to the eSCIA module. */ 00951 } B; 00952 } HLT; /* Halt Register (HLT) (new in MPC563xM) <URM>SIU_HLT</URM> @baseaddress + 0x9A8 */ 00953 00954 union { 00955 vuint32_t R; 00956 struct { 00957 vuint32_t CPUACK:1; /* CPU stop acknowledge. When asserted, indicates that a stop acknowledge was */ 00958 vuint32_t:2; /* Reserved */ 00959 vuint32_t SWTACK:1; /* SWT stop acknowledge. When asserted, indicates that a stop acknowledge was */ 00960 vuint32_t:1; /* Reserved */ 00961 vuint32_t TPUACK:1; /* eTPU stop acknowledge. When asserted, indicates that a stop acknowledge was */ 00962 vuint32_t NPCACK:1; /* Nexus stop acknowledge. When asserted, indicates that a stop acknowledge was */ 00963 vuint32_t EBIACK:1; /* EBI stop acknowledge. When asserted, indicates that a stop acknowledge was */ 00964 vuint32_t ADCACK:1; /* eQADC stop acknowledge. When asserted, indicates that a stop acknowledge was */ 00965 vuint32_t:1; /* Reserved */ 00966 vuint32_t MIOSACK:1; /* eMIOS stop acknowledge. When asserted, indicates that a stop acknowledge was */ 00967 vuint32_t DFILACK:1; /* Decimation filter stop acknowledge. When asserted, indicates that a stop */ 00968 vuint32_t:1; /* Reserved */ 00969 vuint32_t PITACK:1; /* PIT stop acknowledge. When asserted, indicates that a stop acknowledge was */ 00970 vuint32_t:3; /* Reserved */ 00971 vuint32_t CNCACK:1; /* FlexCAN C stop acknowledge. When asserted, indicates that a stop acknowledge */ 00972 vuint32_t:1; /* Reserved */ 00973 vuint32_t CNAACK:1; /* FlexCAN A stop acknowledge. When asserted, indicates that a stop acknowledge */ 00974 vuint32_t:1; /* Reserved */ 00975 vuint32_t SPICACK:1; /* DSPI C stop acknowledge. When asserted, indicates that a stop acknowledge was */ 00976 vuint32_t SPIBACK:1; /* DSPI B stop acknowledge. When asserted, indicates that a stop acknowledge was */ 00977 vuint32_t:7; /* Reserved */ 00978 vuint32_t SCIBACK:1; /* eSCI B stop acknowledge */ 00979 vuint32_t SCIAACK:1; /* eSCI A stop acknowledge. */ 00980 } B; 00981 } HLTACK; /* Halt Acknowledge Register (HLTACK) (new in MPC563xM) <URM>SIU_HLTACK</URM> @baseaddress + 0x9ac */ 00982 00983 int32_t SIU_reserved3[21]; 00984 00985 }; /* end of SIU_tag */ 00986 /****************************************************************************/ 00987 /* MODULE : EMIOS */ 00988 /****************************************************************************/ 00989 struct EMIOS_tag { 00990 union { 00991 vuint32_t R; 00992 struct { 00993 vuint32_t DOZEEN:1; /* new in MPC563xM */ 00994 vuint32_t MDIS:1; 00995 vuint32_t FRZ:1; 00996 vuint32_t GTBE:1; 00997 vuint32_t ETB:1; 00998 vuint32_t GPREN:1; 00999 vuint32_t:6; 01000 vuint32_t SRV:4; 01001 vuint32_t GPRE:8; 01002 vuint32_t:8; 01003 } B; 01004 } MCR; /* Module Configuration Register <URM>EMIOSMCR</URM> */ 01005 01006 union { 01007 vuint32_t R; 01008 struct { 01009 vuint32_t:8; 01010 vuint32_t F23:1; 01011 vuint32_t F22:1; 01012 vuint32_t F21:1; 01013 vuint32_t F20:1; 01014 vuint32_t F19:1; 01015 vuint32_t F18:1; 01016 vuint32_t F17:1; 01017 vuint32_t F16:1; 01018 vuint32_t F15:1; 01019 vuint32_t F14:1; 01020 vuint32_t F13:1; 01021 vuint32_t F12:1; 01022 vuint32_t F11:1; 01023 vuint32_t F10:1; 01024 vuint32_t F9:1; 01025 vuint32_t F8:1; 01026 vuint32_t F7:1; 01027 vuint32_t F6:1; 01028 vuint32_t F5:1; 01029 vuint32_t F4:1; 01030 vuint32_t F3:1; 01031 vuint32_t F2:1; 01032 vuint32_t F1:1; 01033 vuint32_t F0:1; 01034 } B; 01035 } GFR; /* Global FLAG Register <URM>EMIOSGFLAG</URM> */ 01036 01037 union { 01038 vuint32_t R; 01039 struct { 01040 vuint32_t:8; 01041 vuint32_t OU23:1; 01042 vuint32_t OU22:1; 01043 vuint32_t OU21:1; 01044 vuint32_t OU20:1; 01045 vuint32_t OU19:1; 01046 vuint32_t OU18:1; 01047 vuint32_t OU17:1; 01048 vuint32_t OU16:1; 01049 vuint32_t OU15:1; 01050 vuint32_t OU14:1; 01051 vuint32_t OU13:1; 01052 vuint32_t OU12:1; 01053 vuint32_t OU11:1; 01054 vuint32_t OU10:1; 01055 vuint32_t OU9:1; 01056 vuint32_t OU8:1; 01057 vuint32_t OU7:1; 01058 vuint32_t OU6:1; 01059 vuint32_t OU5:1; 01060 vuint32_t OU4:1; 01061 vuint32_t OU3:1; 01062 vuint32_t OU2:1; 01063 vuint32_t OU1:1; 01064 vuint32_t OU0:1; 01065 } B; 01066 } OUDR; /* Output Update Disable Register <URM>EMIOSOUDIS</URM> */ 01067 01068 union { 01069 vuint32_t R; 01070 struct { 01071 vuint32_t:8; /* */ 01072 vuint32_t CHDIS23:1; /* Enable Channel [n] bit */ 01073 vuint32_t CHDIS22:1; /* Enable Channel [n] bit */ 01074 vuint32_t CHDIS21:1; /* Enable Channel [n] bit */ 01075 vuint32_t CHDIS20:1; /* Enable Channel [n] bit */ 01076 vuint32_t CHDIS19:1; /* Enable Channel [n] bit */ 01077 vuint32_t CHDIS18:1; /* Enable Channel [n] bit */ 01078 vuint32_t CHDIS17:1; /* Enable Channel [n] bit */ 01079 vuint32_t CHDIS16:1; /* Enable Channel [n] bit */ 01080 vuint32_t CHDIS15:1; /* Enable Channel [n] bit */ 01081 vuint32_t CHDIS14:1; /* Enable Channel [n] bit */ 01082 vuint32_t CHDIS13:1; /* Enable Channel [n] bit */ 01083 vuint32_t CHDIS12:1; /* Enable Channel [n] bit */ 01084 vuint32_t CHDIS11:1; /* Enable Channel [n] bit */ 01085 vuint32_t CHDIS10:1; /* Enable Channel [n] bit */ 01086 vuint32_t CHDIS9:1; /* Enable Channel [n] bit */ 01087 vuint32_t CHDIS8:1; /* Enable Channel [n] bit */ 01088 vuint32_t CHDIS7:1; /* Enable Channel [n] bit */ 01089 vuint32_t CHDIS6:1; /* Enable Channel [n] bit */ 01090 vuint32_t CHDIS5:1; /* Enable Channel [n] bit */ 01091 vuint32_t CHDIS4:1; /* Enable Channel [n] bit */ 01092 vuint32_t CHDIS3:1; /* Enable Channel [n] bit */ 01093 vuint32_t CHDIS2:1; /* Enable Channel [n] bit */ 01094 vuint32_t CHDIS1:1; /* Enable Channel [n] bit */ 01095 vuint32_t CHDIS0:1; /* Enable Channel [n] bit */ 01096 } B; 01097 } UCDIS; /* Disable Channel (EMIOSUCDIS) <URM>EMIOSUCDIS</URM> (new in MPC563xM) @baseaddress + 0x0C */ 01098 01099 int32_t EMIOS_reserverd_30[4]; 01100 01101 struct { 01102 union { 01103 vuint32_t R; /* Channel A Data Register */ 01104 } CADR; /* <URM>EMIOSA</URM> */ 01105 01106 union { 01107 vuint32_t R; /* Channel B Data Register */ 01108 } CBDR; /* <URM>EMIOSB</URM> */ 01109 01110 union { 01111 vuint32_t R; /* Channel Counter Register */ 01112 } CCNTR; /* <URM>EMIOSCNT</URM> */ 01113 01114 union { 01115 vuint32_t R; 01116 struct { 01117 vuint32_t FREN:1; 01118 vuint32_t ODIS:1; 01119 vuint32_t ODISSL:2; 01120 vuint32_t UCPRE:2; 01121 vuint32_t UCPREN:1; 01122 vuint32_t DMA:1; 01123 vuint32_t:1; 01124 vuint32_t IF:4; 01125 vuint32_t FCK:1; 01126 vuint32_t FEN:1; 01127 vuint32_t:3; 01128 vuint32_t FORCMA:1; 01129 vuint32_t FORCMB:1; 01130 vuint32_t:1; 01131 vuint32_t BSL:2; 01132 vuint32_t EDSEL:1; 01133 vuint32_t EDPOL:1; 01134 vuint32_t MODE:7; 01135 } B; 01136 } CCR; /* Channel Control Register <URM>EMIOSC</URM> */ 01137 01138 union { 01139 vuint32_t R; 01140 struct { 01141 vuint32_t OVR:1; 01142 vuint32_t:15; 01143 vuint32_t OVFL:1; 01144 vuint32_t:12; 01145 vuint32_t UCIN:1; 01146 vuint32_t UCOUT:1; 01147 vuint32_t FLAG:1; 01148 } B; 01149 } CSR; /* Channel Status Register <URM>EMIOSS</URM> */ 01150 01151 union { 01152 vuint32_t R; /* Alternate Channel A Data Register */ 01153 } ALTA; /* new in MPC563xM <URM>EMIOSALTA</URM> */ 01154 01155 uint32_t emios_channel_reserved[2]; 01156 01157 } CH[24]; 01158 01159 }; /* end of EMIOS_tag */ 01160 /****************************************************************************/ 01161 /* MODULE : ETPU */ 01162 /****************************************************************************/ 01163 struct ETPU_tag { /* offset 0x0000 */ 01164 union { /* eTPU module configuration register@baseaddress + 0x00 */ 01165 vuint32_t R; 01166 struct { 01167 vuint32_t GEC:1; /* Global Exception Clear */ 01168 vuint32_t SDMERR:1; /* */ 01169 vuint32_t WDTOA:1; /* */ 01170 vuint32_t WDTOB:1; /* */ 01171 vuint32_t MGE1:1; /* <URM>MGEA</URM> */ 01172 vuint32_t MGE2:1; /* <URM>MGEB</URM> */ 01173 vuint32_t ILF1:1; /* Invalid instruction flag eTPU A. <URM>ILFFA</URM> */ 01174 vuint32_t ILF2:1; /* Invalid instruction flag eTPU B. <URM>ILFFB</URM> */ 01175 vuint32_t SCMERR:1; /* . */ 01176 vuint32_t:2; /* */ 01177 vuint32_t SCMSIZE:5; /* Shared Code Memory size */ 01178 vuint32_t:4; /* */ 01179 vuint32_t SCMMISC:1; /* SCM MISC Flag */ 01180 vuint32_t SCMMISF:1; /* SCM MISC Flag */ 01181 vuint32_t SCMMISEN:1; /* SCM MISC Enable */ 01182 vuint32_t:2; /* */ 01183 vuint32_t VIS:1; /* SCM Visability */ 01184 vuint32_t:5; /* */ 01185 vuint32_t GTBE:1; /* Global Time Base Enable */ 01186 } B; 01187 } MCR; /* <URM>ETPU_MCR</URM> */ 01188 01189 /* offset 0x0004 */ 01190 union { /* eTPU coherent dual-parameter controller register@baseaddress + 0x04 */ 01191 vuint32_t R; 01192 struct { 01193 vuint32_t STS:1; /* Start Status bit */ 01194 vuint32_t CTBASE:5; /* Channel Transfer Base */ 01195 vuint32_t PBASE:10; /* Parameter Buffer Base Address <URM>PBBASE</URM> */ 01196 vuint32_t PWIDTH:1; /* Parameter Width */ 01197 vuint32_t PARAM0:7; /* Channel Parameter 0 <URM>PARM0</URM> */ 01198 vuint32_t WR:1; /* */ 01199 vuint32_t PARAM1:7; /* Channel Parameter 1 <URM>PARM1</URM> */ 01200 } B; 01201 } CDCR; /*<URM>ETPU_CDCR</URM> */ 01202 01203 vuint32_t ETPU_reserved_0; 01204 01205 /* offset 0x000C */ 01206 union { /* eTPU MISC Compare Register@baseaddress + 0x0c */ 01207 vuint32_t R; 01208 struct { 01209 vuint32_t ETPUMISCCMP:32; /* Expected multiple input signature calculator compare register value. <URM>EMISCCMP</URM> */ 01210 } B; 01211 } MISCCMPR /*<URM>ETPU_MISCCMPR</URM> */ ; 01212 01213 /* offset 0x0010 */ 01214 union { /* eTPU SCM Off-Range Data Register@baseaddress + 0x10 */ 01215 vuint32_t R; 01216 struct { 01217 vuint32_t ETPUSCMOFFDATA:32; /* SCM Off-range read data value. */ 01218 } B; 01219 } SCMOFFDATAR; /*<URM>ETPU_SCMOFFDATAR</URM> */ 01220 01221 /* offset 0x0014 */ 01222 union { /* eTPU Engine Configuration Register (ETPUA_ECR)@baseaddress + 0x14 */ 01223 vuint32_t R; 01224 struct { 01225 vuint32_t FEND:1; /* Force END */ 01226 vuint32_t MDIS:1; /* Low power Stop */ 01227 vuint32_t:1; /* */ 01228 vuint32_t STF:1; /* Stop Flag */ 01229 vuint32_t:4; /* */ 01230 vuint32_t HLTF:1; /* Halt Mode Flag */ 01231 vuint32_t:3; /* */ 01232 vuint32_t FCSS:1; 01233 vuint32_t FPSCK:3; /* Filter Prescaler Clock Control */ 01234 vuint32_t CDFC:2; /* */ 01235 vuint32_t:1; /* */ 01236 vuint32_t ERBA:5; /* */ 01237 vuint32_t SPPDIS:1; /* */ 01238 vuint32_t:2; /* */ 01239 vuint32_t ETB:5; /* Entry Table Base */ 01240 } B; 01241 } ECR_A; /*<URM>ETPU_ECR</URM> */ 01242 01243 vuint32_t ETPU_reserved_1[2]; 01244 01245 /* offset 0x0020 */ 01246 union { /* eTPU Time Base Configuration Register (ETPU_TBCR)@baseaddress + 0x20 */ 01247 vuint32_t R; 01248 struct { 01249 vuint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */ 01250 vuint32_t TCRCF:2; /* TCRCLK Signal Filter Control */ 01251 vuint32_t AM:2; /* Angle Mode */ 01252 vuint32_t:3; /* */ 01253 vuint32_t TCR2P:6; /* TCR2 Prescaler Control */ 01254 vuint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */ 01255 vuint32_t TCR1CS:1; /* */ 01256 vuint32_t:5; /* */ 01257 vuint32_t TCR1P:8; /* TCR1 Prescaler Control */ 01258 } B; 01259 } TBCR_A; /*<URM>ETPU_TBCR</URM> */ 01260 01261 /* offset 0x0024 */ 01262 union { /* eTPU Time Base 1 (TCR1) Visibility Register (ETPU_TB1R)@baseaddress + 0x24 */ 01263 vuint32_t R; 01264 struct { 01265 vuint32_t:8; /* */ 01266 vuint32_t TCR1:24; /* TCR1 value. Used on matches and captures. For more information, see the eTPU reference manual. */ 01267 } B; 01268 } TB1R_A; /*<URM>ETPU_TB1R</URM> */ 01269 01270 /* offset 0x0028 */ 01271 union { /* eTPU Time Base 2 (TCR2) Visibility Register (ETPU_TB2R)@baseaddress + 0x28 */ 01272 vuint32_t R; 01273 struct { 01274 vuint32_t:8; /* */ 01275 vuint32_t TCR2:24; /* TCR2 value. Used on matches and captures. For information on TCR2, see the eTPU reference manual. */ 01276 } B; 01277 } TB2R_A; /*<URM>ETPU_TB2R</URM> */ 01278 01279 /* offset 0x002C */ 01280 union { /* STAC Bus Configuration Register (ETPU_STACCR)@baseaddress + 0x2c */ 01281 vuint32_t R; 01282 struct { 01283 vuint32_t REN1:1; /* Resource Enable TCR1 */ 01284 vuint32_t RSC1:1; /* Resource Control TCR1 */ 01285 vuint32_t:2; /* */ 01286 vuint32_t SERVER_ID1:4; /* */ 01287 vuint32_t:4; /* */ 01288 vuint32_t SRV1:4; /* Resource Server Slot */ 01289 vuint32_t REN2:1; /* Resource Enable TCR2 */ 01290 vuint32_t RSC2:1; /* Resource Control TCR2 */ 01291 vuint32_t:2; /* */ 01292 vuint32_t SERVER_ID2:4; /* */ 01293 vuint32_t:4; /* */ 01294 vuint32_t SRV2:4; /* Resource Server Slot */ 01295 } B; 01296 } REDCR_A; /*<URM>ETPU_REDCR</URM> */ 01297 01298 vuint32_t ETPU_reserved_2[12]; 01299 01300 /* offset 0x0060 */ 01301 union { /* ETPU1 WDTR Register */ 01302 vuint32_t R; 01303 struct { 01304 vuint32_t WDM:2; 01305 vuint32_t:14; 01306 vuint32_t WDCNT:16; 01307 } B; 01308 } WDTR_A; 01309 01310 vuint32_t ETPU1_reserved_3; 01311 01312 /* offset 0x0068 */ 01313 union { /* ETPU1 IDLE Register */ 01314 vuint32_t R; 01315 struct { 01316 vuint32_t IDLE_CNT:31; 01317 vuint32_t ICLR:1; 01318 } B; 01319 } IDLE_A; 01320 01321 vuint32_t ETPU_reserved_4[101]; 01322 01323 /* offset 0x0200 */ 01324 union { /* eTPU Channel Interrupt Status Register (ETPU_CISR)@baseaddress + 0x200 */ 01325 vuint32_t R; 01326 struct { 01327 vuint32_t CIS31:1; /* Channel 31 Interrut Status */ 01328 vuint32_t CIS30:1; /* Channel 30 Interrut Status */ 01329 vuint32_t CIS29:1; /* Channel 29 Interrut Status */ 01330 vuint32_t CIS28:1; /* Channel 28 Interrut Status */ 01331 vuint32_t CIS27:1; /* Channel 27 Interrut Status */ 01332 vuint32_t CIS26:1; /* Channel 26 Interrut Status */ 01333 vuint32_t CIS25:1; /* Channel 25 Interrut Status */ 01334 vuint32_t CIS24:1; /* Channel 24 Interrut Status */ 01335 vuint32_t CIS23:1; /* Channel 23 Interrut Status */ 01336 vuint32_t CIS22:1; /* Channel 22 Interrut Status */ 01337 vuint32_t CIS21:1; /* Channel 21 Interrut Status */ 01338 vuint32_t CIS20:1; /* Channel 20 Interrut Status */ 01339 vuint32_t CIS19:1; /* Channel 19 Interrut Status */ 01340 vuint32_t CIS18:1; /* Channel 18 Interrut Status */ 01341 vuint32_t CIS17:1; /* Channel 17 Interrut Status */ 01342 vuint32_t CIS16:1; /* Channel 16 Interrut Status */ 01343 vuint32_t CIS15:1; /* Channel 15 Interrut Status */ 01344 vuint32_t CIS14:1; /* Channel 14 Interrut Status */ 01345 vuint32_t CIS13:1; /* Channel 13 Interrut Status */ 01346 vuint32_t CIS12:1; /* Channel 12 Interrut Status */ 01347 vuint32_t CIS11:1; /* Channel 11 Interrut Status */ 01348 vuint32_t CIS10:1; /* Channel 10 Interrut Status */ 01349 vuint32_t CIS9:1; /* Channel 9 Interrut Status */ 01350 vuint32_t CIS8:1; /* Channel 8 Interrut Status */ 01351 vuint32_t CIS7:1; /* Channel 7 Interrut Status */ 01352 vuint32_t CIS6:1; /* Channel 6 Interrut Status */ 01353 vuint32_t CIS5:1; /* Channel 5 Interrut Status */ 01354 vuint32_t CIS4:1; /* Channel 4 Interrut Status */ 01355 vuint32_t CIS3:1; /* Channel 3 Interrut Status */ 01356 vuint32_t CIS2:1; /* Channel 2 Interrut Status */ 01357 vuint32_t CIS1:1; /* Channel 1 Interrut Status */ 01358 vuint32_t CIS0:1; /* Channel 0 Interrut Status */ 01359 } B; 01360 } CISR_A; /* <URM>ETPU_CISR</URM> */ 01361 01362 int32_t ETPU_reserved_5[3]; 01363 01364 /* offset 0x0210 */ 01365 union { /* @baseaddress + 0x210 */ 01366 vuint32_t R; 01367 struct { 01368 vuint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */ 01369 vuint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */ 01370 vuint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */ 01371 vuint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */ 01372 vuint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */ 01373 vuint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */ 01374 vuint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */ 01375 vuint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */ 01376 vuint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */ 01377 vuint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */ 01378 vuint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */ 01379 vuint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */ 01380 vuint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */ 01381 vuint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */ 01382 vuint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */ 01383 vuint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */ 01384 vuint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */ 01385 vuint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */ 01386 vuint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */ 01387 vuint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */ 01388 vuint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */ 01389 vuint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */ 01390 vuint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */ 01391 vuint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */ 01392 vuint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */ 01393 vuint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */ 01394 vuint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */ 01395 vuint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */ 01396 vuint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */ 01397 vuint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */ 01398 vuint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */ 01399 vuint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */ 01400 } B; 01401 } CDTRSR_A; /* <URM>ETPU_CDTRSR</URM> */ 01402 01403 int32_t ETPU_reserved_6[3]; 01404 01405 /* offset 0x0220 */ 01406 union { /* eTPU Channel Interrupt Overflow Status Register (ETPU_CIOSR)@baseaddress + 0x220 */ 01407 vuint32_t R; 01408 struct { 01409 vuint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */ 01410 vuint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */ 01411 vuint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */ 01412 vuint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */ 01413 vuint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */ 01414 vuint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */ 01415 vuint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */ 01416 vuint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */ 01417 vuint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */ 01418 vuint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */ 01419 vuint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */ 01420 vuint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */ 01421 vuint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */ 01422 vuint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */ 01423 vuint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */ 01424 vuint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */ 01425 vuint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */ 01426 vuint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */ 01427 vuint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */ 01428 vuint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */ 01429 vuint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */ 01430 vuint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */ 01431 vuint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */ 01432 vuint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */ 01433 vuint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */ 01434 vuint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */ 01435 vuint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */ 01436 vuint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */ 01437 vuint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */ 01438 vuint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */ 01439 vuint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */ 01440 vuint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */ 01441 } B; 01442 } CIOSR_A; /* <URM>ETPU_CIOSR</URM> */ 01443 01444 int32_t ETPU_reserved_7[3]; 01445 01446 /* offset 0x0230 */ 01447 union { /* eTPU Channel Data Transfer Request Overflow Status Register@baseaddress + 0x230 */ 01448 vuint32_t R; 01449 struct { 01450 vuint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */ 01451 vuint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */ 01452 vuint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */ 01453 vuint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */ 01454 vuint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */ 01455 vuint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */ 01456 vuint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */ 01457 vuint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */ 01458 vuint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */ 01459 vuint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */ 01460 vuint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */ 01461 vuint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */ 01462 vuint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */ 01463 vuint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */ 01464 vuint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */ 01465 vuint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */ 01466 vuint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */ 01467 vuint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */ 01468 vuint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */ 01469 vuint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */ 01470 vuint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */ 01471 vuint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */ 01472 vuint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */ 01473 vuint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */ 01474 vuint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */ 01475 vuint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */ 01476 vuint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */ 01477 vuint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */ 01478 vuint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */ 01479 vuint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */ 01480 vuint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */ 01481 vuint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */ 01482 } B; 01483 } CDTROSR_A; /* <URM>ETPU_CDTROSR</URM> */ 01484 01485 int32_t ETPU_reserved_8[3]; 01486 01487 /* offset 0x0240 */ 01488 union { /* eTPU Channel Interrupt Enable Register (ETPU_CIER)@baseaddress + 0x240 */ 01489 vuint32_t R; 01490 struct { 01491 vuint32_t CIE31:1; /* Channel 31 Interruput Enable */ 01492 vuint32_t CIE30:1; /* Channel 30 Interruput Enable */ 01493 vuint32_t CIE29:1; /* Channel 29 Interruput Enable */ 01494 vuint32_t CIE28:1; /* Channel 28 Interruput Enable */ 01495 vuint32_t CIE27:1; /* Channel 27 Interruput Enable */ 01496 vuint32_t CIE26:1; /* Channel 26 Interruput Enable */ 01497 vuint32_t CIE25:1; /* Channel 25 Interruput Enable */ 01498 vuint32_t CIE24:1; /* Channel 24 Interruput Enable */ 01499 vuint32_t CIE23:1; /* Channel 23 Interruput Enable */ 01500 vuint32_t CIE22:1; /* Channel 22 Interruput Enable */ 01501 vuint32_t CIE21:1; /* Channel 21 Interruput Enable */ 01502 vuint32_t CIE20:1; /* Channel 20 Interruput Enable */ 01503 vuint32_t CIE19:1; /* Channel 19 Interruput Enable */ 01504 vuint32_t CIE18:1; /* Channel 18 Interruput Enable */ 01505 vuint32_t CIE17:1; /* Channel 17 Interruput Enable */ 01506 vuint32_t CIE16:1; /* Channel 16 Interruput Enable */ 01507 vuint32_t CIE15:1; /* Channel 15 Interruput Enable */ 01508 vuint32_t CIE14:1; /* Channel 14 Interruput Enable */ 01509 vuint32_t CIE13:1; /* Channel 13 Interruput Enable */ 01510 vuint32_t CIE12:1; /* Channel 12 Interruput Enable */ 01511 vuint32_t CIE11:1; /* Channel 11 Interruput Enable */ 01512 vuint32_t CIE10:1; /* Channel 10 Interruput Enable */ 01513 vuint32_t CIE9:1; /* Channel 9 Interruput Enable */ 01514 vuint32_t CIE8:1; /* Channel 8 Interruput Enable */ 01515 vuint32_t CIE7:1; /* Channel 7 Interruput Enable */ 01516 vuint32_t CIE6:1; /* Channel 6 Interruput Enable */ 01517 vuint32_t CIE5:1; /* Channel 5 Interruput Enable */ 01518 vuint32_t CIE4:1; /* Channel 4 Interruput Enable */ 01519 vuint32_t CIE3:1; /* Channel 3 Interruput Enable */ 01520 vuint32_t CIE2:1; /* Channel 2 Interruput Enable */ 01521 vuint32_t CIE1:1; /* Channel 1 Interruput Enable */ 01522 vuint32_t CIE0:1; /* Channel 0 Interruput Enable */ 01523 } B; 01524 } CIER_A; /* <URM>ETPU_CIER</URM> */ 01525 01526 int32_t ETPU_reserved_9[3]; 01527 01528 /* offset 0x0250 */ 01529 union { /* eTPU Channel Data Transfer Request Enable Register (ETPU_CDTRER)@baseaddress + 0x250 */ 01530 vuint32_t R; 01531 struct { 01532 vuint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */ 01533 vuint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */ 01534 vuint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */ 01535 vuint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */ 01536 vuint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */ 01537 vuint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */ 01538 vuint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */ 01539 vuint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */ 01540 vuint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */ 01541 vuint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */ 01542 vuint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */ 01543 vuint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */ 01544 vuint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */ 01545 vuint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */ 01546 vuint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */ 01547 vuint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */ 01548 vuint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */ 01549 vuint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */ 01550 vuint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */ 01551 vuint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */ 01552 vuint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */ 01553 vuint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */ 01554 vuint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */ 01555 vuint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */ 01556 vuint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */ 01557 vuint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */ 01558 vuint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */ 01559 vuint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */ 01560 vuint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */ 01561 vuint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */ 01562 vuint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */ 01563 vuint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */ 01564 } B; 01565 } CDTRER_A; /* <URM>ETPU_CDTRER</URM> */ 01566 01567 int32_t ETPU_reserved_10[3]; 01568 01569 /* offset 0x0260 */ 01570 union { /* ETPUWDSR - eTPU Watchdog Status Register */ 01571 vuint32_t R; 01572 struct { 01573 vuint32_t WDS31:1; /* Channel 31 Data Transfer Request Enable */ 01574 vuint32_t WDS30:1; /* Channel 30 Data Transfer Request Enable */ 01575 vuint32_t WDS29:1; /* Channel 29 Data Transfer Request Enable */ 01576 vuint32_t WDS28:1; /* Channel 28 Data Transfer Request Enable */ 01577 vuint32_t WDS27:1; /* Channel 27 Data Transfer Request Enable */ 01578 vuint32_t WDS26:1; /* Channel 26 Data Transfer Request Enable */ 01579 vuint32_t WDS25:1; /* Channel 25 Data Transfer Request Enable */ 01580 vuint32_t WDS24:1; /* Channel 24 Data Transfer Request Enable */ 01581 vuint32_t WDS23:1; /* Channel 23 Data Transfer Request Enable */ 01582 vuint32_t WDS22:1; /* Channel 22 Data Transfer Request Enable */ 01583 vuint32_t WDS21:1; /* Channel 21 Data Transfer Request Enable */ 01584 vuint32_t WDS20:1; /* Channel 20 Data Transfer Request Enable */ 01585 vuint32_t WDS19:1; /* Channel 19 Data Transfer Request Enable */ 01586 vuint32_t WDS18:1; /* Channel 18 Data Transfer Request Enable */ 01587 vuint32_t WDS17:1; /* Channel 17 Data Transfer Request Enable */ 01588 vuint32_t WDS16:1; /* Channel 16 Data Transfer Request Enable */ 01589 vuint32_t WDS15:1; /* Channel 15 Data Transfer Request Enable */ 01590 vuint32_t WDS14:1; /* Channel 14 Data Transfer Request Enable */ 01591 vuint32_t WDS13:1; /* Channel 13 Data Transfer Request Enable */ 01592 vuint32_t WDS12:1; /* Channel 12 Data Transfer Request Enable */ 01593 vuint32_t WDS11:1; /* Channel 11 Data Transfer Request Enable */ 01594 vuint32_t WDS10:1; /* Channel 10 Data Transfer Request Enable */ 01595 vuint32_t WDS9:1; /* Channel 9 Data Transfer Request Enable */ 01596 vuint32_t WDS8:1; /* Channel 8 Data Transfer Request Enable */ 01597 vuint32_t WDS7:1; /* Channel 7 Data Transfer Request Enable */ 01598 vuint32_t WDS6:1; /* Channel 6 Data Transfer Request Enable */ 01599 vuint32_t WDS5:1; /* Channel 5 Data Transfer Request Enable */ 01600 vuint32_t WDS4:1; /* Channel 4 Data Transfer Request Enable */ 01601 vuint32_t WDS3:1; /* Channel 3 Data Transfer Request Enable */ 01602 vuint32_t WDS2:1; /* Channel 2 Data Transfer Request Enable */ 01603 vuint32_t WDS1:1; /* Channel 1 Data Transfer Request Enable */ 01604 vuint32_t WDS0:1; /* Channel 0 Data Transfer Request Enable */ 01605 } B; 01606 } WDSR_A; 01607 01608 int32_t ETPU_reserved_11[7]; 01609 01610 /* offset 0x0280 */ 01611 union { /* ETPUCPSSR - eTPU Channel Pending Service Status Register */ 01612 vuint32_t R; 01613 struct { 01614 vuint32_t SR31:1; /* Channel 31 Data Transfer Request Enable */ 01615 vuint32_t SR30:1; /* Channel 30 Data Transfer Request Enable */ 01616 vuint32_t SR29:1; /* Channel 29 Data Transfer Request Enable */ 01617 vuint32_t SR28:1; /* Channel 28 Data Transfer Request Enable */ 01618 vuint32_t SR27:1; /* Channel 27 Data Transfer Request Enable */ 01619 vuint32_t SR26:1; /* Channel 26 Data Transfer Request Enable */ 01620 vuint32_t SR25:1; /* Channel 25 Data Transfer Request Enable */ 01621 vuint32_t SR24:1; /* Channel 24 Data Transfer Request Enable */ 01622 vuint32_t SR23:1; /* Channel 23 Data Transfer Request Enable */ 01623 vuint32_t SR22:1; /* Channel 22 Data Transfer Request Enable */ 01624 vuint32_t SR21:1; /* Channel 21 Data Transfer Request Enable */ 01625 vuint32_t SR20:1; /* Channel 20 Data Transfer Request Enable */ 01626 vuint32_t SR19:1; /* Channel 19 Data Transfer Request Enable */ 01627 vuint32_t SR18:1; /* Channel 18 Data Transfer Request Enable */ 01628 vuint32_t SR17:1; /* Channel 17 Data Transfer Request Enable */ 01629 vuint32_t SR16:1; /* Channel 16 Data Transfer Request Enable */ 01630 vuint32_t SR15:1; /* Channel 15 Data Transfer Request Enable */ 01631 vuint32_t SR14:1; /* Channel 14 Data Transfer Request Enable */ 01632 vuint32_t SR13:1; /* Channel 13 Data Transfer Request Enable */ 01633 vuint32_t SR12:1; /* Channel 12 Data Transfer Request Enable */ 01634 vuint32_t SR11:1; /* Channel 11 Data Transfer Request Enable */ 01635 vuint32_t SR10:1; /* Channel 10 Data Transfer Request Enable */ 01636 vuint32_t SR9:1; /* Channel 9 Data Transfer Request Enable */ 01637 vuint32_t SR8:1; /* Channel 8 Data Transfer Request Enable */ 01638 vuint32_t SR7:1; /* Channel 7 Data Transfer Request Enable */ 01639 vuint32_t SR6:1; /* Channel 6 Data Transfer Request Enable */ 01640 vuint32_t SR5:1; /* Channel 5 Data Transfer Request Enable */ 01641 vuint32_t SR4:1; /* Channel 4 Data Transfer Request Enable */ 01642 vuint32_t SR3:1; /* Channel 3 Data Transfer Request Enable */ 01643 vuint32_t SR2:1; /* Channel 2 Data Transfer Request Enable */ 01644 vuint32_t SR1:1; /* Channel 1 Data Transfer Request Enable */ 01645 vuint32_t SR0:1; /* Channel 0 Data Transfer Request Enable */ 01646 } B; 01647 } CPSSR_A; /* <URM>ETPU_CPSSR</URM> */ 01648 01649 int32_t ETPU_reserved_12[3]; 01650 01651 /* offset 0x0290 */ 01652 union { /* ETPUCSSR - eTPU Channel Service Status Register */ 01653 vuint32_t R; 01654 struct { 01655 vuint32_t SS31:1; /* Channel 31 Data Transfer Request Enable */ 01656 vuint32_t SS30:1; /* Channel 30 Data Transfer Request Enable */ 01657 vuint32_t SS29:1; /* Channel 29 Data Transfer Request Enable */ 01658 vuint32_t SS28:1; /* Channel 28 Data Transfer Request Enable */ 01659 vuint32_t SS27:1; /* Channel 27 Data Transfer Request Enable */ 01660 vuint32_t SS26:1; /* Channel 26 Data Transfer Request Enable */ 01661 vuint32_t SS25:1; /* Channel 25 Data Transfer Request Enable */ 01662 vuint32_t SS24:1; /* Channel 24 Data Transfer Request Enable */ 01663 vuint32_t SS23:1; /* Channel 23 Data Transfer Request Enable */ 01664 vuint32_t SS22:1; /* Channel 22 Data Transfer Request Enable */ 01665 vuint32_t SS21:1; /* Channel 21 Data Transfer Request Enable */ 01666 vuint32_t SS20:1; /* Channel 20 Data Transfer Request Enable */ 01667 vuint32_t SS19:1; /* Channel 19 Data Transfer Request Enable */ 01668 vuint32_t SS18:1; /* Channel 18 Data Transfer Request Enable */ 01669 vuint32_t SS17:1; /* Channel 17 Data Transfer Request Enable */ 01670 vuint32_t SS16:1; /* Channel 16 Data Transfer Request Enable */ 01671 vuint32_t SS15:1; /* Channel 15 Data Transfer Request Enable */ 01672 vuint32_t SS14:1; /* Channel 14 Data Transfer Request Enable */ 01673 vuint32_t SS13:1; /* Channel 13 Data Transfer Request Enable */ 01674 vuint32_t SS12:1; /* Channel 12 Data Transfer Request Enable */ 01675 vuint32_t SS11:1; /* Channel 11 Data Transfer Request Enable */ 01676 vuint32_t SS10:1; /* Channel 10 Data Transfer Request Enable */ 01677 vuint32_t SS9:1; /* Channel 9 Data Transfer Request Enable */ 01678 vuint32_t SS8:1; /* Channel 8 Data Transfer Request Enable */ 01679 vuint32_t SS7:1; /* Channel 7 Data Transfer Request Enable */ 01680 vuint32_t SS6:1; /* Channel 6 Data Transfer Request Enable */ 01681 vuint32_t SS5:1; /* Channel 5 Data Transfer Request Enable */ 01682 vuint32_t SS4:1; /* Channel 4 Data Transfer Request Enable */ 01683 vuint32_t SS3:1; /* Channel 3 Data Transfer Request Enable */ 01684 vuint32_t SS2:1; /* Channel 2 Data Transfer Request Enable */ 01685 vuint32_t SS1:1; /* Channel 1 Data Transfer Request Enable */ 01686 vuint32_t SS0:1; /* Channel 0 Data Transfer Request Enable */ 01687 } B; 01688 } CSSR_A; /* <URM>ETPU_CSSR</URM> */ 01689 01690 int32_t ETPU_reserved_13[3]; 01691 int32_t ETPU_reserved_14[88]; 01692 01693 /***************************** Channels ********************************/ 01694 /* Note not all devices implement all channels or even 2 engines */ 01695 /* Each eTPU engine can implement 64 channels, however most devcies */ 01696 /* only implemnet 32 channels. The eTPU block can implement 1 or 2 */ 01697 /* engines per instantiation */ 01698 /***********************************************************************/ 01699 01700 struct { 01701 union { /* eTPU Channel n Configuration Register (ETPU_CnCR)@baseaddress + 0x400 */ 01702 vuint32_t R; 01703 struct { 01704 vuint32_t CIE:1; /* Channel Interruput Enable */ 01705 vuint32_t DTRE:1; /* Data Transfer Request Enable */ 01706 vuint32_t CPR:2; /* Channel Priority */ 01707 vuint32_t:2; /* */ 01708 vuint32_t ETPD:1; /* This bit selects which channel signal, input or output, is used in the entry point selection */ 01709 vuint32_t ETCS:1; /* Entry Table Condition Select */ 01710 vuint32_t:3; /* */ 01711 vuint32_t CFS:5; /* Channel Function Select */ 01712 vuint32_t ODIS:1; /* Output disable */ 01713 vuint32_t OPOL:1; /* output polarity */ 01714 vuint32_t:3; /* */ 01715 vuint32_t CPBA:11; /* Channel Parameter Base Address */ 01716 } B; 01717 } CR; /* <URM>ETPU_CnCR</URM> */ 01718 01719 union { /* eTPU Channel n Status Control Register (ETPU_CnSCR)@baseaddress + 0x404 */ 01720 vuint32_t R; 01721 struct { 01722 vuint32_t CIS:1; /* Channel Interruput Status */ 01723 vuint32_t CIOS:1; /* Channel Interruput Overflow Status */ 01724 vuint32_t:6; /* */ 01725 vuint32_t DTRS:1; /* Data Transfer Status */ 01726 vuint32_t DTROS:1; /* Data Transfer Overflow Status */ 01727 vuint32_t:6; /* */ 01728 vuint32_t IPS:1; /* Input Pin State */ 01729 vuint32_t OPS:1; /* Output Pin State */ 01730 vuint32_t OBE:1; /* Output Pin State */ 01731 vuint32_t:11; /* */ 01732 vuint32_t FM1:1; /* Function mode */ 01733 vuint32_t FM0:1; /* Function mode */ 01734 } B; 01735 } SCR; /* <URM>ETPU_CnSCR</URM> */ 01736 01737 union { /* eTPU channel host service request register (ETPU_CnHSRR)@baseaddress + 0x408 */ 01738 vuint32_t R; 01739 struct { 01740 vuint32_t:29; /* Host Service Request */ 01741 vuint32_t HSR:3; /* */ 01742 } B; 01743 } HSRR; /* <URM>ETPU_CnHSRR</URM> */ 01744 int32_t ETPU_reserved_18; 01745 01746 } CHAN[127]; 01747 /**** Note: Not all channels implemented on all devices. Up 64 can be implemented on */ 01748 }; /* end of ETPU_tag */ 01749 /****************************************************************************/ 01750 /* MODULE : XBAR */ 01751 /****************************************************************************/ 01752 struct XBAR_tag { 01753 union { 01754 vuint32_t R; 01755 struct { 01756 vuint32_t:4; /* Master 7 Priority - Not implemented */ 01757 vuint32_t:4; /* Master 6 Priority - Not implemented */ 01758 vuint32_t:4; /* Master 5 Priority - Not implemented */ 01759 vuint32_t:1; /* */ 01760 vuint32_t MSTR4:3; /* Master 4 Priority - Core load/store & Nexus port */ 01761 vuint32_t:4; /* Master 3 Priority - Not implemented */ 01762 vuint32_t:1; /* */ 01763 vuint32_t MSTR2:3; /* Master 2 Priority - Unused implemented master port */ 01764 vuint32_t:1; /* */ 01765 vuint32_t MSTR1:3; /* Master 1 Priority - eDMA */ 01766 vuint32_t:1; /* */ 01767 vuint32_t MSTR0:3; /* Master 0 Priority - e200z335 core Instruction */ 01768 } B; 01769 } MPR0; /* Master Priority Register for Slave port 0 @baseaddress + 0x00 - Flash */ 01770 01771 int32_t XBAR_reserverd_35[3]; 01772 01773 union { 01774 vuint32_t R; 01775 struct { 01776 vuint32_t RO:1; /* Read Only */ 01777 vuint32_t HLP:1; /* Halt Low Priority (new in MPC563xM) */ 01778 vuint32_t:6; /* Slave General Purpose Control Register Reserved */ 01779 vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ 01780 vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ 01781 vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ 01782 vuint32_t HPE4:1; /* High Priority Enable (new in MPC563xM) */ 01783 vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ 01784 vuint32_t HPE2:1; /* High Priority Enable (new in MPC563xM) */ 01785 vuint32_t HPE1:1; /* High Priority Enable (new in MPC563xM) */ 01786 vuint32_t HPE0:1; /* High Priority Enable (new in MPC563xM) */ 01787 vuint32_t:6; /* */ 01788 vuint32_t ARB:2; /* Arbitration Mode */ 01789 vuint32_t:2; /* */ 01790 vuint32_t PCTL:2; /* Parking Control */ 01791 vuint32_t:1; /* */ 01792 vuint32_t PARK:3; /* PARK */ 01793 } B; 01794 } SGPCR0; /* Slave General Purpose Control Register 0 @baseaddress + 0x10 */ 01795 01796 int32_t XBAR_reserverd_71[59]; 01797 01798 union { 01799 vuint32_t R; 01800 struct { 01801 vuint32_t:4; /* Master 7 Priority - Not implemented */ 01802 vuint32_t:4; /* Master 6 Priority - Not implemented */ 01803 vuint32_t:4; /* Master 5 Priority - Not implemented */ 01804 vuint32_t:1; /* */ 01805 vuint32_t MSTR4:3; /* Master 4 Priority - Core load/store & Nexus port */ 01806 vuint32_t:4; /* Master 3 Priority - Not implemented */ 01807 vuint32_t:1; /* */ 01808 vuint32_t MSTR2:3; /* Master 2 Priority - Unused implemented master port */ 01809 vuint32_t:1; /* */ 01810 vuint32_t MSTR1:3; /* Master 1 Priority - eDMA */ 01811 vuint32_t:1; /* */ 01812 vuint32_t MSTR0:3; /* Master 0 Priority - e200z335 core Instruction */ 01813 } B; 01814 } MPR1; /* Master Priority Register for Slave port 1 @baseaddress + 0x100 */ 01815 01816 int32_t XBAR_reserverd_105[3]; 01817 01818 union { 01819 vuint32_t R; 01820 struct { 01821 vuint32_t RO:1; /* Read Only */ 01822 vuint32_t HLP:1; /* Halt Low Priority (new in MPC563xM) */ 01823 vuint32_t:6; /* Slave General Purpose Control Register Reserved */ 01824 vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ 01825 vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ 01826 vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ 01827 vuint32_t HPE4:1; /* High Priority Enable (new in MPC563xM) */ 01828 vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ 01829 vuint32_t HPE2:1; /* High Priority Enable (new in MPC563xM) */ 01830 vuint32_t HPE1:1; /* High Priority Enable (new in MPC563xM) */ 01831 vuint32_t HPE0:1; /* High Priority Enable (new in MPC563xM) */ 01832 vuint32_t:6; /* */ 01833 vuint32_t ARB:2; /* Arbitration Mode */ 01834 vuint32_t:2; /* */ 01835 vuint32_t PCTL:2; /* Parking Control */ 01836 vuint32_t:1; /* */ 01837 vuint32_t PARK:3; /* PARK */ 01838 } B; 01839 } SGPCR1; /* Slave General Purpose Control Register 1 @baseaddress + 0x110 */ 01840 01841 int32_t XBAR_reserverd_141[59]; 01842 01843 /* Slave General Purpose Control Register 2 @baseaddress + 0x210 - not implemented */ 01844 01845 int32_t XBAR_reserverd_211[64]; 01846 01847 union { 01848 vuint32_t R; 01849 struct { 01850 vuint32_t:4; /* Master 7 Priority - Not implemented */ 01851 vuint32_t:4; /* Master 6 Priority - Not implemented */ 01852 vuint32_t:4; /* Master 5 Priority - Not implemented */ 01853 vuint32_t:1; /* */ 01854 vuint32_t MSTR4:3; /* Master 4 Priority - Core load/store & Nexus port */ 01855 vuint32_t:4; /* Master 3 Priority - Not implemented */ 01856 vuint32_t:1; /* */ 01857 vuint32_t MSTR2:3; /* Master 2 Priority - Unused implemented master port */ 01858 vuint32_t:1; /* */ 01859 vuint32_t MSTR1:3; /* Master 1 Priority - eDMA */ 01860 vuint32_t:1; /* */ 01861 vuint32_t MSTR0:3; /* Master 0 Priority - e200z335 core Instruction */ 01862 } B; 01863 } MPR3; /* Master Priority Register for Slave port 3 @baseaddress + 0x300 */ 01864 01865 int32_t XBAR_reserverd_245[3]; 01866 01867 union { 01868 vuint32_t R; 01869 struct { 01870 vuint32_t RO:1; /* Read Only */ 01871 vuint32_t HLP:1; /* Halt Low Priority (new in MPC563xM) */ 01872 vuint32_t:6; /* Slave General Purpose Control Register Reserved */ 01873 vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ 01874 vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ 01875 vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ 01876 vuint32_t HPE4:1; /* High Priority Enable (new in MPC563xM) */ 01877 vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ 01878 vuint32_t HPE2:1; /* High Priority Enable (new in MPC563xM) */ 01879 vuint32_t HPE1:1; /* High Priority Enable (new in MPC563xM) */ 01880 vuint32_t HPE0:1; /* High Priority Enable (new in MPC563xM) */ 01881 vuint32_t:6; /* */ 01882 vuint32_t ARB:2; /* Arbitration Mode */ 01883 vuint32_t:2; /* */ 01884 vuint32_t PCTL:2; /* Parking Control */ 01885 vuint32_t:1; /* */ 01886 vuint32_t PARK:3; /* PARK */ 01887 } B; 01888 } SGPCR3; /* Slave General Purpose Control Register 3 @baseaddress + 0x310 */ 01889 01890 int32_t XBAR_reserverd_281[59]; 01891 01892 /* Slave General Purpose Control Register 4 @baseaddress + 0x410 - not implemented */ 01893 01894 int32_t XBAR_reserverd_351[64]; 01895 01896 /* Slave XBAR Port 5 Not implemented @baseaddress + 0x510 */ 01897 01898 int32_t XBAR_reserverd_421[64]; 01899 01900 /* Slave Port 6 not implemented @baseaddress + 0x610 */ 01901 01902 int32_t XBAR_reserverd_491[64]; 01903 01904 union { 01905 vuint32_t R; 01906 struct { 01907 vuint32_t:4; /* Master 7 Priority - Not implemented */ 01908 vuint32_t:4; /* Master 6 Priority - Not implemented */ 01909 vuint32_t:4; /* Master 5 Priority - Not implemented */ 01910 vuint32_t:1; /* */ 01911 vuint32_t MSTR4:3; /* Master 4 Priority - Core load/store & Nexus port */ 01912 vuint32_t:4; /* Master 3 Priority - Not implemented */ 01913 vuint32_t:1; /* */ 01914 vuint32_t MSTR2:3; /* Master 2 Priority - Unused implemented master port */ 01915 vuint32_t:1; /* */ 01916 vuint32_t MSTR1:3; /* Master 1 Priority - eDMA */ 01917 vuint32_t:1; /* */ 01918 vuint32_t MSTR0:3; /* Master 0 Priority - e200z335 core Instruction */ 01919 } B; 01920 } MPR7; /* Master Priority Register for Slave port 7 @baseaddress + 0x700 */ 01921 01922 int32_t XBAR_reserverd_525[3]; 01923 01924 union { 01925 vuint32_t R; 01926 struct { 01927 vuint32_t RO:1; /* Read Only */ 01928 vuint32_t HLP:1; /* Halt Low Priority (new in MPC563xM) */ 01929 vuint32_t:6; /* Slave General Purpose Control Register Reserved */ 01930 vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ 01931 vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ 01932 vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ 01933 vuint32_t HPE4:1; /* High Priority Enable (new in MPC563xM) */ 01934 vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ 01935 vuint32_t HPE2:1; /* High Priority Enable (new in MPC563xM) */ 01936 vuint32_t HPE1:1; /* High Priority Enable (new in MPC563xM) */ 01937 vuint32_t HPE0:1; /* High Priority Enable (new in MPC563xM) */ 01938 vuint32_t:6; /* */ 01939 vuint32_t ARB:2; /* Arbitration Mode */ 01940 vuint32_t:2; /* */ 01941 vuint32_t PCTL:2; /* Parking Control */ 01942 vuint32_t:1; /* */ 01943 vuint32_t PARK:3; /* PARK */ 01944 } B; 01945 } SGPCR7; /* Slave General Purpose Control Register 7 @baseaddress + 0x710 */ 01946 01947 int32_t XBAR_reserverd_561[59]; 01948 01949 union { 01950 vuint32_t R; 01951 struct { 01952 vuint32_t:29; /* */ 01953 vuint32_t AULB:3; /* Arbitrate on Undefined Length Bursts */ 01954 } B; 01955 } MGPCR0; /* Master General Purpose Control Register 0 @baseaddress + 0x800 */ 01956 01957 int32_t XBAR_reserverd_564[63]; 01958 01959 union { 01960 vuint32_t R; 01961 struct { 01962 vuint32_t:29; /* */ 01963 vuint32_t AULB:3; /* Arbitrate on Undefined Length Bursts */ 01964 } B; 01965 } MGPCR1; /* Master General Purpose Control Register 1 @baseaddress + 0x900 */ 01966 01967 int32_t XBAR_reserverd_567[63]; 01968 01969 union { 01970 vuint32_t R; 01971 struct { 01972 vuint32_t:29; /* */ 01973 vuint32_t AULB:3; /* Arbitrate on Undefined Length Bursts */ 01974 } B; 01975 } MGPCR2; /* Master General Purpose Control Register 2 @baseaddress + 0xA00 */ 01976 01977 int32_t XBAR_reserverd_570[63]; 01978 01979 /* Master General Purpose Control Register 3 not implemented @baseaddress + 0xB00 */ 01980 01981 int32_t XBAR_reserverd_573[64]; 01982 01983 union { 01984 vuint32_t R; 01985 struct { 01986 vuint32_t:29; /* */ 01987 vuint32_t AULB:3; /* Arbitrate on Undefined Length Bursts */ 01988 } B; 01989 } MGPCR4; /* Master General Purpose Control Register 4 @baseaddress + 0xC00 */ 01990 01991 int32_t XBAR_reserverd_576[64]; 01992 01993 /* Master General Purpose Control Register 5 not implemented @baseaddress + 0xD00 */ 01994 01995 int32_t XBAR_reserverd_579[64]; 01996 01997 /* Master General Purpose Control Register 6 not implemented @baseaddress + 0xE00 */ 01998 01999 int32_t XBAR_reserverd_582[64]; 02000 02001 /* Master General Purpose Control Register 7 not implemented @baseaddress + 0xF00 */ 02002 02003 }; /* end of XBAR_tag */ 02004 /****************************************************************************/ 02005 /* MODULE : ECSM */ 02006 /****************************************************************************/ 02007 struct ECSM_tag { 02008 /* SWTCR, SWTSR and SWTIR don't exist in MPC563xM */ 02009 uint32_t ecsm_reserved1[16]; 02010 02011 uint8_t ecsm_reserved3[3]; /* base + 0x40 */ 02012 02013 union { 02014 vuint8_t R; 02015 struct { 02016 vuint8_t:6; 02017 vuint8_t ERNCR:1; /* <URM>EPRNCR</URM> */ 02018 vuint8_t EFNCR:1; /* <URM>EPFNCR</URM> */ 02019 } B; 02020 } ECR; /* ECC Configuration Register */ 02021 02022 uint8_t ecsm_reserved4[3]; /* base + 0x44 */ 02023 02024 union { 02025 vuint8_t R; 02026 struct { 02027 vuint8_t:6; 02028 vuint8_t RNCE:1; /* <URM>PRNCE</URM> */ 02029 vuint8_t FNCE:1; /* <URM>PFNCE</URM> */ 02030 } B; 02031 } ESR; /* ECC Status Register */ 02032 02033 /* EEGR don't exist in MPC563xM */ 02034 uint32_t ecsm_reserved4a[2]; 02035 02036 union { 02037 vuint32_t R; 02038 struct { 02039 vuint32_t FEAR:32; /* <URM>PFEAR</URM> */ 02040 } B; 02041 } FEAR; /* Flash ECC Address Register <URM>PFEAR</URM> - 0x50 */ 02042 02043 uint16_t ecsm_reserved4b; 02044 02045 union { 02046 vuint8_t R; 02047 struct { 02048 vuint8_t:4; 02049 vuint8_t FEMR:4; /* <URM>PFEMR</URM> */ 02050 } B; 02051 } FEMR; /* Flash ECC Master Register <URM>PFEMR</URM> */ 02052 02053 union { 02054 vuint8_t R; 02055 struct { 02056 vuint8_t WRITE:1; 02057 vuint8_t SIZE:3; 02058 vuint8_t PROT0:1; /* <URM>PROTECTION</URM> */ 02059 vuint8_t PROT1:1; /* <URM>PROTECTION</URM> */ 02060 vuint8_t PROT2:1; /* <URM>PROTECTION</URM> */ 02061 vuint8_t PROT3:1; /* <URM>PROTECTION</URM> */ 02062 } B; 02063 } FEAT; /* Flash ECC Attributes Register <URM>PFEAT</URM> */ 02064 02065 union { 02066 vuint32_t R; 02067 struct { 02068 vuint32_t FEDH:32; /* <URM>PFEDR</URM> */ 02069 } B; 02070 } FEDRH; /* Flash ECC Data High Register <URM>PFEDRH</URM> */ 02071 02072 union { 02073 vuint32_t R; 02074 struct { 02075 vuint32_t FEDL:32; /* <URM>PFEDR</URM> */ 02076 } B; 02077 } FEDRL; /* Flash ECC Data Low Register <URM>PFEDRL</URM> */ 02078 02079 union { 02080 vuint32_t R; 02081 struct { 02082 vuint32_t REAR:32; /* <URM>PREAR</URM> */ 02083 } B; 02084 } REAR; /* RAM ECC Address <URM>PREAR</URM> */ 02085 02086 uint8_t ecsm_reserved5; 02087 02088 union { 02089 vuint8_t R; 02090 struct { 02091 vuint8_t PRESR:8; 02092 } B; 02093 } PRESR; /* RAM ECC Syndrome (new in MPC563xM) */ 02094 02095 union { 02096 vuint8_t R; 02097 struct { 02098 vuint8_t:4; 02099 vuint8_t REMR:4; /* <URM>PREMR</URM> */ 02100 } B; 02101 } REMR; /* RAM ECC Master <URM>PREMR</URM> */ 02102 02103 union { 02104 vuint8_t R; 02105 struct { 02106 vuint8_t WRITE:1; 02107 vuint8_t SIZE:3; 02108 vuint8_t PROT0:1; /* <URM>PROTECTION</URM> */ 02109 vuint8_t PROT1:1; /* <URM>PROTECTION</URM> */ 02110 vuint8_t PROT2:1; /* <URM>PROTECTION</URM> */ 02111 vuint8_t PROT3:1; /* <URM>PROTECTION</URM> */ 02112 } B; 02113 } REAT; /* RAM ECC Attributes Register <URM>PREAT</URM> */ 02114 02115 union { 02116 vuint32_t R; 02117 struct { 02118 vuint32_t REDH:32; /* <URM>PREDR</URM> */ 02119 } B; 02120 } REDRH; /* RAM ECC Data High Register <URM>PREDRH</URM> */ 02121 02122 union { 02123 vuint32_t R; 02124 struct { 02125 vuint32_t REDL:32; /* <URM>PREDR</URM> */ 02126 } B; 02127 } REDRL; /* RAMECC Data Low Register <URM>PREDRL</URM> */ 02128 02129 }; 02130 /****************************************************************************/ 02131 /* MODULE : EDMA */ 02132 /****************************************************************************/ 02133 struct EDMA_tag { 02134 union { 02135 vuint32_t R; 02136 struct { 02137 vuint32_t:14; /* Reserved */ 02138 vuint32_t CX:1; /* Cancel Transfer (new in MPC563xM) */ 02139 vuint32_t ECX:1; /* Error Cancel Transfer (new in MPC563xM) */ 02140 vuint32_t GRP3PRI:2; /* Channel Group 3 Priority (new in MPC563xM) */ 02141 vuint32_t GRP2PRI:2; /* Channel Group 2 Priority (new in MPC563xM) */ 02142 vuint32_t GRP1PRI:2; /* Channel Group 1 Priority */ 02143 vuint32_t GRP0PRI:2; /* Channel Group 0 Priority */ 02144 vuint32_t EMLM:1; /* Enable Minor Loop Mapping (new in MPC563xM) */ 02145 vuint32_t CLM:1; /* Continuous Link Mode (new in MPC563xM) */ 02146 vuint32_t HALT:1; /* Halt DMA Operations (new in MPC563xM) */ 02147 vuint32_t HOE:1; /* Halt On Error (new in MPC563xM) */ 02148 vuint32_t ERGA:1; /* Enable Round Robin Group Arbitration */ 02149 vuint32_t ERCA:1; /* Enable Round Robin Channel Arbitration */ 02150 vuint32_t EDBG:1; /* Enable Debug */ 02151 vuint32_t EBW:1; /* Enable Buffered Writes */ 02152 } B; 02153 } CR; /* DMA Control Register <URM>DMACR</URM> @baseaddress + 0x0 */ 02154 02155 union { 02156 vuint32_t R; 02157 struct { 02158 vuint32_t VLD:1; /* Logical OR of all DMAERRH */ 02159 02160 vuint32_t:14; /* Reserved */ 02161 vuint32_t ECX:1; /* (new in MPC563xM) */ 02162 vuint32_t GPE:1; /* Group Priority Error */ 02163 vuint32_t CPE:1; /* Channel Priority Error */ 02164 vuint32_t ERRCHN:6; /* ERRCHN[5:0] Error Channel Number or The channel number of the last recorded error */ 02165 vuint32_t SAE:1; /* Source Address Error 0 */ 02166 vuint32_t SOE:1; /* Source Offset Error */ 02167 vuint32_t DAE:1; /* Destination Address Error */ 02168 vuint32_t DOE:1; /* Destination Offset Error */ 02169 vuint32_t NCE:1; /* Nbytes/Citer Configuration Error */ 02170 vuint32_t SGE:1; /* Scatter/Gather Configuration Error */ 02171 vuint32_t SBE:1; /* Source Bus Error */ 02172 vuint32_t DBE:1; /* Destination Bus Error */ 02173 02174 } B; 02175 } ESR; /* <URM>DMAES</URM> Error Status Register */ 02176 02177 uint32_t edma_reserved_erqrh; 02178 02179 union { 02180 vuint32_t R; 02181 struct { 02182 vuint32_t ERQ31:1; 02183 vuint32_t ERQ30:1; 02184 vuint32_t ERQ29:1; 02185 vuint32_t ERQ28:1; 02186 vuint32_t ERQ27:1; 02187 vuint32_t ERQ26:1; 02188 vuint32_t ERQ25:1; 02189 vuint32_t ERQ24:1; 02190 vuint32_t ERQ23:1; 02191 vuint32_t ERQ22:1; 02192 vuint32_t ERQ21:1; 02193 vuint32_t ERQ20:1; 02194 vuint32_t ERQ19:1; 02195 vuint32_t ERQ18:1; 02196 vuint32_t ERQ17:1; 02197 vuint32_t ERQ16:1; 02198 vuint32_t ERQ15:1; 02199 vuint32_t ERQ14:1; 02200 vuint32_t ERQ13:1; 02201 vuint32_t ERQ12:1; 02202 vuint32_t ERQ11:1; 02203 vuint32_t ERQ10:1; 02204 vuint32_t ERQ09:1; 02205 vuint32_t ERQ08:1; 02206 vuint32_t ERQ07:1; 02207 vuint32_t ERQ06:1; 02208 vuint32_t ERQ05:1; 02209 vuint32_t ERQ04:1; 02210 vuint32_t ERQ03:1; 02211 vuint32_t ERQ02:1; 02212 vuint32_t ERQ01:1; 02213 vuint32_t ERQ00:1; 02214 } B; 02215 } ERQRL; /* <URM>DMAERQL</URM> ,DMA Enable Request Register Low */ 02216 02217 uint32_t edma_reserved_eeirh; 02218 02219 union { 02220 vuint32_t R; 02221 struct { 02222 vuint32_t EEI31:1; 02223 vuint32_t EEI30:1; 02224 vuint32_t EEI29:1; 02225 vuint32_t EEI28:1; 02226 vuint32_t EEI27:1; 02227 vuint32_t EEI26:1; 02228 vuint32_t EEI25:1; 02229 vuint32_t EEI24:1; 02230 vuint32_t EEI23:1; 02231 vuint32_t EEI22:1; 02232 vuint32_t EEI21:1; 02233 vuint32_t EEI20:1; 02234 vuint32_t EEI19:1; 02235 vuint32_t EEI18:1; 02236 vuint32_t EEI17:1; 02237 vuint32_t EEI16:1; 02238 vuint32_t EEI15:1; 02239 vuint32_t EEI14:1; 02240 vuint32_t EEI13:1; 02241 vuint32_t EEI12:1; 02242 vuint32_t EEI11:1; 02243 vuint32_t EEI10:1; 02244 vuint32_t EEI09:1; 02245 vuint32_t EEI08:1; 02246 vuint32_t EEI07:1; 02247 vuint32_t EEI06:1; 02248 vuint32_t EEI05:1; 02249 vuint32_t EEI04:1; 02250 vuint32_t EEI03:1; 02251 vuint32_t EEI02:1; 02252 vuint32_t EEI01:1; 02253 vuint32_t EEI00:1; 02254 } B; 02255 } EEIRL; /* <URM>DMAEEIL</URM> , DMA Enable Error Interrupt Register Low */ 02256 02257 union { 02258 vuint8_t R; 02259 vuint8_t B; /* <URM>NOP:1 SERQ:7</URM> */ 02260 } SERQR; /* <URM>DMASERQ</URM> , DMA Set Enable Request Register */ 02261 02262 union { 02263 vuint8_t R; 02264 vuint8_t B; /* <URM>NOP:1 CERQ:7</URM> */ 02265 } CERQR; /* <URM>DMACERQ</URM> , DMA Clear Enable Request Register */ 02266 02267 union { 02268 vuint8_t R; 02269 vuint8_t B; /* <URM>NOP:1 SEEI:7</URM> */ 02270 } SEEIR; /* <URM>DMASEEI</URM> , DMA Set Enable Error Interrupt Register */ 02271 02272 union { 02273 vuint8_t R; 02274 vuint8_t B; /* <URM>NOP:1 CEEI:7</URM> */ 02275 } CEEIR; /* <URM>DMACEEI</URM> , DMA Clear Enable Error Interrupt Register */ 02276 02277 union { 02278 vuint8_t R; 02279 vuint8_t B; /* <URM>NOP:1 CINT:7</URM> */ 02280 } CIRQR; /* <URM>DMACINT</URM> , DMA Clear Interrupt Request Register */ 02281 02282 union { 02283 vuint8_t R; 02284 vuint8_t B; /* <URM>NOP:1 CERR:7</URM> */ 02285 } CER; /* <URM>DMACERR</URM> , DMA Clear error Register */ 02286 02287 union { 02288 vuint8_t R; 02289 vuint8_t B; /* <URM>NOP:1 SSRT:7</URM> */ 02290 } SSBR; /* <URM>DMASSRT</URM> , Set Start Bit Register */ 02291 02292 union { 02293 vuint8_t R; 02294 vuint8_t B; /* <URM>NOP:1 CDNE:7</URM> */ 02295 } CDSBR; /* <URM>DMACDNE</URM> , Clear Done Status Bit Register */ 02296 02297 uint32_t edma_reserved_irqrh; 02298 02299 union { 02300 vuint32_t R; 02301 struct { 02302 vuint32_t INT31:1; 02303 vuint32_t INT30:1; 02304 vuint32_t INT29:1; 02305 vuint32_t INT28:1; 02306 vuint32_t INT27:1; 02307 vuint32_t INT26:1; 02308 vuint32_t INT25:1; 02309 vuint32_t INT24:1; 02310 vuint32_t INT23:1; 02311 vuint32_t INT22:1; 02312 vuint32_t INT21:1; 02313 vuint32_t INT20:1; 02314 vuint32_t INT19:1; 02315 vuint32_t INT18:1; 02316 vuint32_t INT17:1; 02317 vuint32_t INT16:1; 02318 vuint32_t INT15:1; 02319 vuint32_t INT14:1; 02320 vuint32_t INT13:1; 02321 vuint32_t INT12:1; 02322 vuint32_t INT11:1; 02323 vuint32_t INT10:1; 02324 vuint32_t INT09:1; 02325 vuint32_t INT08:1; 02326 vuint32_t INT07:1; 02327 vuint32_t INT06:1; 02328 vuint32_t INT05:1; 02329 vuint32_t INT04:1; 02330 vuint32_t INT03:1; 02331 vuint32_t INT02:1; 02332 vuint32_t INT01:1; 02333 vuint32_t INT00:1; 02334 } B; 02335 } IRQRL; /* <URM>DMAINTL</URM> , DMA Interrupt Request Low */ 02336 02337 uint32_t edma_reserved_erh; 02338 02339 union { 02340 vuint32_t R; 02341 struct { 02342 vuint32_t ERR31:1; 02343 vuint32_t ERR30:1; 02344 vuint32_t ERR29:1; 02345 vuint32_t ERR28:1; 02346 vuint32_t ERR27:1; 02347 vuint32_t ERR26:1; 02348 vuint32_t ERR25:1; 02349 vuint32_t ERR24:1; 02350 vuint32_t ERR23:1; 02351 vuint32_t ERR22:1; 02352 vuint32_t ERR21:1; 02353 vuint32_t ERR20:1; 02354 vuint32_t ERR19:1; 02355 vuint32_t ERR18:1; 02356 vuint32_t ERR17:1; 02357 vuint32_t ERR16:1; 02358 vuint32_t ERR15:1; 02359 vuint32_t ERR14:1; 02360 vuint32_t ERR13:1; 02361 vuint32_t ERR12:1; 02362 vuint32_t ERR11:1; 02363 vuint32_t ERR10:1; 02364 vuint32_t ERR09:1; 02365 vuint32_t ERR08:1; 02366 vuint32_t ERR07:1; 02367 vuint32_t ERR06:1; 02368 vuint32_t ERR05:1; 02369 vuint32_t ERR04:1; 02370 vuint32_t ERR03:1; 02371 vuint32_t ERR02:1; 02372 vuint32_t ERR01:1; 02373 vuint32_t ERR00:1; 02374 } B; 02375 } ERL; /* <URM>DMAERRL</URM> , DMA Error Low */ 02376 02377 int32_t edma_reserverd_hrsh[1]; 02378 02379 int32_t edma_reserverd_hrsl[1]; 02380 02381 int32_t edma_reserverd_gpor[1]; 02382 02383 int32_t EDMA_reserverd_223[49]; 02384 02385 union { 02386 vuint8_t R; 02387 struct { 02388 vuint8_t ECP:1; 02389 vuint8_t DPA:1; 02390 vuint8_t GRPPRI:2; 02391 vuint8_t CHPRI:4; 02392 } B; 02393 } CPR[64]; /* <URM>DCHPRI [32]</URM> , Channel n Priority */ 02394 02395 uint32_t edma_reserved2[944]; 02396 02397 /****************************************************************************/ 02398 /* DMA2 Transfer Control Descriptor */ 02399 /****************************************************************************/ 02400 02401 struct tcd_t { /*for "standard" format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=0 && EDMA.EMLM=0 ) */ 02402 vuint32_t SADDR; /* source address */ 02403 02404 vuint16_t SMOD:5; /* source address modulo */ 02405 vuint16_t SSIZE:3; /* source transfer size */ 02406 vuint16_t DMOD:5; /* destination address modulo */ 02407 vuint16_t DSIZE:3; /* destination transfer size */ 02408 vint16_t SOFF; /* signed source address offset */ 02409 vuint32_t NBYTES; /* inner (“minor”) byte count */ 02410 vint32_t SLAST; /* last destination address adjustment, or 02411 02412 scatter/gather address (if e_sg = 1) */ 02413 vuint32_t DADDR; /* destination address */ 02414 vuint16_t CITERE_LINK:1; 02415 vuint16_t CITER:15; 02416 vint16_t DOFF; /* signed destination address offset */ 02417 vint32_t DLAST_SGA; 02418 vuint16_t BITERE_LINK:1; /* beginning ("major") iteration count */ 02419 vuint16_t BITER:15; 02420 vuint16_t BWC:2; /* bandwidth control */ 02421 vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */ 02422 vuint16_t DONE:1; /* channel done */ 02423 vuint16_t ACTIVE:1; /* channel active */ 02424 vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */ 02425 vuint16_t E_SG:1; /* enable scatter/gather descriptor */ 02426 vuint16_t D_REQ:1; /* disable ipd_req when done */ 02427 vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */ 02428 vuint16_t INT_MAJ:1; /* interrupt on major loop completion */ 02429 vuint16_t START:1; /* explicit channel start */ 02430 } TCD[64]; /* <URM>TCD [32]</URM> , transfer_control_descriptor */ 02431 }; 02432 02433 struct EDMA_TCD_alt1_tag { /*for alternate format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=1 ) */ 02434 02435 struct tcd_alt1_t { 02436 vuint32_t SADDR; /* source address */ 02437 02438 vuint16_t SMOD:5; /* source address modulo */ 02439 vuint16_t SSIZE:3; /* source transfer size */ 02440 vuint16_t DMOD:5; /* destination address modulo */ 02441 vuint16_t DSIZE:3; /* destination transfer size */ 02442 vint16_t SOFF; /* signed source address offset */ 02443 vuint32_t NBYTES; /* inner (“minor”) byte count */ 02444 vint32_t SLAST; /* last destination address adjustment, or 02445 02446 scatter/gather address (if e_sg = 1) */ 02447 vuint32_t DADDR; /* destination address */ 02448 vuint16_t CITERE_LINK:1; 02449 vuint16_t CITERLINKCH:6; 02450 vuint16_t CITER:9; 02451 vint16_t DOFF; /* signed destination address offset */ 02452 vint32_t DLAST_SGA; 02453 vuint16_t BITERE_LINK:1; /* beginning (“major”) iteration count */ 02454 vuint16_t BITERLINKCH:6; 02455 vuint16_t BITER:9; 02456 vuint16_t BWC:2; /* bandwidth control */ 02457 vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */ 02458 vuint16_t DONE:1; /* channel done */ 02459 vuint16_t ACTIVE:1; /* channel active */ 02460 vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */ 02461 vuint16_t E_SG:1; /* enable scatter/gather descriptor */ 02462 vuint16_t D_REQ:1; /* disable ipd_req when done */ 02463 vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */ 02464 vuint16_t INT_MAJ:1; /* interrupt on major loop completion */ 02465 vuint16_t START:1; /* explicit channel start */ 02466 } TCD[64]; /* <URM>TCD [32]</URM> , transfer_control_descriptor */ 02467 }; 02468 02469 /****************************************************************************/ 02470 /* MODULE : INTC */ 02471 /****************************************************************************/ 02472 struct INTC_tag { 02473 union { 02474 vuint32_t R; 02475 struct { 02476 vuint32_t:18; /* Reserved */ 02477 vuint32_t VTES_PRC1:1; /* Vector Table Entry Size for PRC1 (new in MPC563xM) */ 02478 vuint32_t:4; /* Reserved */ 02479 vuint32_t HVEN_PRC1:1; /* Hardware Vector Enable for PRC1 (new in MPC563xM) */ 02480 vuint32_t:2; /* Reserved */ 02481 vuint32_t VTES:1; /* Vector Table Entry Size for PRC0 <URM>VTES_PRC0</URM> */ 02482 vuint32_t:4; /* Reserved */ 02483 vuint32_t HVEN:1; /* Hardware Vector Enable for PRC0 <URM>HVEN_PRC0</URM> */ 02484 } B; 02485 } MCR; /* INTC Module Configuration Register (MCR) <URM>INTC_BCR</URM> @baseaddress + 0x00 */ 02486 int32_t INTC_reserverd_10[1]; 02487 02488 union { 02489 vuint32_t R; 02490 struct { 02491 vuint32_t:28; /* Reserved */ 02492 vuint32_t PRI:4; /* Priority */ 02493 } B; 02494 } CPR; /* INTC Current Priority Register for Processor 0 (CPR) <URM>INTC_CPR_PRC0</URM> @baseaddress + 0x08 */ 02495 02496 int32_t INTC_reserved_1; /* CPR_PRC1 - INTC Current Priority Register for Processor 1 (CPR_PRC1) <URM>INTC_CPR_PRC1</URM> @baseaddress + 0x0c */ 02497 02498 union { 02499 vuint32_t R; 02500 struct { 02501 vuint32_t VTBA:21; /* Vector Table Base Address <URM>VTBA_PRC0</URM> */ 02502 vuint32_t INTVEC:9; /* Interrupt Vector <URM>INTVEC_PRC0</URM> */ 02503 vuint32_t:2; /* Reserved */ 02504 } B; 02505 } IACKR; /* INTC Interrupt Acknowledge Register for Processor 0 (IACKR) <URM>INTC_IACKR_PRC0</URM> @baseaddress + 0x10 */ 02506 02507 int32_t INTC_reserverd_2; /* IACKR_PRC1 - INTC Interrupt Acknowledge Register for Processor 1 (IACKR_PRC1) <URM>INTC_IACKR_PRC1</URM> @baseaddress + 0x14 */ 02508 02509 union { 02510 vuint32_t R; 02511 } EOIR; /* INTC End of Interrupt Register for Processor 0 (EOIR) <URM>INTC_EOIR_PRC0</URM> @baseaddress + 0x18 */ 02512 02513 int32_t INTC_reserverd_3; /* EOIR_PRC1 - INTC End of Interrupt Register for Processor 1 (EOIR_PRC1) <URM>INTC_EOIR_PRC1</URM> @baseaddress + 0x1C */ 02514 02515 union { 02516 vuint8_t R; 02517 struct { 02518 vuint8_t:6; /* Reserved */ 02519 vuint8_t SET:1; /* Set Flag bits */ 02520 vuint8_t CLR:1; /* Clear Flag bits */ 02521 } B; 02522 } SSCIR[8]; /* INTC Software Set/Clear Interrupt Registers (SSCIR) <URM>INTC_SSCIRn</URM> @baseaddress + 0x20 */ 02523 02524 int32_t INTC_reserverd_32[6]; 02525 02526 union { 02527 vuint8_t R; 02528 struct { 02529 vuint8_t PRC_SEL:2; /* Processor Select (new in MPC563xM) */ 02530 vuint8_t:2; /* Reserved */ 02531 vuint8_t PRI:4; /* Priority Select */ 02532 } B; 02533 } PSR[512]; /* INTC Priority Select Registers (PSR) <URM>INTC_PSR</URM> @baseaddress + 0x40 */ 02534 02535 }; /* end of INTC_tag */ 02536 /****************************************************************************/ 02537 /* MODULE : EQADC */ 02538 /****************************************************************************/ 02539 struct EQADC_tag { 02540 union { 02541 vuint32_t R; 02542 struct { 02543 vuint32_t:24; 02544 vuint32_t ICEA0:1; 02545 vuint32_t ICEA1:1; 02546 vuint32_t:1; 02547 vuint32_t ESSIE:2; 02548 vuint32_t:1; 02549 vuint32_t DBG:2; 02550 } B; 02551 } MCR; /* Module Configuration Register <URM>EQADC_MCR</URM> */ 02552 02553 int32_t EQADC_reserved00; 02554 02555 union { 02556 vuint32_t R; 02557 struct { 02558 vuint32_t:6; 02559 vuint32_t NMF:26; 02560 } B; 02561 } NMSFR; /* Null Message Send Format Register <URM>EQADC_NMSFR</URM> */ 02562 02563 union { 02564 vuint32_t R; 02565 struct { 02566 vuint32_t:28; 02567 vuint32_t DFL:4; 02568 } B; 02569 } ETDFR; /* External Trigger Digital Filter Register <URM>EQADC_ETDFR</URM> */ 02570 02571 union { 02572 vuint32_t R; 02573 struct { 02574 vuint32_t CFPUSH:32; /* <URM>CF_PUSH</URM> */ 02575 } B; 02576 } CFPR[6]; /* CFIFO Push Registers <URM>EQADC_CFPR</URM> */ 02577 02578 uint32_t eqadc_reserved1; 02579 02580 uint32_t eqadc_reserved2; 02581 02582 union { 02583 vuint32_t R; 02584 struct { 02585 vuint32_t:16; 02586 vuint32_t RFPOP:16; /* <URM>RF_POP</URM> */ 02587 } B; 02588 } RFPR[6]; /* Result FIFO Pop Registers <URM>EQADC_RFPR</URM> */ 02589 02590 uint32_t eqadc_reserved3; 02591 02592 uint32_t eqadc_reserved4; 02593 02594 union { 02595 vuint16_t R; 02596 struct { 02597 vuint16_t:3; 02598 vuint16_t CFEE0:1; 02599 vuint16_t STRME0:1; 02600 vuint16_t SSE:1; 02601 vuint16_t CFINV:1; 02602 vuint16_t:1; 02603 vuint16_t MODE:4; 02604 vuint16_t AMODE0:4; /* CFIFO0 only */ 02605 } B; 02606 } CFCR[6]; /* CFIFO Control Registers <URM>EQADC_CFCR</URM> */ 02607 02608 uint32_t eqadc_reserved5; 02609 02610 union { 02611 vuint16_t R; 02612 struct { 02613 vuint16_t NCIE:1; 02614 vuint16_t TORIE:1; 02615 vuint16_t PIE:1; 02616 vuint16_t EOQIE:1; 02617 vuint16_t CFUIE:1; 02618 vuint16_t:1; 02619 vuint16_t CFFE:1; 02620 vuint16_t CFFS:1; 02621 vuint16_t:4; 02622 vuint16_t RFOIE:1; 02623 vuint16_t:1; 02624 vuint16_t RFDE:1; 02625 vuint16_t RFDS:1; 02626 } B; 02627 } IDCR[6]; /* Interrupt and DMA Control Registers <URM>EQADC_IDCR</URM> */ 02628 02629 uint32_t eqadc_reserved6; 02630 02631 union { 02632 vuint32_t R; 02633 struct { 02634 vuint32_t NCF:1; 02635 vuint32_t TORF:1; 02636 vuint32_t PF:1; 02637 vuint32_t EOQF:1; 02638 vuint32_t CFUF:1; 02639 vuint32_t SSS:1; 02640 vuint32_t CFFF:1; 02641 vuint32_t:5; 02642 vuint32_t RFOF:1; 02643 vuint32_t:1; 02644 vuint32_t RFDF:1; 02645 vuint32_t:1; 02646 vuint32_t CFCTR:4; 02647 vuint32_t TNXTPTR:4; 02648 vuint32_t RFCTR:4; 02649 vuint32_t POPNXTPTR:4; 02650 } B; 02651 } FISR[6]; /* FIFO and Interrupt Status Registers <URM>EQADC_FISR</URM> */ 02652 02653 uint32_t eqadc_reserved7; 02654 02655 uint32_t eqadc_reserved8; 02656 02657 union { 02658 vuint16_t R; 02659 struct { 02660 vuint16_t:5; 02661 vuint16_t TCCF:11; /* <URM>TC_CF</URM> */ 02662 } B; 02663 } CFTCR[6]; /* CFIFO Transfer Counter Registers <URM>EQADC_CFTCR</URM> */ 02664 02665 uint32_t eqadc_reserved9; 02666 02667 union { 02668 vuint32_t R; 02669 struct { 02670 vuint32_t CFS0:2; /* <URM>CFS0_TCB0</URM> */ 02671 vuint32_t CFS1:2; /* <URM>CFS1_TCB0</URM> */ 02672 vuint32_t CFS2:2; /* <URM>CFS2_TCB0</URM> */ 02673 vuint32_t CFS3:2; /* <URM>CFS3_TCB0</URM> */ 02674 vuint32_t CFS4:2; /* <URM>CFS4_TCB0</URM> */ 02675 vuint32_t CFS5:2; /* <URM>CFS5_TCB0</URM> */ 02676 vuint32_t:5; 02677 vuint32_t LCFTCB0:4; 02678 vuint32_t TC_LCFTCB0:11; 02679 } B; 02680 } CFSSR0; /* CFIFO Status Register 0 <URM>EQADC_CFSSR0</URM> */ 02681 02682 union { 02683 vuint32_t R; 02684 struct { 02685 vuint32_t CFS0:2; /* <URM>CFS0_TCB1</URM> */ 02686 vuint32_t CFS1:2; /* <URM>CFS1_TCB1</URM> */ 02687 vuint32_t CFS2:2; /* <URM>CFS2_TCB1</URM> */ 02688 vuint32_t CFS3:2; /* <URM>CFS3_TCB1</URM> */ 02689 vuint32_t CFS4:2; /* <URM>CFS4_TCB1</URM> */ 02690 vuint32_t CFS5:2; /* <URM>CFS5_TCB1</URM> */ 02691 vuint32_t:5; 02692 vuint32_t LCFTCB1:4; 02693 vuint32_t TC_LCFTCB1:11; 02694 } B; 02695 } CFSSR1; /* CFIFO Status Register 1 <URM>EQADC_CFSSR1</URM> */ 02696 02697 union { 02698 vuint32_t R; 02699 struct { 02700 vuint32_t CFS0:2; /* <URM>CFS0_TSSI</URM> */ 02701 vuint32_t CFS1:2; /* <URM>CFS1_TSSI</URM> */ 02702 vuint32_t CFS2:2; /* <URM>CFS2_TSSI</URM> */ 02703 vuint32_t CFS3:2; /* <URM>CFS3_TSSI</URM> */ 02704 vuint32_t CFS4:2; /* <URM>CFS4_TSSI</URM> */ 02705 vuint32_t CFS5:2; /* <URM>CFS5_TSSI</URM> */ 02706 vuint32_t:4; 02707 vuint32_t ECBNI:1; 02708 vuint32_t LCFTSSI:4; 02709 vuint32_t TC_LCFTSSI:11; 02710 } B; 02711 } CFSSR2; /* CFIFO Status Register 2 <URM>EQADC_CFSSR2</URM> */ 02712 02713 union { 02714 vuint32_t R; 02715 struct { 02716 vuint32_t CFS0:2; 02717 vuint32_t CFS1:2; 02718 vuint32_t CFS2:2; 02719 vuint32_t CFS3:2; 02720 vuint32_t CFS4:2; 02721 vuint32_t CFS5:2; 02722 vuint32_t:20; 02723 } B; 02724 } CFSR; /* <URM>EQADC_CFSR</URM> */ 02725 02726 uint32_t eqadc_reserved11; 02727 02728 union { 02729 vuint32_t R; 02730 struct { 02731 vuint32_t:21; 02732 vuint32_t MDT:3; 02733 vuint32_t:4; 02734 vuint32_t BR:4; 02735 } B; 02736 } SSICR; /* SSI Control Register <URM>EQADC_SSICR</URM> */ 02737 02738 union { 02739 vuint32_t R; 02740 struct { 02741 vuint32_t RDV:1; 02742 vuint32_t:5; 02743 vuint32_t RDATA:26; 02744 } B; 02745 } SSIRDR; /* SSI Recieve Data Register <URM>EQADC_SSIRDR</URM> @ baseaddress + 0xB8 */ 02746 02747 uint32_t eqadc_reserved11b[5]; 02748 02749 uint32_t eqadc_reserved15; /* EQADC Red Line Client Configuration Register @ baseaddress + 0xD0 */ 02750 /* REDLCCR is not implemented in the MPC563xM */ 02751 02752 uint32_t eqadc_reserved12[11]; 02753 02754 struct { 02755 union { 02756 vuint32_t R; 02757 02758 /*<URM>B.CFIFOx_DATAw</URM> */ 02759 02760 } R[4]; /*<URM>EQADC_CFxRw<URM> */ 02761 02762 union { 02763 vuint32_t R; 02764 /*<URM>B.CFIFOx_EDATAw</URM> */ 02765 } EDATA[4]; /*<URM>EQADC_CFxERw</URM> (new in MPC563xM) */ 02766 02767 uint32_t eqadc_reserved13[8]; 02768 02769 } CF[6]; 02770 02771 uint32_t eqadc_reserved14[32]; 02772 02773 struct { 02774 union { 02775 vuint32_t R; 02776 /*<URM>RFIFOx_DATAw</URM> */ 02777 } R[4]; /*<URM>EQADC_RFxRw</URM> */ 02778 02779 uint32_t eqadc_reserved15[12]; 02780 02781 } RF[6]; 02782 02783 }; 02784 /****************************************************************************/ 02785 /* MODULE : DSPI */ 02786 /****************************************************************************/ 02787 struct DSPI_tag { 02788 union { 02789 vuint32_t R; 02790 struct { 02791 vuint32_t MSTR:1; 02792 vuint32_t CONT_SCKE:1; 02793 vuint32_t DCONF:2; 02794 vuint32_t FRZ:1; 02795 vuint32_t MTFE:1; 02796 vuint32_t PCSSE:1; 02797 vuint32_t ROOE:1; 02798 vuint32_t PCSIS7:1; /* new in MPC563xM */ 02799 vuint32_t PCSIS6:1; /* new in MPC563xM */ 02800 vuint32_t PCSIS5:1; 02801 vuint32_t PCSIS4:1; 02802 vuint32_t PCSIS3:1; 02803 vuint32_t PCSIS2:1; 02804 vuint32_t PCSIS1:1; 02805 vuint32_t PCSIS0:1; 02806 vuint32_t DOZE:1; 02807 vuint32_t MDIS:1; 02808 vuint32_t DIS_TXF:1; 02809 vuint32_t DIS_RXF:1; 02810 vuint32_t CLR_TXF:1; 02811 vuint32_t CLR_RXF:1; 02812 vuint32_t SMPL_PT:2; 02813 vuint32_t:7; 02814 vuint32_t HALT:1; 02815 } B; 02816 } MCR; /* Module Configuration Register <URM>DSPI_MCR</URM> @baseaddress + 0x00 */ 02817 02818 uint32_t dspi_reserved1; 02819 02820 union { 02821 vuint32_t R; 02822 struct { 02823 vuint32_t TCNT:16; /* <URM>SPI_TCNT</URM> */ 02824 vuint32_t:16; 02825 } B; 02826 } TCR; /* DSPI Transfer Count Register <URM>DSPI_TCR</URM> @baseaddress + 0x08 */ 02827 02828 union { 02829 vuint32_t R; 02830 struct { 02831 vuint32_t DBR:1; 02832 vuint32_t FMSZ:4; 02833 vuint32_t CPOL:1; 02834 vuint32_t CPHA:1; 02835 vuint32_t LSBFE:1; 02836 vuint32_t PCSSCK:2; 02837 vuint32_t PASC:2; 02838 vuint32_t PDT:2; 02839 vuint32_t PBR:2; 02840 vuint32_t CSSCK:4; 02841 vuint32_t ASC:4; 02842 vuint32_t DT:4; 02843 vuint32_t BR:4; 02844 } B; 02845 } CTAR[8]; /* Clock and Transfer Attributes Registers <URM>DSPI_CTARx</URM> @baseaddress + 0x0C - 0x28 */ 02846 02847 union { 02848 vuint32_t R; 02849 struct { 02850 vuint32_t TCF:1; 02851 vuint32_t TXRXS:1; 02852 vuint32_t:1; 02853 vuint32_t EOQF:1; 02854 vuint32_t TFUF:1; 02855 vuint32_t:1; 02856 vuint32_t TFFF:1; 02857 vuint32_t:5; 02858 vuint32_t RFOF:1; 02859 vuint32_t:1; 02860 vuint32_t RFDF:1; 02861 vuint32_t:1; 02862 vuint32_t TXCTR:4; 02863 vuint32_t TXNXTPTR:4; 02864 vuint32_t RXCTR:4; 02865 vuint32_t POPNXTPTR:4; 02866 } B; 02867 } SR; /* Status Register <URM>DSPI_SR</URM> @baseaddress + 0x2C */ 02868 02869 union { 02870 vuint32_t R; 02871 struct { 02872 vuint32_t TCFRE:1; /*<URM>TCF_RE</URM> */ 02873 vuint32_t:2; 02874 vuint32_t EOQFRE:1; /*<URM>EQQF_RE</URM> */ 02875 vuint32_t TFUFRE:1; /*<URM>TFUF_RE</URM> */ 02876 vuint32_t:1; 02877 vuint32_t TFFFRE:1; /*<URM>TFFF_RE</URM> */ 02878 vuint32_t TFFFDIRS:1; /*<URM>TFFF_DIRS</URM> */ 02879 vuint32_t:4; 02880 vuint32_t RFOFRE:1; /*<URM>RFOF_RE</URM> */ 02881 vuint32_t:1; 02882 vuint32_t RFDFRE:1; /*<URM>RFDF_RE</URM> */ 02883 vuint32_t RFDFDIRS:1; /*<URM>RFDF_DIRS</URM> */ 02884 vuint32_t:16; 02885 } B; 02886 } RSER; /* DMA/Interrupt Request Select and Enable Register <URM>DSPI_RSER</URM> @baseaddress + 0x30 */ 02887 02888 union { 02889 vuint32_t R; 02890 struct { 02891 vuint32_t CONT:1; 02892 vuint32_t CTAS:3; 02893 vuint32_t EOQ:1; 02894 vuint32_t CTCNT:1; 02895 vuint32_t:2; 02896 vuint32_t PCS7:1; /* new in MPC563xM */ 02897 vuint32_t PCS6:1; /* new in MPC563xM */ 02898 vuint32_t PCS5:1; 02899 vuint32_t PCS4:1; 02900 vuint32_t PCS3:1; 02901 vuint32_t PCS2:1; 02902 vuint32_t PCS1:1; 02903 vuint32_t PCS0:1; 02904 vuint32_t TXDATA:16; 02905 } B; 02906 } PUSHR; /* PUSH TX FIFO Register <URM>DSPI_PUSHR</URM> @baseaddress + 0x34 */ 02907 02908 union { 02909 vuint32_t R; 02910 struct { 02911 vuint32_t:16; 02912 vuint32_t RXDATA:16; 02913 } B; 02914 } POPR; /* POP RX FIFO Register <URM>DSPI_POPR</URM> @baseaddress + 0x38 */ 02915 02916 union { 02917 vuint32_t R; 02918 struct { 02919 vuint32_t TXCMD:16; 02920 vuint32_t TXDATA:16; 02921 } B; 02922 } TXFR[4]; /* Transmit FIFO Registers <URM>DSPI_TXFRx</URM> @baseaddress + 0x3c - 0x78 */ 02923 02924 vuint32_t DSPI_reserved_txf[12]; 02925 02926 union { 02927 vuint32_t R; 02928 struct { 02929 vuint32_t:16; 02930 vuint32_t RXDATA:16; 02931 } B; 02932 } RXFR[4]; /* Transmit FIFO Registers <URM>DSPI_RXFRx</URM> @baseaddress + 0x7c - 0xB8 */ 02933 02934 vuint32_t DSPI_reserved_rxf[12]; 02935 02936 union { 02937 vuint32_t R; 02938 struct { 02939 vuint32_t MTOE:1; 02940 vuint32_t:1; 02941 vuint32_t MTOCNT:6; 02942 vuint32_t:3; 02943 vuint32_t TSBC:1; 02944 vuint32_t TXSS:1; 02945 vuint32_t TPOL:1; 02946 vuint32_t TRRE:1; 02947 vuint32_t CID:1; 02948 vuint32_t DCONT:1; 02949 vuint32_t DSICTAS:3; 02950 vuint32_t:4; 02951 vuint32_t DPCS7:1; 02952 vuint32_t DPCS6:1; 02953 vuint32_t DPCS5:1; 02954 vuint32_t DPCS4:1; 02955 vuint32_t DPCS3:1; 02956 vuint32_t DPCS2:1; 02957 vuint32_t DPCS1:1; 02958 vuint32_t DPCS0:1; 02959 } B; 02960 } DSICR; /* DSI Configuration Register <URM>DSPI_DSICR</URM> @baseaddress + 0xBC */ 02961 02962 union { 02963 vuint32_t R; 02964 struct { 02965 vuint32_t SER_DATA:32; /* 32bit instead of 16 in MPC563xM */ 02966 } B; 02967 } SDR; /* DSI Serialization Data Register <URM>DSPI_SDR</URM> @baseaddress + 0xC0 */ 02968 02969 union { 02970 vuint32_t R; 02971 struct { 02972 vuint32_t ASER_DATA:32; /* 32bit instead of 16 in MPC563xM */ 02973 } B; 02974 } ASDR; /* DSI Alternate Serialization Data Register <URM>DSPI_ASDR</URM> @baseaddress + 0xC4 */ 02975 02976 union { 02977 vuint32_t R; 02978 struct { 02979 vuint32_t COMP_DATA:32; /* 32bit instead of 16 in MPC563xM */ 02980 } B; 02981 } COMPR; /* DSI Transmit Comparison Register <URM>DSPI_COMPR</URM> @baseaddress + 0xC8 */ 02982 02983 union { 02984 vuint32_t R; 02985 struct { 02986 vuint32_t DESER_DATA:32; /* 32bit instead of 16 in MPC563xM */ 02987 } B; 02988 } DDR; /* DSI deserialization Data Register <URM>DSPI_DDR</URM> @baseaddress + 0xCC */ 02989 02990 union { 02991 vuint32_t R; 02992 struct { 02993 vuint32_t:3; 02994 vuint32_t TSBCNT:5; 02995 vuint32_t:16; 02996 vuint32_t DPCS1_7:1; 02997 vuint32_t DPCS1_6:1; 02998 vuint32_t DPCS1_5:1; 02999 vuint32_t DPCS1_4:1; 03000 vuint32_t DPCS1_3:1; 03001 vuint32_t DPCS1_2:1; 03002 vuint32_t DPCS1_1:1; 03003 vuint32_t DPCS1_0:1; 03004 } B; 03005 } DSICR1; /* DSI Configuration Register 1 <URM>DSPI_DSICR1</URM> @baseaddress + 0xD0 */ 03006 03007 }; 03008 /****************************************************************************/ 03009 /* MODULE : eSCI */ 03010 /****************************************************************************/ 03011 struct ESCI_tag { 03012 union { 03013 vuint32_t R; 03014 struct { 03015 vuint32_t:3; 03016 vuint32_t SBR:13; 03017 vuint32_t LOOPS:1; 03018 vuint32_t:1; /* Reserved in MPC563xM */ 03019 vuint32_t RSRC:1; 03020 vuint32_t M:1; 03021 vuint32_t WAKE:1; 03022 vuint32_t ILT:1; 03023 vuint32_t PE:1; 03024 vuint32_t PT:1; 03025 vuint32_t TIE:1; 03026 vuint32_t TCIE:1; 03027 vuint32_t RIE:1; 03028 vuint32_t ILIE:1; 03029 vuint32_t TE:1; 03030 vuint32_t RE:1; 03031 vuint32_t RWU:1; 03032 vuint32_t SBK:1; 03033 } B; 03034 } CR1; /* Control Register 1 <URM>SCIBDH, SCIBDL, SCICR1, SCICR2</URM> @baseaddress + 0x00 */ 03035 03036 union { 03037 vuint16_t R; 03038 struct { 03039 vuint16_t MDIS:1; 03040 vuint16_t FBR:1; 03041 vuint16_t BSTP:1; 03042 vuint16_t IEBERR:1; /* <URM>BERIE</URM> */ 03043 vuint16_t RXDMA:1; 03044 vuint16_t TXDMA:1; 03045 vuint16_t BRK13:1; /* <URM>BRCL</URM> */ 03046 vuint16_t TXDIR:1; 03047 vuint16_t BESM13:1; /* <URM>BESM</URM> */ 03048 vuint16_t SBSTP:1; /* <URM>BESTP</URM> */ 03049 vuint16_t RXPOL:1; 03050 vuint16_t PMSK:1; 03051 vuint16_t ORIE:1; 03052 vuint16_t NFIE:1; 03053 vuint16_t FEIE:1; 03054 vuint16_t PFIE:1; 03055 } B; 03056 } CR2; /* Control Register 2 <URM>SCICR3, SCICR4</URM> @baseaddress + 0x04 */ 03057 03058 union { 03059 vuint16_t R; 03060 struct { 03061 vuint16_t R8:1; /* <URM>RN</URM> */ 03062 vuint16_t T8:1; /* <URM>TN</URM> */ 03063 vuint16_t ERR:1; 03064 vuint16_t:1; 03065 vuint16_t R:4; 03066 vuint8_t D; 03067 } B; 03068 } DR; /* Data Register <URM>SCIDRH, SCIDRL</URM> @baseaddress + 0x06 */ 03069 03070 union { 03071 vuint32_t R; 03072 struct { 03073 vuint32_t TDRE:1; 03074 vuint32_t TC:1; 03075 vuint32_t RDRF:1; 03076 vuint32_t IDLE:1; 03077 vuint32_t OR:1; 03078 vuint32_t NF:1; 03079 vuint32_t FE:1; 03080 vuint32_t PF:1; 03081 vuint32_t:3; 03082 vuint32_t BERR:1; 03083 vuint32_t:2; 03084 vuint32_t TACT:1; 03085 vuint32_t RAF:1; /* <URM>RACT</URM> */ 03086 vuint32_t RXRDY:1; 03087 vuint32_t TXRDY:1; 03088 vuint32_t LWAKE:1; 03089 vuint32_t STO:1; 03090 vuint32_t PBERR:1; 03091 vuint32_t CERR:1; 03092 vuint32_t CKERR:1; 03093 vuint32_t FRC:1; 03094 vuint32_t:6; 03095 vuint32_t UREQ:1; 03096 vuint32_t OVFL:1; 03097 } B; 03098 } SR; /* Status Register <URM>SCISR1, SCIRSR2, LINSTAT1, LINSTAT2 </URM> @baseaddress + 0x08 */ 03099 03100 union { 03101 vuint32_t R; 03102 struct { 03103 vuint32_t LRES:1; 03104 vuint32_t WU:1; 03105 vuint32_t WUD0:1; 03106 vuint32_t WUD1:1; 03107 vuint32_t:2; /* reserved: LDBG and DSF not longer supported */ 03108 vuint32_t PRTY:1; 03109 vuint32_t LIN:1; 03110 vuint32_t RXIE:1; 03111 vuint32_t TXIE:1; 03112 vuint32_t WUIE:1; 03113 vuint32_t STIE:1; 03114 vuint32_t PBIE:1; 03115 vuint32_t CIE:1; 03116 vuint32_t CKIE:1; 03117 vuint32_t FCIE:1; 03118 vuint32_t:6; 03119 vuint32_t UQIE:1; 03120 vuint32_t OFIE:1; 03121 vuint32_t:8; 03122 } B; 03123 } LCR; /* LIN Control Register <URM>LINCTRL1, LINCTRL2, LINCTRL3 </URM> @baseaddress + 0x0C */ 03124 03125 union { 03126 vuint32_t R; 03127 } LTR; /* LIN Transmit Register <URM>LINTX</URM> @baseaddress + 0x10 */ 03128 03129 union { 03130 vuint32_t R; 03131 } LRR; /* LIN Recieve Register <URM>LINRX</URM> @baseaddress + 0x14 */ 03132 03133 union { 03134 vuint32_t R; 03135 struct { 03136 vuint32_t P:16; 03137 vuint32_t:3; 03138 vuint32_t SYNM:1; 03139 vuint32_t EROE:1; 03140 vuint32_t ERFE:1; 03141 vuint32_t ERPE:1; 03142 vuint32_t M2:1; 03143 vuint32_t:8; 03144 } B; 03145 } LPR; /* LIN CRC Polynom Register <URM>LINCRCP1, LINCRCP2, SCICR5</URM> @baseaddress + 0x18 */ 03146 03147 }; 03148 /****************************************************************************/ 03149 /* MODULE : eSCI */ 03150 /****************************************************************************/ 03151 struct ESCI_12_13_bit_tag { 03152 union { 03153 vuint16_t R; 03154 struct { 03155 vuint16_t R8:1; 03156 vuint16_t T8:1; 03157 vuint16_t ERR:1; 03158 vuint16_t:1; 03159 vuint16_t D:12; 03160 } B; 03161 } DR; /* Data Register */ 03162 }; 03163 /****************************************************************************/ 03164 /* MODULE : FlexCAN */ 03165 /****************************************************************************/ 03166 struct FLEXCAN_BUF_t { 03167 union { 03168 vuint32_t R; 03169 struct { 03170 vuint32_t:4; 03171 vuint32_t CODE:4; 03172 vuint32_t:1; 03173 vuint32_t SRR:1; 03174 vuint32_t IDE:1; 03175 vuint32_t RTR:1; 03176 vuint32_t LENGTH:4; 03177 vuint32_t TIMESTAMP:16; 03178 } B; 03179 } CS; 03180 03181 union { 03182 vuint32_t R; 03183 struct { 03184 vuint32_t PRIO:3; 03185 vuint32_t STD_ID:11; 03186 vuint32_t EXT_ID:18; 03187 } B; 03188 } ID; 03189 03190 union { 03191 /*vuint8_t B[8]; *//* Data buffer in Bytes (8 bits) *//* Not used in MPC563xM */ 03192 /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) *//* Not used in MPC563xM */ 03193 vuint32_t W[2]; /* Data buffer in words (32 bits) */ 03194 /*vuint32_t R[2]; *//* Data buffer in words (32 bits) *//* Not used in MPC563xM */ 03195 } DATA; 03196 03197 }; /* end of FLEXCAN_BUF_t */ 03198 03199 struct FLEXCAN_RXFIFO_t { 03200 union { 03201 vuint32_t R; 03202 struct { 03203 vuint32_t:9; 03204 vuint32_t SRR:1; 03205 vuint32_t IDE:1; 03206 vuint32_t RTR:1; 03207 vuint32_t LENGTH:4; 03208 vuint32_t TIMESTAMP:16; 03209 } B; 03210 } CS; 03211 03212 union { 03213 vuint32_t R; 03214 struct { 03215 vuint32_t:3; 03216 vuint32_t STD_ID:11; 03217 vuint32_t EXT_ID:18; 03218 } B; 03219 } ID; 03220 03221 union { 03222 /*vuint8_t B[8]; *//* Data buffer in Bytes (8 bits) *//* Not used in MPC563xM */ 03223 /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) *//* Not used in MPC563xM */ 03224 vuint32_t W[2]; /* Data buffer in words (32 bits) */ 03225 /*vuint32_t R[2]; *//* Data buffer in words (32 bits) *//* Not used in MPC563xM */ 03226 } DATA; 03227 03228 uint32_t FLEXCAN_RXFIFO_reserved[20]; /* {0x00E0-0x0090}/0x4 = 0x14 */ 03229 03230 union { 03231 vuint32_t R; 03232 } IDTABLE[8]; 03233 03234 }; /* end of FLEXCAN_RXFIFO_t */ 03235 03236 struct FLEXCAN2_tag { 03237 union { 03238 vuint32_t R; 03239 struct { 03240 vuint32_t MDIS:1; 03241 vuint32_t FRZ:1; 03242 vuint32_t FEN:1; /* new in MPC563xM */ 03243 vuint32_t HALT:1; 03244 vuint32_t NOTRDY:1; /* <URM>NOT_RDY</URM> */ 03245 vuint32_t WAK_MSK:1; /* new in MPC563xM */ 03246 vuint32_t SOFTRST:1; /* <URM>SOFT_RST</URM> */ 03247 vuint32_t FRZACK:1; /* <URM>FRZ_ACK</URM> */ 03248 vuint32_t SUPV:1; /* new in MPC563xM */ 03249 vuint32_t SLF_WAK:1; /* new in MPC563xM */ 03250 03251 vuint32_t WRNEN:1; /* <URM>WRN_EN</URM> */ 03252 03253 vuint32_t MDISACK:1; /* <URM>LPM_ACK</URM> */ 03254 vuint32_t WAK_SRC:1; /* new in MPC563xM */ 03255 vuint32_t DOZE:1; /* new in MPC563xM */ 03256 03257 vuint32_t SRXDIS:1; /* <URM>SRX_DIS</URM> */ 03258 vuint32_t MBFEN:1; /* <URM>BCC</URM> */ 03259 vuint32_t:2; 03260 03261 vuint32_t LPRIO_EN:1; /* new in MPC563xM */ 03262 vuint32_t AEN:1; /* new in MPC563xM */ 03263 vuint32_t:2; 03264 vuint32_t IDAM:2; /* new in MPC563xM */ 03265 vuint32_t:2; 03266 03267 vuint32_t MAXMB:6; 03268 } B; 03269 } MCR; /* Module Configuration Register */ 03270 03271 union { 03272 vuint32_t R; 03273 struct { 03274 vuint32_t PRESDIV:8; 03275 vuint32_t RJW:2; 03276 vuint32_t PSEG1:3; 03277 vuint32_t PSEG2:3; 03278 vuint32_t BOFFMSK:1; /* <URM>BOFF_MSK</URM> */ 03279 vuint32_t ERRMSK:1; /* <URM>ERR_MSK</URM> */ 03280 vuint32_t CLKSRC:1; /* <URM>CLK_SRC</URM> */ 03281 vuint32_t LPB:1; 03282 vuint32_t TWRNMSK:1; /* <URM>TWRN_MSK</URM> */ 03283 vuint32_t RWRNMSK:1; /* <URM>RWRN_MSK</URM> */ 03284 vuint32_t:2; 03285 vuint32_t SMP:1; 03286 vuint32_t BOFFREC:1; /* <URM>BOFF_REC</URM> */ 03287 vuint32_t TSYN:1; 03288 vuint32_t LBUF:1; 03289 vuint32_t LOM:1; 03290 vuint32_t PROPSEG:3; 03291 } B; /* Control Register */ 03292 } CR; /* <URM>CTRL</URM> */ 03293 03294 union { 03295 vuint32_t R; 03296 } TIMER; /* Free Running Timer */ 03297 03298 int32_t FLEXCAN_reserved00; 03299 03300 union { 03301 vuint32_t R; 03302 struct { 03303 vuint32_t:3; 03304 vuint32_t MI:29; 03305 } B; 03306 } RXGMASK; /* RX Global Mask */ 03307 03308 union { 03309 vuint32_t R; 03310 struct { 03311 vuint32_t:3; 03312 vuint32_t MI:29; 03313 } B; 03314 } RX14MASK; /* RX 14 Mask */ 03315 03316 union { 03317 vuint32_t R; 03318 struct { 03319 vuint32_t:3; 03320 vuint32_t MI:29; 03321 } B; 03322 } RX15MASK; /* RX 15 Mask */ 03323 03324 union { 03325 vuint32_t R; 03326 struct { 03327 vuint32_t:16; 03328 vuint32_t RXECNT:8; 03329 vuint32_t TXECNT:8; 03330 } B; 03331 } ECR; /* Error Counter Register */ 03332 03333 union { 03334 vuint32_t R; 03335 struct { 03336 vuint32_t:14; 03337 vuint32_t TWRNINT:1; /* <URM>TWRN_INT</URM> */ 03338 vuint32_t RWRNINT:1; /* <URM>RWRN_INT</URM> */ 03339 vuint32_t BIT1ERR:1; /* <URM>BIT1_ERR</URM> */ 03340 vuint32_t BIT0ERR:1; /* <URM>BIT0_ERR</URM> */ 03341 vuint32_t ACKERR:1; /* <URM>ACK_ERR</URM> */ 03342 vuint32_t CRCERR:1; /* <URM>CRC_ERR</URM> */ 03343 vuint32_t FRMERR:1; /* <URM>FRM_ERR</URM> */ 03344 vuint32_t STFERR:1; /* <URM>STF_ERR</URM> */ 03345 vuint32_t TXWRN:1; /* <URM>TX_WRN</URM> */ 03346 vuint32_t RXWRN:1; /* <URM>RX_WRN</URM> */ 03347 vuint32_t IDLE:1; 03348 vuint32_t TXRX:1; 03349 vuint32_t FLTCONF:2; /* <URM>FLT_CONF</URM> */ 03350 vuint32_t:1; 03351 vuint32_t BOFFINT:1; /* <URM>BOFF_INT</URM> */ 03352 vuint32_t ERRINT:1; /* <URM>ERR_INT</URM> */ 03353 vuint32_t WAK_INT:1; /* new in MPC563xM */ 03354 } B; 03355 } ESR; /* Error and Status Register */ 03356 03357 union { 03358 vuint32_t R; 03359 struct { 03360 vuint32_t BUF63M:1; 03361 vuint32_t BUF62M:1; 03362 vuint32_t BUF61M:1; 03363 vuint32_t BUF60M:1; 03364 vuint32_t BUF59M:1; 03365 vuint32_t BUF58M:1; 03366 vuint32_t BUF57M:1; 03367 vuint32_t BUF56M:1; 03368 vuint32_t BUF55M:1; 03369 vuint32_t BUF54M:1; 03370 vuint32_t BUF53M:1; 03371 vuint32_t BUF52M:1; 03372 vuint32_t BUF51M:1; 03373 vuint32_t BUF50M:1; 03374 vuint32_t BUF49M:1; 03375 vuint32_t BUF48M:1; 03376 vuint32_t BUF47M:1; 03377 vuint32_t BUF46M:1; 03378 vuint32_t BUF45M:1; 03379 vuint32_t BUF44M:1; 03380 vuint32_t BUF43M:1; 03381 vuint32_t BUF42M:1; 03382 vuint32_t BUF41M:1; 03383 vuint32_t BUF40M:1; 03384 vuint32_t BUF39M:1; 03385 vuint32_t BUF38M:1; 03386 vuint32_t BUF37M:1; 03387 vuint32_t BUF36M:1; 03388 vuint32_t BUF35M:1; 03389 vuint32_t BUF34M:1; 03390 vuint32_t BUF33M:1; 03391 vuint32_t BUF32M:1; 03392 } B; /* Interruput Masks Register */ 03393 } IMRH; /* <URM>IMASK2</URM> */ 03394 03395 union { 03396 vuint32_t R; 03397 struct { 03398 vuint32_t BUF31M:1; 03399 vuint32_t BUF30M:1; 03400 vuint32_t BUF29M:1; 03401 vuint32_t BUF28M:1; 03402 vuint32_t BUF27M:1; 03403 vuint32_t BUF26M:1; 03404 vuint32_t BUF25M:1; 03405 vuint32_t BUF24M:1; 03406 vuint32_t BUF23M:1; 03407 vuint32_t BUF22M:1; 03408 vuint32_t BUF21M:1; 03409 vuint32_t BUF20M:1; 03410 vuint32_t BUF19M:1; 03411 vuint32_t BUF18M:1; 03412 vuint32_t BUF17M:1; 03413 vuint32_t BUF16M:1; 03414 vuint32_t BUF15M:1; 03415 vuint32_t BUF14M:1; 03416 vuint32_t BUF13M:1; 03417 vuint32_t BUF12M:1; 03418 vuint32_t BUF11M:1; 03419 vuint32_t BUF10M:1; 03420 vuint32_t BUF09M:1; 03421 vuint32_t BUF08M:1; 03422 vuint32_t BUF07M:1; 03423 vuint32_t BUF06M:1; 03424 vuint32_t BUF05M:1; 03425 vuint32_t BUF04M:1; 03426 vuint32_t BUF03M:1; 03427 vuint32_t BUF02M:1; 03428 vuint32_t BUF01M:1; 03429 vuint32_t BUF00M:1; 03430 } B; /* Interruput Masks Register */ 03431 } IMRL; /* <URM>IMASK1</URM> */ 03432 03433 union { 03434 vuint32_t R; 03435 struct { 03436 vuint32_t BUF63I:1; 03437 vuint32_t BUF62I:1; 03438 vuint32_t BUF61I:1; 03439 vuint32_t BUF60I:1; 03440 vuint32_t BUF59I:1; 03441 vuint32_t BUF58I:1; 03442 vuint32_t BUF57I:1; 03443 vuint32_t BUF56I:1; 03444 vuint32_t BUF55I:1; 03445 vuint32_t BUF54I:1; 03446 vuint32_t BUF53I:1; 03447 vuint32_t BUF52I:1; 03448 vuint32_t BUF51I:1; 03449 vuint32_t BUF50I:1; 03450 vuint32_t BUF49I:1; 03451 vuint32_t BUF48I:1; 03452 vuint32_t BUF47I:1; 03453 vuint32_t BUF46I:1; 03454 vuint32_t BUF45I:1; 03455 vuint32_t BUF44I:1; 03456 vuint32_t BUF43I:1; 03457 vuint32_t BUF42I:1; 03458 vuint32_t BUF41I:1; 03459 vuint32_t BUF40I:1; 03460 vuint32_t BUF39I:1; 03461 vuint32_t BUF38I:1; 03462 vuint32_t BUF37I:1; 03463 vuint32_t BUF36I:1; 03464 vuint32_t BUF35I:1; 03465 vuint32_t BUF34I:1; 03466 vuint32_t BUF33I:1; 03467 vuint32_t BUF32I:1; 03468 } B; /* Interruput Flag Register */ 03469 } IFRH; /* <URM>IFLAG2</URM> */ 03470 03471 union { 03472 vuint32_t R; 03473 struct { 03474 vuint32_t BUF31I:1; 03475 vuint32_t BUF30I:1; 03476 vuint32_t BUF29I:1; 03477 vuint32_t BUF28I:1; 03478 vuint32_t BUF27I:1; 03479 vuint32_t BUF26I:1; 03480 vuint32_t BUF25I:1; 03481 vuint32_t BUF24I:1; 03482 vuint32_t BUF23I:1; 03483 vuint32_t BUF22I:1; 03484 vuint32_t BUF21I:1; 03485 vuint32_t BUF20I:1; 03486 vuint32_t BUF19I:1; 03487 vuint32_t BUF18I:1; 03488 vuint32_t BUF17I:1; 03489 vuint32_t BUF16I:1; 03490 vuint32_t BUF15I:1; 03491 vuint32_t BUF14I:1; 03492 vuint32_t BUF13I:1; 03493 vuint32_t BUF12I:1; 03494 vuint32_t BUF11I:1; 03495 vuint32_t BUF10I:1; 03496 vuint32_t BUF09I:1; 03497 vuint32_t BUF08I:1; 03498 vuint32_t BUF07I:1; 03499 vuint32_t BUF06I:1; 03500 vuint32_t BUF05I:1; 03501 vuint32_t BUF04I:1; 03502 vuint32_t BUF03I:1; 03503 vuint32_t BUF02I:1; 03504 vuint32_t BUF01I:1; 03505 vuint32_t BUF00I:1; 03506 } B; /* Interruput Flag Register */ 03507 } IFRL; /* <URM>IFLAG1</URM> */ 03508 03509 uint32_t flexcan2_reserved2[19]; 03510 03511 /****************************************************************************/ 03512 /* Use either Standard Buffer Structure OR RX FIFO and Buffer Structure */ 03513 /****************************************************************************/ 03514 /* Standard Buffer Structure */ 03515 struct FLEXCAN_BUF_t BUF[64]; 03516 03517 /* RX FIFO and Buffer Structure *//* New options in MPC563xM */ 03518 /*struct FLEXCAN_RXFIFO_t RXFIFO; */ 03519 /*struct FLEXCAN_BUF_t BUF[56]; */ 03520 /****************************************************************************/ 03521 03522 uint32_t FLEXCAN_reserved3[256]; /* {0x0880-0x0480}/0x4 = 0x100 *//* (New in MPC563xM) Address Base + 0x0034 */ 03523 03524 union { 03525 vuint32_t R; 03526 struct { 03527 vuint32_t MI:32; 03528 } B; /* RX Individual Mask Registers */ 03529 } RXIMR[64]; /* (New in MPC563xM) Address Base + 0x0880 */ 03530 03531 }; /* end of FLEXCAN_tag */ 03532 /****************************************************************************/ 03533 /* MODULE : Decimation Filter (DECFIL) */ 03534 /****************************************************************************/ 03535 struct DECFIL_tag { 03536 union { 03537 vuint32_t R; 03538 struct { 03539 vuint32_t MDIS:1; 03540 vuint32_t FREN:1; 03541 vuint32_t:1; 03542 vuint32_t FRZ:1; 03543 vuint32_t SRES:1; 03544 vuint32_t:2; /* CASCD not supported in MPC563xM */ 03545 vuint32_t IDEN:1; 03546 vuint32_t ODEN:1; 03547 vuint32_t ERREN:1; 03548 vuint32_t:1; 03549 vuint32_t FTYPE:2; 03550 vuint32_t:1; 03551 vuint32_t SCAL:2; 03552 vuint32_t:1; 03553 vuint32_t SAT:1; 03554 vuint32_t ISEL:1; 03555 vuint32_t:1; /* MIXM does not appear to be implemented on the MPC563xM */ 03556 vuint32_t DEC_RATE:4; 03557 vuint32_t:1; /* SDIE not supported in MPC563xM */ 03558 vuint32_t DSEL:1; 03559 vuint32_t IBIE:1; 03560 vuint32_t OBIE:1; 03561 vuint32_t EDME:1; 03562 vuint32_t TORE:1; 03563 vuint32_t TMODE:2; /* the LSB of TMODE is always 0 on the MPC563xM */ 03564 } B; 03565 } MCR; /* Configuration Register <URM>DECFILTER_MCR</URM> @baseaddress + 0x00 */ 03566 03567 union { 03568 vuint32_t R; 03569 struct { 03570 vuint32_t BSY:1; 03571 vuint32_t:1; 03572 vuint32_t DEC_COUNTER:4; 03573 vuint32_t IDFC:1; 03574 vuint32_t ODFC:1; 03575 vuint32_t SDFC:1; /* SDFC not supported in MPC563xM */ 03576 vuint32_t IBIC:1; 03577 vuint32_t OBIC:1; 03578 vuint32_t SVRC:1; /* SVRC not supported in MPC563xM */ 03579 vuint32_t DIVRC:1; 03580 vuint32_t OVFC:1; 03581 vuint32_t OVRC:1; 03582 vuint32_t IVRC:1; 03583 vuint32_t:6; 03584 vuint32_t IDF:1; 03585 vuint32_t ODF:1; 03586 vuint32_t SDF:1; /* SDF not supported in MPC563xM */ 03587 vuint32_t IBIF:1; 03588 vuint32_t OBIF:1; 03589 vuint32_t SVR:1; /* SVR not supported in MPC563xM */ 03590 vuint32_t DIVR:1; 03591 vuint32_t OVF:1; 03592 vuint32_t OVR:1; 03593 vuint32_t IVR:1; 03594 } B; 03595 } MSR; /* Status Register <URM>DECFILTER_MSR</URM> @baseaddress + 0x04 */ 03596 03597 /* Module Extended Config.Register - not siupported on the MPC563xM <URM>DECFILTER_MXCR</URM> @baseaddress + 0x08 */ 03598 03599 uint32_t decfil_reserved1[2]; 03600 03601 union { 03602 vuint32_t R; 03603 struct { 03604 vuint32_t:4; 03605 vuint32_t INTAG:4; 03606 vuint32_t:6; 03607 vuint32_t PREFILL:1; 03608 vuint32_t FLUSH:1; 03609 vuint32_t INPBUF:16; 03610 } B; 03611 } IB; /* Interface Input Buffer <URM>DECFILTER_IB</URM> @baseaddress + 0x10 */ 03612 03613 union { 03614 vuint32_t R; 03615 struct { 03616 vuint32_t:12; 03617 vuint32_t OUTTAG:4; 03618 vuint32_t OUTBUF:16; 03619 } B; 03620 } OB; /* Interface Output Buffer <URM>DECFILTER_OB</URM> @baseaddress + 0x14 */ 03621 03622 uint32_t decfil_reserved2[2]; 03623 03624 union { 03625 vuint32_t R; 03626 struct { 03627 vuint32_t:8; 03628 vuint32_t COEF:24; 03629 } B; 03630 } COEF[9]; /* Filter Coefficient Registers <URM>DECFILTER_COEFx</URM> @baseaddress + 0x20 - 0x40 */ 03631 03632 uint32_t decfil_reserved3[13]; 03633 03634 union { 03635 vuint32_t R; 03636 struct { 03637 vuint32_t:8; 03638 vuint32_t TAP:24; 03639 } B; 03640 } TAP[8]; /* Filter TAP Registers <URM>DECFILTER_TAPx</URM> @baseaddress + 0x78 - 0x94 */ 03641 03642 uint32_t decfil_reserved4[14]; 03643 03644 /* 0x0D0 */ 03645 union { 03646 vuint16_t R; 03647 struct { 03648 vuint32_t:16; 03649 vuint32_t SAMP_DATA:16; 03650 } B; 03651 } EDID; /* Filter EDID Registers <URM>DECFILTER_EDID</URM> @baseaddress + 0xD0 */ 03652 03653 uint32_t decfil_reserved5[3]; 03654 03655 /* 0x0E0 */ 03656 uint32_t decfil_reserved6; 03657 /* Filter FINTVAL Registers - Not supported on MPC563xM <URM>DECFILTER_FINTVAL</URM> @baseaddress + 0xE0 */ 03658 03659 /* 0x0E4 */ 03660 uint32_t decfil_reserved7; 03661 /* Filter FINTCNT Registers - Not supported on MPC563xM <URM>DECFILTER_FINTCNT</URM> @baseaddress + 0xE4 */ 03662 03663 /* 0x0E8 */ 03664 uint32_t decfil_reserved8; 03665 /* Filter CINTVAL Registers - Not supported on MPC563xM <URM>DECFILTER_CINTVAL</URM> @baseaddress + 0xE8 */ 03666 03667 /* 0x0EC */ 03668 uint32_t decfil_reserved9; 03669 /* Filter CINTCNT Registers - Not supported on MPC563xM <URM>DECFILTER_CINTCNT</URM> @baseaddress + 0xEC */ 03670 03671 }; 03672 /****************************************************************************/ 03673 /* MODULE : Periodic Interval Timer (PIT) */ 03674 /****************************************************************************/ 03675 struct PIT_tag { 03676 03677 union { 03678 vuint32_t R; 03679 struct { 03680 vuint32_t:29; 03681 vuint32_t MDIS_RTI:1; 03682 vuint32_t MDIS:1; 03683 vuint32_t FRZ:1; 03684 } B; 03685 } PITMCR; /* PIT Module Control Register */ 03686 03687 uint32_t pit_reserved1[59]; 03688 03689 struct { 03690 union { 03691 vuint32_t R; /* <URM>TSVn</URM> */ 03692 } LDVAL; /* Timer Load Value Register */ 03693 03694 union { 03695 vuint32_t R; /* <URM>TVLn</URM> */ 03696 } CVAL; /* Current Timer Value Register */ 03697 03698 union { 03699 vuint32_t R; 03700 struct { 03701 vuint32_t:30; 03702 vuint32_t TIE:1; 03703 vuint32_t TEN:1; 03704 } B; 03705 } TCTRL; /* Timer Control Register */ 03706 03707 union { 03708 vuint32_t R; 03709 struct { 03710 vuint32_t:31; 03711 vuint32_t TIF:1; 03712 } B; 03713 } TFLG; /* Timer Flag Register */ 03714 } RTI; /* RTI Channel */ 03715 03716 struct { 03717 union { 03718 vuint32_t R; 03719 } LDVAL; /* Timer Load Value Register */ 03720 03721 union { 03722 vuint32_t R; 03723 } CVAL; /* Current Timer Value Register */ 03724 03725 union { 03726 vuint32_t R; 03727 struct { 03728 vuint32_t:30; 03729 vuint32_t TIE:1; 03730 vuint32_t TEN:1; 03731 } B; 03732 } TCTRL; /* Timer Control Register */ 03733 03734 union { 03735 vuint32_t R; 03736 struct { 03737 vuint32_t:31; 03738 vuint32_t TIF:1; 03739 } B; 03740 } TFLG; /* Timer Flag Register */ 03741 } TIMER[4]; /* Timer Channels */ 03742 03743 }; 03744 /****************************************************************************/ 03745 /* MODULE : System Timer Module (STM) */ 03746 /****************************************************************************/ 03747 struct STM_tag { 03748 union { 03749 vuint32_t R; 03750 struct { 03751 vuint32_t:16; 03752 vuint32_t CPS:8; 03753 vuint32_t:6; 03754 vuint32_t FRZ:1; 03755 vuint32_t TEN:1; 03756 } B; 03757 } CR; /* STM Control Register <URM>STM_CR</URM> (new in MPC563xM) Offset 0x0000 */ 03758 03759 union { 03760 vuint32_t R; 03761 } CNT; /* STM Count Register <URM>STM_CNT</URM> (new in MPC563xM) Offset Offset 0x0004 */ 03762 03763 uint32_t stm_reserved1[2]; /* Reserved (new in MPC563xM) Offset Offset 0x0008 */ 03764 03765 union { 03766 vuint32_t R; 03767 struct { 03768 vuint32_t:31; 03769 vuint32_t CEN:1; 03770 } B; 03771 } CCR0; /* STM Channel Control Register <URM>STM_CCR0</URM> (new in MPC563xM) Offset 0x0010 */ 03772 03773 union { 03774 vuint32_t R; 03775 struct { 03776 vuint32_t:31; 03777 vuint32_t CIF:1; 03778 } B; 03779 } CIR0; /* STM Channel Interrupt Register <URM>STM_CIR0</URM> (new in MPC563xM) Offset 0x0014 */ 03780 03781 union { 03782 vuint32_t R; 03783 } CMP0; /* STM Channel Compare Register <URM>STM_CMP0</URM> (new in MPC563xM) Offset Offset 0x0018 */ 03784 03785 uint32_t stm_reserved2; /* Reserved (new in MPC563xM) Offset Offset 0x001C */ 03786 03787 union { 03788 vuint32_t R; 03789 struct { 03790 vuint32_t:31; 03791 vuint32_t CEN:1; 03792 } B; 03793 } CCR1; /* STM Channel Control Register <URM>STM_CCR1</URM> (new in MPC563xM) Offset 0x0020 */ 03794 03795 union { 03796 vuint32_t R; 03797 struct { 03798 vuint32_t:31; 03799 vuint32_t CIF:1; 03800 } B; 03801 } CIR1; /* STM Channel Interrupt Register <URM>STM_CIR1</URM> (new in MPC563xM) Offset 0x0024 */ 03802 03803 union { 03804 vuint32_t R; 03805 } CMP1; /* STM Channel Compare Register <URM>STM_CMP1</URM> (new in MPC563xM) Offset Offset 0x0028 */ 03806 03807 uint32_t stm_reserved3; /* Reserved (new in MPC563xM) Offset Offset 0x002C */ 03808 03809 union { 03810 vuint32_t R; 03811 struct { 03812 vuint32_t:31; 03813 vuint32_t CEN:1; 03814 } B; 03815 } CCR2; /* STM Channel Control Register <URM>STM_CCR2</URM> (new in MPC563xM) Offset 0x0030 */ 03816 03817 union { 03818 vuint32_t R; 03819 struct { 03820 vuint32_t:31; 03821 vuint32_t CIF:1; 03822 } B; 03823 } CIR2; /* STM Channel Interrupt Register <URM>STM_CIR2</URM> (new in MPC563xM) Offset 0x0034 */ 03824 03825 union { 03826 vuint32_t R; 03827 } CMP2; /* STM Channel Compare Register <URM>STM_CMP2</URM> (new in MPC563xM) Offset Offset 0x0038 */ 03828 03829 uint32_t stm_reserved4; /* Reserved (new in MPC563xM) Offset Offset 0x003C */ 03830 03831 union { 03832 vuint32_t R; 03833 struct { 03834 vuint32_t:31; 03835 vuint32_t CEN:1; 03836 } B; 03837 } CCR3; /* STM Channel Control Register <URM>STM_CCR3</URM> (new in MPC563xM) Offset 0x0040 */ 03838 03839 union { 03840 vuint32_t R; 03841 struct { 03842 vuint32_t:31; 03843 vuint32_t CIF:1; 03844 } B; 03845 } CIR3; /* STM Channel Interrupt Register <URM>STM_CIR3</URM> (new in MPC563xM) Offset 0x0044 */ 03846 03847 union { 03848 vuint32_t R; 03849 } CMP3; /* STM Channel Compare Register <URM>STM_CMP3</URM> (new in MPC563xM) Offset Offset 0x0048 */ 03850 03851 uint32_t stm_reserved5; /* Reserved (new in MPC563xM) Offset Offset 0x004C */ 03852 }; 03853 03854 /****************************************************************************/ 03855 /* MODULE : SWT */ 03856 /****************************************************************************/ 03857 03858 struct SWT_tag { 03859 union { 03860 vuint32_t R; 03861 struct { 03862 vuint32_t MAP0:1; 03863 vuint32_t MAP1:1; 03864 vuint32_t MAP2:1; 03865 vuint32_t MAP3:1; 03866 vuint32_t MAP4:1; 03867 vuint32_t MAP5:1; 03868 vuint32_t MAP6:1; 03869 vuint32_t MAP7:1; 03870 vuint32_t:14; 03871 vuint32_t KEY:1; 03872 vuint32_t RIA:1; 03873 vuint32_t WND:1; 03874 vuint32_t ITR:1; 03875 vuint32_t HLK:1; 03876 vuint32_t SLK:1; 03877 vuint32_t CSL:1; 03878 vuint32_t STP:1; 03879 vuint32_t FRZ:1; 03880 vuint32_t WEN:1; 03881 } B; 03882 } MCR; /*<URM>SWT_CR</URM> *//* Module Configuration Register */ 03883 03884 union { 03885 vuint32_t R; 03886 struct { 03887 vuint32_t:31; 03888 vuint32_t TIF:1; 03889 } B; 03890 } IR; /* Interrupt register <URM>SWT_IR</URM> */ 03891 03892 union { 03893 vuint32_t R; 03894 struct { 03895 vuint32_t WTO:32; 03896 } B; 03897 } TO; /* Timeout register <URM>SWT_TO</URM> */ 03898 03899 union { 03900 vuint32_t R; 03901 struct { 03902 vuint32_t WST:32; 03903 03904 } B; 03905 } WN; /* Window register <URM>SWT_WN</URM> */ 03906 03907 union { 03908 vuint32_t R; 03909 struct { 03910 vuint32_t:16; 03911 vuint32_t WSC:16; 03912 } B; 03913 } SR; /* Service register <URM>SWT_SR</URM> */ 03914 03915 union { 03916 vuint32_t R; 03917 struct { 03918 vuint32_t CNT:32; 03919 } B; 03920 } CO; /* Counter output register <URM>SWT_CO</URM> */ 03921 03922 union { 03923 vuint32_t R; 03924 struct { 03925 vuint32_t:16; 03926 vuint32_t SK:16; 03927 } B; 03928 } SK; /* Service key register <URM>SWT_SK</URM> */ 03929 }; 03930 /****************************************************************************/ 03931 /* MODULE : Power Management Controller (PMC) */ 03932 /****************************************************************************/ 03933 struct PMC_tag { 03934 union { 03935 vuint32_t R; 03936 struct { 03937 vuint32_t LVRER:1; /* <URM> LVIRR </URM> */ 03938 vuint32_t LVREH:1; /* <URM> LVIHR </URM> */ 03939 vuint32_t LVRE50:1; /* <URM> LVI5R </URM> */ 03940 vuint32_t LVRE33:1; /* <URM> LVI3R </URM> */ 03941 vuint32_t LVREC:1; /* <URM> LVI1R </URM> */ 03942 vuint32_t:3; 03943 vuint32_t LVIER:1; /* <URM> LVIRE </URM> */ 03944 vuint32_t LVIEH:1; /* <URM> LVIHE </URM> */ 03945 vuint32_t LVIE50:1; /* <URM> LVI5E </URM> */ 03946 vuint32_t LVIE33:1; /* <URM> LVI3E </URM> */ 03947 vuint32_t LVIC:1; /* <URM> LVI1E </URM> */ 03948 vuint32_t:2; 03949 vuint32_t TLK:1; 03950 vuint32_t:16; 03951 } B; 03952 } MCR; /* Module Configuration register <URM> CFGR </URM> */ 03953 03954 union { 03955 vuint32_t R; 03956 struct { 03957 vuint32_t:12; 03958 vuint32_t LVDREGTRIM:4; /* <URM> LVI50TRIM </URM> */ 03959 vuint32_t VDD33TRIM:4; /* <URM> BV33TRIM </URM> */ 03960 vuint32_t LVD33TRIM:4; /* <URM> LVI33TRIM </URM> */ 03961 vuint32_t VDDCTRIM:4; /* <URM> V12TRIM </URM> */ 03962 vuint32_t LVDCTRIM:4; /* <URM> LVI33TRIM </URM> */ 03963 } B; 03964 } TRIMR; /* Trimming register */ 03965 03966 union { 03967 vuint32_t R; 03968 struct { 03969 vuint32_t:5; 03970 vuint32_t LVFVSTBY:1; 03971 vuint32_t BGRDY:1; /* <URM> BGS1 </URM> */ 03972 vuint32_t BGTS:1; /* <URM> BGS2 </URM> */ 03973 vuint32_t:5; 03974 vuint32_t LVFCSTBY:1; 03975 vuint32_t:1; 03976 vuint32_t V33DIS:1; /* 3.3V Regulator Disable <URM> V33S </URM> */ 03977 vuint32_t LVFCR:1; /* Clear LVFR <URM> LVIRC </URM> */ 03978 vuint32_t LVFCH:1; /* Clear LVFH <URM> LVIHC </URM> */ 03979 vuint32_t LVFC50:1; /* Clear LVF5 <URM> LVI5 </URM> */ 03980 vuint32_t LVFC33:1; /* Clear LVF3 <URM> LVI3 </URM> */ 03981 vuint32_t LVFCC:1; /* Clear LVFC <URM> LVI1 </URM> */ 03982 vuint32_t:3; 03983 vuint32_t LVFR:1; /* Low Voltage Flag Reset Supply <URM> LVIRF </URM> */ 03984 vuint32_t LVFH:1; /* Low Voltage Flag VDDEH Supply <URM> LVIHF </URM> */ 03985 vuint32_t LVF50:1; /* Low Voltage Flag 5V Supply <URM> LVI5F </URM> */ 03986 vuint32_t LVF33:1; /* Low Voltage Flag 3.3V Supply <URM> LVI3F </URM> */ 03987 vuint32_t LVFC:1; /* Low Voltage Flag Core (1.2V) <URM> LVI1F </URM> */ 03988 vuint32_t:3; 03989 03990 } B; 03991 } SR; /* status register */ 03992 }; 03993 /****************************************************************************/ 03994 /* MODULE : TSENS (Temperature Sensor) */ 03995 /****************************************************************************/ 03996 03997 struct TSENS_tag { 03998 03999 union { 04000 vuint32_t R; 04001 struct { 04002 vuint32_t TSCV2:16; 04003 vuint32_t TSCV1:16; 04004 } B; 04005 } TCCR0; /* Temperature Sensor Calibration B @baseaddress + 0x00 */ 04006 04007 union { 04008 vuint32_t R; 04009 struct { 04010 vuint32_t:16; 04011 vuint32_t TSCV3:16; 04012 } B; 04013 } TCCR1; /* Temperature Sensor Calibration A @baseaddress + 0x04 */ 04014 04015 uint32_t TSENS_reserved0008[16382]; /* 0x0008-0xFFFF */ 04016 04017 }; 04018 04019 /* Define memories */ 04020 /* Comments need to be moved for different memory sizes */ 04021 04022 #define SRAM_START 0x40000000 04023 /*#define SRAM_SIZE 0xC000 48K SRAM */ 04024 /*#define SRAM_SIZE 0x10000 64K SRAM */ 04025 #define SRAM_SIZE 0x17800 /* 94K SRAM */ 04026 /*#define SRAM_END 0x4000BFFF 48K SRAM */ 04027 /*#define SRAM_END 0x4000FFFF 64K SRAM */ 04028 #define SRAM_END 0x400177FF /* 94K SRAM */ 04029 04030 #define FLASH_START 0x0 04031 /*#define FLASH_SIZE 0x100000 1M Flash */ 04032 #define FLASH_SIZE 0x180000 /* 1.5M Flash */ 04033 /*#define FLASH_END 0xFFFFF 1M Flash */ 04034 #define FLASH_END 0x17FFFF /* 1.5M Flash */ 04035 04036 /* Shadow Flash start and end address */ 04037 #define FLASH_SHADOW_START 0x00FFC000 04038 #define FLASH_SHADOW_SIZE 0x4000 04039 #define FLASH_SHADOW_END 0x00FFFFFF 04040 04041 /* Define instances of modules */ 04042 #define FMPLL (*( volatile struct FMPLL_tag *) 0xC3F80000) 04043 #define EBI (*( volatile struct EBI_tag *) 0xC3F84000) 04044 #define CFLASH0 (*( volatile struct FLASH_tag *) 0xC3F88000) 04045 #define CFLASH1 (*( volatile struct FLASH_tag *) 0xC3FB0000) 04046 #define CFLASH2 (*( volatile struct FLASH_tag *) 0xC3FB4000) 04047 #define SIU (*( volatile struct SIU_tag *) 0xC3F90000) 04048 04049 #define EMIOS (*( volatile struct EMIOS_tag *) 0xC3FA0000) 04050 #define PMC (*( volatile struct PMC_tag *) 0xC3FBC000) 04051 #define ETPU (*( volatile struct ETPU_tag *) 0xC3FC0000) 04052 #define ETPU_DATA_RAM (*( uint32_t *) 0xC3FC8000) 04053 #define ETPU_DATA_RAM_EXT (*( uint32_t *) 0xC3FCC000) 04054 #define ETPU_DATA_RAM_END 0xC3FC8BFC 04055 #define CODE_RAM (*( uint32_t *) 0xC3FD0000) 04056 #define ETPU_CODE_RAM (*( uint32_t *) 0xC3FD0000) 04057 #define PIT (*( volatile struct PIT_tag *) 0xC3FF0000) 04058 04059 #define XBAR (*( volatile struct XBAR_tag *) 0xFFF04000) 04060 #define SWT (*( volatile struct SWT_tag *) 0xFFF38000) 04061 #define STM (*( volatile struct STM_tag *) 0xFFF3C000) 04062 #define ECSM (*( volatile struct ECSM_tag *) 0xFFF40000) 04063 #define EDMA (*( volatile struct EDMA_tag *) 0xFFF44000) 04064 #define INTC (*( volatile struct INTC_tag *) 0xFFF48000) 04065 04066 #define EQADC (*( volatile struct EQADC_tag *) 0xFFF80000) 04067 #define DECFIL (*( volatile struct DECFIL_tag *) 0xFFF88000) 04068 04069 #define DSPI_B (*( volatile struct DSPI_tag *) 0xFFF94000) 04070 #define DSPI_C (*( volatile struct DSPI_tag *) 0xFFF98000) 04071 04072 #define ESCI_A (*( volatile struct ESCI_tag *) 0xFFFB0000) 04073 #define ESCI_A_12_13 (*( volatile struct ESCI_12_13_bit_tag *) 0xFFFB0006) 04074 #define ESCI_B (*( volatile struct ESCI_tag *) 0xFFFB4000) 04075 #define ESCI_B_12_13 (*( volatile struct ESCI_12_13_bit_tag *) 0xFFFB4006) 04076 04077 #define CAN_A (*( volatile struct FLEXCAN2_tag *) 0xFFFC0000) 04078 #define CAN_C (*( volatile struct FLEXCAN2_tag *) 0xFFFC8000) 04079 04080 #define TSENS (*( volatile struct TSENS_tag *) 0xFFFEC000) 04081 04082 #ifdef __MWERKS__ 04083 #pragma pop 04084 #endif /* 04085 */ 04086 04087 #ifdef __cplusplus 04088 } 04089 #endif /* 04090 */ 04091 04092 #endif /* ifdef _MPC563M_H */ 04093 /********************************************************************* 04094 * 04095 * Copyright: 04096 * Freescale Semiconductor, INC. All Rights Reserved. 04097 * You are hereby granted a copyright license to use, modify, and 04098 * distribute the SOFTWARE so long as this entire notice is 04099 * retained without alteration in any modified and/or redistributed 04100 * versions, and that such modified versions are clearly identified 04101 * as such. No licenses are granted by implication, estoppel or 04102 * otherwise under any patents or trademarks of Freescale 04103 * Semiconductor, Inc. This software is provided on an "AS IS" 04104 * basis and without warranty. 04105 * 04106 * To the maximum extent permitted by applicable law, Freescale 04107 * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, 04108 * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A 04109 * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH 04110 * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) 04111 * AND ANY ACCOMPANYING WRITTEN MATERIALS. 04112 * 04113 * To the maximum extent permitted by applicable law, IN NO EVENT 04114 * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER 04115 * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, 04116 * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER 04117 * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. 04118 * 04119 * Freescale Semiconductor assumes no responsibility for the 04120 * maintenance and support of this software 04121 * 04122 ********************************************************************/ 04123