mirror of
https://salsa.debian.org/gnuk-team/gnuk/gnuk.git
synced 2024-09-21 11:20:08 +00:00
600 lines
14 KiB
C
600 lines
14 KiB
C
/*
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* sys.c - system routines for the initial page for STM32F103.
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*
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* Copyright (C) 2013 Flying Stone Technology
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* Author: NIIBE Yutaka <gniibe@fsij.org>
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*
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* Copying and distribution of this file, with or without modification,
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* are permitted in any medium without royalty provided the copyright
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* notice and this notice are preserved. This file is offered as-is,
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* without any warranty.
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*
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* When the flash ROM is protected, we cannot modify the initial page.
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* We put some system routines (which is useful for any program) here.
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*/
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#include <stdint.h>
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#include <stdlib.h>
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#include "board.h"
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#define CORTEX_PRIORITY_BITS 4
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#define CORTEX_PRIORITY_MASK(n) ((n) << (8 - CORTEX_PRIORITY_BITS))
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#define USB_LP_CAN1_RX0_IRQn 20
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#define STM32_USB_IRQ_PRIORITY 11
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#define STM32_SW_PLL (2 << 0)
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#define STM32_PLLSRC_HSE (1 << 16)
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#define STM32_PLLXTPRE_DIV1 (0 << 17)
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#define STM32_PLLXTPRE_DIV2 (1 << 17)
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#define STM32_HPRE_DIV1 (0 << 4)
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#define STM32_PPRE1_DIV2 (4 << 8)
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#define STM32_PPRE2_DIV1 (0 << 11)
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#define STM32_PPRE2_DIV2 (4 << 11)
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#define STM32_ADCPRE_DIV4 (1 << 14)
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#define STM32_ADCPRE_DIV6 (2 << 14)
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#define STM32_USBPRE_DIV1P5 (0 << 22)
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#define STM32_MCO_NOCLOCK (0 << 24)
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#define STM32_SW STM32_SW_PLL
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#define STM32_PLLSRC STM32_PLLSRC_HSE
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#define STM32_HPRE STM32_HPRE_DIV1
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#define STM32_PPRE1 STM32_PPRE1_DIV2
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#define STM32_PPRE2 STM32_PPRE2_DIV1
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#define STM32_ADCPRE STM32_ADCPRE_DIV6
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#define STM32_MCOSEL STM32_MCO_NOCLOCK
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#define STM32_USBPRE STM32_USBPRE_DIV1P5
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#define STM32_PLLCLKIN (STM32_HSECLK / 1)
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#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18)
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#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
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#define STM32_SYSCLK STM32_PLLCLKOUT
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#define STM32_HCLK (STM32_SYSCLK / 1)
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#define STM32_FLASHBITS 0x00000012
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struct NVIC {
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uint32_t ISER[8];
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uint32_t unused1[24];
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uint32_t ICER[8];
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uint32_t unused2[24];
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uint32_t ISPR[8];
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uint32_t unused3[24];
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uint32_t ICPR[8];
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uint32_t unused4[24];
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uint32_t IABR[8];
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uint32_t unused5[56];
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uint32_t IPR[60];
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};
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static struct NVIC *const NVICBase = ((struct NVIC *const)0xE000E100);
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#define NVIC_ISER(n) (NVICBase->ISER[n >> 5])
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#define NVIC_ICPR(n) (NVICBase->ICPR[n >> 5])
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#define NVIC_IPR(n) (NVICBase->IPR[n >> 2])
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static void
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nvic_enable_vector (uint32_t n, uint32_t prio)
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{
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unsigned int sh = (n & 3) << 3;
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NVIC_IPR (n) = (NVIC_IPR(n) & ~(0xFF << sh)) | (prio << sh);
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NVIC_ICPR (n) = 1 << (n & 0x1F);
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NVIC_ISER (n) = 1 << (n & 0x1F);
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}
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#define PERIPH_BASE 0x40000000
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#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
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#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
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struct RCC {
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volatile uint32_t CR;
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volatile uint32_t CFGR;
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volatile uint32_t CIR;
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volatile uint32_t APB2RSTR;
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volatile uint32_t APB1RSTR;
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volatile uint32_t AHBENR;
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volatile uint32_t APB2ENR;
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volatile uint32_t APB1ENR;
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volatile uint32_t BDCR;
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volatile uint32_t CSR;
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};
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#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
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static struct RCC *const RCC = ((struct RCC *const)RCC_BASE);
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#define RCC_APB1ENR_USBEN 0x00800000
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#define RCC_APB1RSTR_USBRST 0x00800000
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#define RCC_CR_HSION 0x00000001
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#define RCC_CR_HSIRDY 0x00000002
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#define RCC_CR_HSITRIM 0x000000F8
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#define RCC_CR_HSEON 0x00010000
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#define RCC_CR_HSERDY 0x00020000
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#define RCC_CR_PLLON 0x01000000
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#define RCC_CR_PLLRDY 0x02000000
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#define RCC_CFGR_SWS 0x0000000C
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#define RCC_CFGR_SWS_HSI 0x00000000
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#define RCC_AHBENR_CRCEN 0x0040
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struct FLASH {
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volatile uint32_t ACR;
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volatile uint32_t KEYR;
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volatile uint32_t OPTKEYR;
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volatile uint32_t SR;
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volatile uint32_t CR;
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volatile uint32_t AR;
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volatile uint32_t RESERVED;
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volatile uint32_t OBR;
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volatile uint32_t WRPR;
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};
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#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000)
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static struct FLASH *const FLASH = ((struct FLASH *const) FLASH_R_BASE);
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static void
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clock_init (void)
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{
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/* HSI setup */
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RCC->CR |= RCC_CR_HSION;
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while (!(RCC->CR & RCC_CR_HSIRDY))
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;
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RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION;
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RCC->CFGR = 0;
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
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;
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/* HSE setup */
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RCC->CR |= RCC_CR_HSEON;
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while (!(RCC->CR & RCC_CR_HSERDY))
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;
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/* PLL setup */
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RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC;
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RCC->CR |= RCC_CR_PLLON;
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while (!(RCC->CR & RCC_CR_PLLRDY))
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;
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/* Clock settings */
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RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE
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| STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
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/* Flash setup */
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FLASH->ACR = STM32_FLASHBITS;
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/* CRC */
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RCC->AHBENR |= RCC_AHBENR_CRCEN;
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/* Switching on the configured clock source. */
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RCC->CFGR |= STM32_SW;
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while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
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;
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}
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#define RCC_APB2ENR_IOPAEN 0x00000004
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#define RCC_APB2RSTR_IOPARST 0x00000004
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#define RCC_APB2ENR_IOPBEN 0x00000008
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#define RCC_APB2RSTR_IOPBRST 0x00000008
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#define RCC_APB2ENR_IOPCEN 0x00000010
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#define RCC_APB2RSTR_IOPCRST 0x00000010
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#define RCC_APB2ENR_IOPDEN 0x00000020
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#define RCC_APB2RSTR_IOPDRST 0x00000020
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struct GPIO {
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volatile uint32_t CRL;
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volatile uint32_t CRH;
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volatile uint32_t IDR;
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volatile uint32_t ODR;
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volatile uint32_t BSRR;
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volatile uint32_t BRR;
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volatile uint32_t LCKR;
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};
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#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
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#define GPIOA ((struct GPIO *) GPIOA_BASE)
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#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
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#define GPIOB ((struct GPIO *) GPIOB_BASE)
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#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
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#define GPIOC ((struct GPIO *) GPIOC_BASE)
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#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
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#define GPIOD ((struct GPIO *) GPIOD_BASE)
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#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
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#define GPIOE ((struct GPIO *) GPIOE_BASE)
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static struct GPIO *const GPIO_USB = ((struct GPIO *const) GPIO_USB_BASE);
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static struct GPIO *const GPIO_LED = ((struct GPIO *const) GPIO_LED_BASE);
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static void
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gpio_init (void)
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{
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/* Enable GPIO clock. */
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RCC->APB2ENR |= RCC_APB2ENR_IOP_EN;
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RCC->APB2RSTR = RCC_APB2RSTR_IOP_RST;
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RCC->APB2RSTR = 0;
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GPIO_USB->ODR = VAL_GPIO_ODR;
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GPIO_USB->CRH = VAL_GPIO_CRH;
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GPIO_USB->CRL = VAL_GPIO_CRL;
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#if GPIO_USB_BASE != GPIO_LED_BASE
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GPIO_LED->ODR = VAL_GPIO_LED_ODR;
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GPIO_LED->CRH = VAL_GPIO_LED_CRH;
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GPIO_LED->CRL = VAL_GPIO_LED_CRL;
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#endif
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}
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static void
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usb_cable_config (int enable)
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{
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#if defined(GPIO_USB_SET_TO_ENABLE)
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if (enable)
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GPIO_USB->BSRR = (1 << GPIO_USB_SET_TO_ENABLE);
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else
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GPIO_USB->BRR = (1 << GPIO_USB_SET_TO_ENABLE);
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#elif defined(GPIO_USB_CLEAR_TO_ENABLE)
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if (enable)
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GPIO_USB->BRR = (1 << GPIO_USB_CLEAR_TO_ENABLE);
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else
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GPIO_USB->BSRR = (1 << GPIO_USB_CLEAR_TO_ENABLE);
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#else
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(void)enable;
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#endif
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}
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void
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set_led (int on)
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{
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#if defined(GPIO_LED_CLEAR_TO_EMIT)
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if (on)
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GPIO_LED->BRR = (1 << GPIO_LED_CLEAR_TO_EMIT);
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else
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GPIO_LED->BSRR = (1 << GPIO_LED_CLEAR_TO_EMIT);
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#else
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if (on)
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GPIO_LED->BSRR = (1 << GPIO_LED_SET_TO_EMIT);
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else
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GPIO_LED->BRR = (1 << GPIO_LED_SET_TO_EMIT);
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#endif
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}
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static void wait (int count)
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{
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int i;
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for (i = 0; i < count; i++)
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asm volatile ("" : : "r" (i) : "memory");
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}
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#define USB_IRQ 20
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#define USB_IRQ_PRIORITY ((11) << 4)
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static void
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usb_lld_sys_shutdown (void)
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{
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RCC->APB1ENR &= ~RCC_APB1ENR_USBEN;
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RCC->APB1RSTR = RCC_APB1RSTR_USBRST;
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usb_cable_config (0);
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}
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static void
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usb_lld_sys_init (void)
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{
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if ((RCC->APB1ENR & RCC_APB1ENR_USBEN)
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&& (RCC->APB1RSTR & RCC_APB1RSTR_USBRST) == 0)
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/* Make sure the device is disconnected, even after core reset. */
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{
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usb_lld_sys_shutdown ();
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/* Disconnect requires SE0 (>= 2.5uS). */
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wait (300);
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}
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usb_cable_config (1);
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RCC->APB1ENR |= RCC_APB1ENR_USBEN;
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nvic_enable_vector (USB_LP_CAN1_RX0_IRQn,
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CORTEX_PRIORITY_MASK (STM32_USB_IRQ_PRIORITY));
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/*
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* Note that we also have other IRQ(s):
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* USB_HP_CAN1_TX_IRQn (for double-buffered or isochronous)
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* USBWakeUp_IRQn (suspend/resume)
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*/
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RCC->APB1RSTR = RCC_APB1RSTR_USBRST;
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RCC->APB1RSTR = 0;
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}
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#define FLASH_KEY1 0x45670123UL
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#define FLASH_KEY2 0xCDEF89ABUL
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enum flash_status
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{
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FLASH_BUSY = 1,
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FLASH_ERROR_PG,
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FLASH_ERROR_WRP,
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FLASH_COMPLETE,
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FLASH_TIMEOUT
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};
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static void __attribute__ ((used))
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flash_unlock (void)
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{
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FLASH->KEYR = FLASH_KEY1;
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FLASH->KEYR = FLASH_KEY2;
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}
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#define intr_disable() asm volatile ("cpsid i" : : : "memory")
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#define intr_enable() asm volatile ("cpsie i" : : : "memory")
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#define FLASH_SR_BSY 0x01
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#define FLASH_SR_PGERR 0x04
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#define FLASH_SR_WRPRTERR 0x10
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#define FLASH_SR_EOP 0x20
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#define FLASH_CR_PG 0x0001
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#define FLASH_CR_PER 0x0002
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#define FLASH_CR_MER 0x0004
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#define FLASH_CR_OPTPG 0x0010
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#define FLASH_CR_OPTER 0x0020
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#define FLASH_CR_STRT 0x0040
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#define FLASH_CR_LOCK 0x0080
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#define FLASH_CR_OPTWRE 0x0200
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#define FLASH_CR_ERRIE 0x0400
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#define FLASH_CR_EOPIE 0x1000
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static int
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flash_wait_for_last_operation (uint32_t timeout)
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{
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int status;
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do
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{
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status = FLASH->SR;
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if (--timeout == 0)
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break;
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}
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while ((status & FLASH_SR_BSY) != 0);
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return status & (FLASH_SR_BSY|FLASH_SR_PGERR|FLASH_SR_WRPRTERR);
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}
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#define FLASH_PROGRAM_TIMEOUT 0x00010000
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#define FLASH_ERASE_TIMEOUT 0x01000000
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static int
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flash_program_halfword (uint32_t addr, uint16_t data)
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{
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int status;
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status = flash_wait_for_last_operation (FLASH_PROGRAM_TIMEOUT);
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intr_disable ();
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if (status == 0)
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{
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FLASH->CR |= FLASH_CR_PG;
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*(volatile uint16_t *)addr = data;
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status = flash_wait_for_last_operation (FLASH_PROGRAM_TIMEOUT);
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FLASH->CR &= ~FLASH_CR_PG;
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}
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intr_enable ();
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return status;
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}
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static int
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flash_erase_page (uint32_t addr)
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{
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int status;
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status = flash_wait_for_last_operation (FLASH_ERASE_TIMEOUT);
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intr_disable ();
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if (status == 0)
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{
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FLASH->CR |= FLASH_CR_PER;
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FLASH->AR = addr;
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FLASH->CR |= FLASH_CR_STRT;
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status = flash_wait_for_last_operation (FLASH_ERASE_TIMEOUT);
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FLASH->CR &= ~FLASH_CR_PER;
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}
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intr_enable ();
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return status;
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}
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static int
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flash_check_blank (const uint8_t *p_start, size_t size)
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{
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const uint8_t *p;
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for (p = p_start; p < p_start + size; p++)
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if (*p != 0xff)
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return 0;
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return 1;
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}
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extern uint8_t __flash_start__, __flash_end__;
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static int
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flash_write (uint32_t dst_addr, const uint8_t *src, size_t len)
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{
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int status;
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uint32_t flash_start = (uint32_t)&__flash_start__;
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uint32_t flash_end = (uint32_t)&__flash_end__;
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if (dst_addr < flash_start || dst_addr + len > flash_end)
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return 0;
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while (len)
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{
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uint16_t hw = *src++;
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hw |= (*src++ << 8);
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status = flash_program_halfword (dst_addr, hw);
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if (status != 0)
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return 0; /* error return */
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dst_addr += 2;
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len -= 2;
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}
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return 1;
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}
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#define OPTION_BYTES_ADDR 0x1ffff800
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static int
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flash_protect (void)
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{
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int status;
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uint32_t option_bytes_value;
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status = flash_wait_for_last_operation (FLASH_ERASE_TIMEOUT);
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intr_disable ();
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if (status == 0)
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{
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FLASH->OPTKEYR = FLASH_KEY1;
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FLASH->OPTKEYR = FLASH_KEY2;
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FLASH->CR |= FLASH_CR_OPTER;
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FLASH->CR |= FLASH_CR_STRT;
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status = flash_wait_for_last_operation (FLASH_ERASE_TIMEOUT);
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FLASH->CR &= ~FLASH_CR_OPTER;
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}
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intr_enable ();
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if (status != 0)
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return 0;
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option_bytes_value = *(uint32_t *)OPTION_BYTES_ADDR;
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return (option_bytes_value & 0xff) == 0xff ? 1 : 0;
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}
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static void __attribute__((naked))
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flash_erase_all_and_exec (void (*entry)(void))
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{
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uint32_t addr = (uint32_t)&__flash_start__;
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uint32_t end = (uint32_t)&__flash_end__;
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int r;
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while (addr < end)
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{
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r = flash_erase_page (addr);
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if (r != 0)
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break;
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addr += FLASH_PAGE_SIZE;
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}
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if (addr >= end)
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(*entry) ();
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for (;;);
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}
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struct SCB
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{
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volatile uint32_t CPUID;
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volatile uint32_t ICSR;
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volatile uint32_t VTOR;
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volatile uint32_t AIRCR;
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volatile uint32_t SCR;
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volatile uint32_t CCR;
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volatile uint8_t SHP[12];
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volatile uint32_t SHCSR;
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volatile uint32_t CFSR;
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volatile uint32_t HFSR;
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volatile uint32_t DFSR;
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volatile uint32_t MMFAR;
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volatile uint32_t BFAR;
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volatile uint32_t AFSR;
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volatile uint32_t PFR[2];
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volatile uint32_t DFR;
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volatile uint32_t ADR;
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volatile uint32_t MMFR[4];
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volatile uint32_t ISAR[5];
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};
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#define SCS_BASE (0xE000E000)
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#define SCB_BASE (SCS_BASE + 0x0D00)
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static struct SCB *const SCB = ((struct SCB *const) SCB_BASE);
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#define SYSRESETREQ 0x04
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static void
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nvic_system_reset (void)
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{
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SCB->AIRCR = (0x05FA0000 | (SCB->AIRCR & 0x70) | SYSRESETREQ);
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asm volatile ("dsb");
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for (;;);
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}
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static void __attribute__ ((naked))
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reset (void)
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{
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extern const unsigned long *FT0, *FT1, *FT2;
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asm volatile ("cpsid i\n\t" /* Mask all interrupts. */
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"mov.w r0, #0xed00\n\t" /* r0 = SCR */
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"movt r0, #0xe000\n\t"
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"mov r1, pc\n\t" /* r1 = (PC + 0x1000) & ~0x0fff */
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"mov r2, #0x1000\n\t"
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"add r1, r1, r2\n\t"
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"sub r2, r2, #1\n\t"
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"bic r1, r1, r2\n\t"
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"str r1, [r0, #8]\n\t" /* Set SCR->VCR */
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"ldr r0, [r1], #4\n\t"
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"msr MSP, r0\n\t" /* Main (exception handler) stack. */
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"ldr r0, [r1]\n\t" /* Reset handler. */
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"bx r0\n"
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: /* no output */ : /* no input */ : "memory");
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|
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/* Never reach here. */
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/* Artificial entry to refer FT0, FT1, and FT2. */
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asm volatile (""
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: : "r" (FT0), "r" (FT1), "r" (FT2));
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}
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typedef void (*handler)(void);
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extern uint8_t __ram_end__;
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handler vector[] __attribute__ ((section(".vectors"))) = {
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(handler)&__ram_end__,
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reset,
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(handler)set_led,
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flash_unlock,
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(handler)flash_program_halfword,
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(handler)flash_erase_page,
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(handler)flash_check_blank,
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(handler)flash_write,
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(handler)flash_protect,
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(handler)flash_erase_all_and_exec,
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usb_lld_sys_init,
|
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usb_lld_sys_shutdown,
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nvic_system_reset,
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clock_init,
|
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gpio_init,
|
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NULL,
|
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};
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|
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const uint8_t sys_version[8] __attribute__((section(".sys.version"))) = {
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3*2+2, /* bLength */
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0x03, /* bDescriptorType = USB_STRING_DESCRIPTOR_TYPE*/
|
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/* sys version: "2.0" */
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'2', 0, '.', 0, '0', 0,
|
|
};
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