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https://salsa.debian.org/gnuk-team/gnuk/gnuk.git
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213 lines
8.2 KiB
C
213 lines
8.2 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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---
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A special exception to the GPL can be applied should you wish to distribute
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a combined work that includes ChibiOS/RT, without being obliged to provide
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the source code for any proprietary components. See the file exception.txt
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for full details of how and when the exception can be applied.
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*/
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/**
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* @file STM32/hal_lld.c
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* @brief STM32 HAL subsystem low level driver source.
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*
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* @addtogroup STM32_HAL
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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#define AIRCR_VECTKEY 0x05FA0000
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables. */
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/*===========================================================================*/
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/**
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* @brief PAL setup.
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* @details Digital I/O ports static configuration as defined in @p board.h.
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*/
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const PALConfig pal_default_config =
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{
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{VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
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{VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
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{VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
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{VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
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#if !defined(STM32F10X_LD) && !defined(BOARD_STBEE_MINI)
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{VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},
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#endif
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#if defined(STM32F10X_HD)
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{VAL_GPIOFODR, VAL_GPIOFCRL, VAL_GPIOFCRH},
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{VAL_GPIOGODR, VAL_GPIOGCRL, VAL_GPIOGCRH},
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#endif
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};
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level HAL driver initialization.
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*/
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void hal_lld_init(void) {
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/* SysTick initialization using the system clock.*/
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SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1;
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SysTick->VAL = 0;
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SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
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SysTick_CTRL_ENABLE_Msk |
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SysTick_CTRL_TICKINT_Msk;
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#if CH_HAL_USE_ADC || CH_HAL_USE_SPI
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dmaInit();
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#endif
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}
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/**
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* @brief STM32 clocks and PLL initialization.
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* @note All the involved constants come from the file @p board.h.
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*/
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#if defined(STM32F10X_LD) || defined(STM32F10X_MD) || \
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defined(STM32F10X_HD) || defined(__DOXYGEN__)
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/*
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* Clocks initialization for the LD, MD and HD sub-families.
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*/
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void stm32_clock_init(void) {
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/* HSI setup, it enforces the reset situation in order to handle possible
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problems with JTAG probes and re-initializations.*/
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RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */
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while (!(RCC->CR & RCC_CR_HSIRDY))
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; /* Wait until HSI is stable. */
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RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */
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RCC->CFGR = 0; /* CFGR reset value. */
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
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; /* Wait until HSI is the source.*/
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/* HSE setup, it is only performed if the HSE clock is selected as source
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of the system clock (directly or through the PLL).*/
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#if (STM32_SW == STM32_SW_HSE) || \
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((STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE))
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RCC->CR |= RCC_CR_HSEON;
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while (!(RCC->CR & RCC_CR_HSERDY))
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; /* Waits until HSE is stable. */
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#endif
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/* PLL setup, it is only performed if the PLL is the selected source of
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the system clock else it is left disabled.*/
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#if STM32_SW == STM32_SW_PLL
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RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC;
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RCC->CR |= RCC_CR_PLLON;
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while (!(RCC->CR & RCC_CR_PLLRDY))
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; /* Waits until PLL is stable. */
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#endif
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/* Clock settings.*/
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RCC->CFGR = STM32_MCO | STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC |
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STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
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/* Flash setup and final clock selection. */
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FLASH->ACR = STM32_FLASHBITS; /* Flash wait states depending on clock. */
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/* Switching on the configured clock source if it is different from HSI.*/
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#if (STM32_SW != STM32_SW_HSI)
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RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
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while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
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;
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#endif
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}
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#elif defined(STM32F10X_CL)
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/*
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* Clocks initialization for the CL sub-family.
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*/
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void stm32_clock_init(void) {
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/* HSI setup, it enforces the reset situation in order to handle possible
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problems with JTAG probes and re-initializations.*/
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RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */
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while (!(RCC->CR & RCC_CR_HSIRDY))
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; /* Wait until HSI is stable. */
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RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */
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RCC->CFGR = 0; /* CFGR reset value. */
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
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; /* Wait until HSI is the source.*/
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RCC->CFGR2 = 0;
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/* HSE setup, it is only performed if the HSE clock is selected as source
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of the system clock (directly or through the PLLs).*/
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#if (STM32_SW == STM32_SW_HSE) || \
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((STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_PREDIV1))
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RCC->CR |= RCC_CR_HSEON;
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while (!(RCC->CR & RCC_CR_HSERDY))
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; /* Waits until HSE is stable. */
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#endif
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/* PLL2 setup, it is only performed if the PLL2 clock is selected as source
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for the PLL clock else it is left disabled.*/
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#if STM32_SW == STM32_SW_PLL
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#if STM32_PREDIV1SRC == STM32_PREDIV1SRC_PLL2
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RCC->CFGR2 |= STM32_PREDIV2 | STM32_PLL2MUL;
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RCC->CR |= RCC_CR_PLL2ON;
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while (!(RCC->CR & RCC_CR_PLL2RDY))
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; /* Waits until PLL is stable. */
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#endif
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/* PLL setup, it is only performed if the PLL is the selected source of
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the system clock else it is left disabled.*/
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RCC->CFGR2 |= STM32_PREDIV1 | STM32_PREDIV1SRC;
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RCC->CFGR |= STM32_PLLMUL | STM32_PLLSRC;
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RCC->CR |= RCC_CR_PLLON;
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while (!(RCC->CR & RCC_CR_PLLRDY))
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; /* Waits until PLL2 is stable. */
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#endif
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/* Clock settings.*/
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RCC->CFGR = STM32_MCO | STM32_PLLMUL | STM32_PLLSRC |
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STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
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/* Flash setup and final clock selection. */
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FLASH->ACR = STM32_FLASHBITS; /* Flash wait states depending on clock. */
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/* Switching on the configured clock source if it is different from HSI.*/
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#if (STM32_SW != STM32_SW_HSI)
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RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
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while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
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;
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#endif
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}
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#else
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void stm32_clock_init(void) {}
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#endif
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/** @} */
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