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127 lines
3.5 KiB
ArmAsm
127 lines
3.5 KiB
ArmAsm
/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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---
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A special exception to the GPL can be applied should you wish to distribute
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a combined work that includes ChibiOS/RT, without being obliged to provide
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the source code for any proprietary components. See the file exception.txt
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for full details of how and when the exception can be applied.
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*/
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/**
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* @file PPC/crt0.s
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* @brief Generic PowerPC startup file for ChibiOS/RT.
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*
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* @addtogroup PPC_CORE
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* @{
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*/
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/** @cond never */
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.section .text
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.align 2
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.globl _boot_address
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_boot_address:
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/*
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* Stack setup.
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*/
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lis %r1, __ram_end__@h
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ori %r1, %r1, __ram_end__@l
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li %r0, 0
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stwu %r0, -8(%r1)
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/*
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* IVPR initialization.
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*/
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lis %r4, __ivpr_base__@h
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mtIVPR %r4
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/*
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* Small sections registers initialization.
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*/
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lis %r2, __sdata2_start__@h
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ori %r2, %r2, __sdata2_start__@l
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lis %r13, __sdata_start__@h
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ori %r13, %r13, __sdata_start__@l
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/*
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* Early initialization.
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*/
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bl hwinit0
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/*
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* BSS clearing.
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*/
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lis %r4, __bss_start__@h
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ori %r4, %r4, __bss_start__@l
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lis %r5, __bss_end__@h
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ori %r5, %r5, __bss_end__@l
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li %r7, 0
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.bssloop:
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cmpl cr0, %r4, %r5
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bge cr0, .bssend
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stw %r7, 0(%r4)
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addi %r4, %r4, 4
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b .bssloop
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.bssend:
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/*
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* DATA initialization.
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*/
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lis %r4, __romdata_start__@h
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ori %r4, %r4, __romdata_start__@l
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lis %r5, __data_start__@h
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ori %r5, %r5, __data_start__@l
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lis %r6, __data_end__@h
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ori %r6, %r6, __data_end__@l
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.dataloop:
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cmpl cr0, %r5, %r6
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bge cr0, .dataend
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lwz %r7, 0(%r4)
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addi %r4, %r4, 4
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stw %r7, 0(%r5)
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addi %r5, %r5, 4
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b .dataloop
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.dataend:
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/*
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* Late initialization.
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*/
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bl hwinit1
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li %r3, 0
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li %r4, 0
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bl main
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b main_exit
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/*
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* Default main exit code, infinite loop.
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*/
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.weak main_exit
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.globl main_exit
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main_exit:
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forever:
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b forever
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/*
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* Default initialization code, none.
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*/
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.weak hwinit0
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.globl hwinit0
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hwinit0:
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.weak hwinit1
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.globl hwinit1
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hwinit1:
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blr
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/** @endcond */
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/** @} */
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