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<td><big><big>ChibiOS/RT</big></big><br><br>Architecture - Reference Manual - Guides</td>
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<li><a href="annotated.html"><span>Data Structures</span></a></li>
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<h1>mpc563m.h</h1><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/**************************************************************************/</span>
|
||
<a name="l00002"></a>00002
|
||
<a name="l00003"></a>00003 <span class="comment">/* FILE NAME: mpc563xm.h COPYRIGHT (c) Freescale 2008,2009 */</span>
|
||
<a name="l00004"></a>00004 <span class="comment">/* VERSION: 2.0 All Rights Reserved */</span>
|
||
<a name="l00005"></a>00005 <span class="comment">/* */</span>
|
||
<a name="l00006"></a>00006 <span class="comment">/* DESCRIPTION: */</span>
|
||
<a name="l00007"></a>00007 <span class="comment">/* This file contain all of the register and bit field definitions for */</span>
|
||
<a name="l00008"></a>00008 <span class="comment">/* MPC563xM. This version supports revision 1.0 and later. */</span>
|
||
<a name="l00009"></a>00009 <span class="comment">/*========================================================================*/</span>
|
||
<a name="l00010"></a>00010 <span class="comment">/* UPDATE HISTORY */</span>
|
||
<a name="l00011"></a>00011 <span class="comment">/* REV AUTHOR DATE DESCRIPTION OF CHANGE */</span>
|
||
<a name="l00012"></a>00012 <span class="comment">/* --- ----------- --------- --------------------- */</span>
|
||
<a name="l00013"></a>00013 <span class="comment">/* 1.0 G. Emerson 31/OCT/07 Initial version. */</span>
|
||
<a name="l00014"></a>00014 <span class="comment">/* 1.1 G. Emerson 20/DEC/07 Added SYSDIV HLT HLTACK */</span>
|
||
<a name="l00015"></a>00015 <span class="comment">/* Added ESYNCR1 ESYNCR2 SYNFMMR */</span>
|
||
<a name="l00016"></a>00016 <span class="comment">/* 1.2 G. Emerson 31/JAN/08 Change eMIOS channels so there are 24. */</span>
|
||
<a name="l00017"></a>00017 <span class="comment">/* 8 channels in the middle of the range */</span>
|
||
<a name="l00018"></a>00018 <span class="comment">/* do not exist */</span>
|
||
<a name="l00019"></a>00019 <span class="comment">/* 1.3 G. Emerson 30/JUL/08 FLEXCAN - Supports FIFO and Buffer. */</span>
|
||
<a name="l00020"></a>00020 <span class="comment">/* RXIMR added */</span>
|
||
<a name="l00021"></a>00021 <span class="comment">/* FMPLL - Added FMPLL.SYNFMMR.B.BSY */</span>
|
||
<a name="l00022"></a>00022 <span class="comment">/* SIU - Added SIU.ISEL0-3 */</span>
|
||
<a name="l00023"></a>00023 <span class="comment">/* EMIOS - Added EMIOS.CH[x].ALTCADR.R */</span>
|
||
<a name="l00024"></a>00024 <span class="comment">/* MCM - Replaced ECSM with MCM */</span>
|
||
<a name="l00025"></a>00025 <span class="comment">/* removing SWT registers as defined at */</span>
|
||
<a name="l00026"></a>00026 <span class="comment">/* seperate memory location. PFLASH */</span>
|
||
<a name="l00027"></a>00027 <span class="comment">/* registers pre-fixed with P*. Added PCT,*/</span>
|
||
<a name="l00028"></a>00028 <span class="comment">/* PLREV, PLAMC, PLASC, IOPMC, MRSR, MWCR.*/</span>
|
||
<a name="l00029"></a>00029 <span class="comment">/* PBRIDGE - Removed as no PBRIDGE */</span>
|
||
<a name="l00030"></a>00030 <span class="comment">/* registers. */</span>
|
||
<a name="l00031"></a>00031 <span class="comment">/* INTC - Updated number of PSR from */</span>
|
||
<a name="l00032"></a>00032 <span class="comment">/* 358 to 360. */</span>
|
||
<a name="l00033"></a>00033 <span class="comment">/* mpc5500_spr.h - Added RI to MSR and NMI*/</span>
|
||
<a name="l00034"></a>00034 <span class="comment">/* to MSCR. */</span>
|
||
<a name="l00035"></a>00035 <span class="comment">/* 1.4 G. Emerson 30/SEP/08 Add SIU.MIDR2 */</span>
|
||
<a name="l00036"></a>00036 <span class="comment">/* Changes to SIU.MIDR as per RM. */</span>
|
||
<a name="l00037"></a>00037 <span class="comment">/* 1.5 May 2009 Changes to match documentation, removed*/</span>
|
||
<a name="l00038"></a>00038 <span class="comment">/* Not released */</span>
|
||
<a name="l00039"></a>00039 <span class="comment">/* 1.6 K. Odenthal 03/June/09 Update for 1.5M version of the MPC563xM*/</span>
|
||
<a name="l00040"></a>00040 <span class="comment">/* & R. Dees */</span>
|
||
<a name="l00041"></a>00041 <span class="comment">/* INTC - All Processor 0 regs matched to previous */</span>
|
||
<a name="l00042"></a>00042 <span class="comment">/* version */</span>
|
||
<a name="l00043"></a>00043 <span class="comment">/* INTC - BCR renamed to MCR to match previous */</span>
|
||
<a name="l00044"></a>00044 <span class="comment">/* version */</span>
|
||
<a name="l00045"></a>00045 <span class="comment">/* INTC - VTES_PRC1 and HVEN_PRC1 added to MCR */</span>
|
||
<a name="l00046"></a>00046 <span class="comment">/* INTC - CPR_PRC1, IACKR_PRC1 and EOIR_PRC1 */</span>
|
||
<a name="l00047"></a>00047 <span class="comment">/* registers added */</span>
|
||
<a name="l00048"></a>00048 <span class="comment">/* INTC - 512 PSR registers instead of 364 */</span>
|
||
<a name="l00049"></a>00049 <span class="comment">/* ECSM - (Internal - mcm -> ecsm in the source files*/</span>
|
||
<a name="l00050"></a>00050 <span class="comment">/* for generating the header file */</span>
|
||
<a name="l00051"></a>00051 <span class="comment">/* ECSM - All bits and regs got an additional "p" in */</span>
|
||
<a name="l00052"></a>00052 <span class="comment">/* the name in the user manual for "Platform" */</span>
|
||
<a name="l00053"></a>00053 <span class="comment">/* -> deleted to match */</span>
|
||
<a name="l00054"></a>00054 <span class="comment">/* ECSM - SWTCR, SWTSR and SWTIR don't exist in */</span>
|
||
<a name="l00055"></a>00055 <span class="comment">/* MPC563xM -> deleted */</span>
|
||
<a name="l00056"></a>00056 <span class="comment">/* ECSM - PROTECTION in the URM is one bitfield, */</span>
|
||
<a name="l00057"></a>00057 <span class="comment">/* in mop5534 this are four: PROT1-4 -> */</span>
|
||
<a name="l00058"></a>00058 <span class="comment">/* changed to match */</span>
|
||
<a name="l00059"></a>00059 <span class="comment">/* EMCM - removed undocumented registers */</span>
|
||
<a name="l00060"></a>00060 <span class="comment">/* ECSM - RAM ECC Syndrome is new in MPC563xM -> added */</span>
|
||
<a name="l00061"></a>00061 <span class="comment">/* XBAR - removed AMPR and ASGPCR registers */</span>
|
||
<a name="l00062"></a>00062 <span class="comment">/* XBAR - removed HPE bits for nonexistant masters */</span>
|
||
<a name="l00063"></a>00063 <span class="comment">/* EBI - added: D16_31, AD_MUX and SETA bits */</span>
|
||
<a name="l00064"></a>00064 <span class="comment">/* EBI - Added reserved register at address 0x4. */</span>
|
||
<a name="l00065"></a>00065 <span class="comment">/* EBI - Corrected number of chip selects in for both*/</span>
|
||
<a name="l00066"></a>00066 <span class="comment">/* the EBI_CS and the CAL_EBI_CS */</span>
|
||
<a name="l00067"></a>00067 <span class="comment">/* SIU - corrected number of GPDO registers and */</span>
|
||
<a name="l00068"></a>00068 <span class="comment">/* allowed for maximum PCR registers. */</span>
|
||
<a name="l00069"></a>00069 <span class="comment">/* SWT - add KEY bit to CR, correct WND (from WNO) */</span>
|
||
<a name="l00070"></a>00070 <span class="comment">/* SWT - add SK register */</span>
|
||
<a name="l00071"></a>00071 <span class="comment">/* PMC - moved bits from CFGR to Status Register (SR)*/</span>
|
||
<a name="l00072"></a>00072 <span class="comment">/* PMC - Added SR */</span>
|
||
<a name="l00073"></a>00073 <span class="comment">/* DECFIL - Added new bits DSEL, IBIE, OBIE, EDME, */</span>
|
||
<a name="l00074"></a>00074 <span class="comment">/* TORE, & TRFE to MCR. Added IBIC, OBIC, */</span>
|
||
<a name="l00075"></a>00075 <span class="comment">/* DIVRC, IBIF, OBIF, DIVR to MSR. */</span>
|
||
<a name="l00076"></a>00076 <span class="comment">/* changed OUTTEG to OUTTAG in OB */</span>
|
||
<a name="l00077"></a>00077 <span class="comment">/* Change COEF to TAG in TAG register */</span>
|
||
<a name="l00078"></a>00078 <span class="comment">/* EQADC - removed REDLCCR - not supported */</span>
|
||
<a name="l00079"></a>00079 <span class="comment">/* FLASH - Aligned register and bit names with legacy*/</span>
|
||
<a name="l00080"></a>00080 <span class="comment">/* 1.7 K. Odenthal 10/November/09 */</span>
|
||
<a name="l00081"></a>00081 <span class="comment">/* SIU - changed PCR[n].PA from 3 bit to 4 bit */</span>
|
||
<a name="l00082"></a>00082 <span class="comment">/* eTPU - changed WDTR_A.WDM from 1 bit to 2 bits */</span>
|
||
<a name="l00083"></a>00083 <span class="comment">/* DECFIL - changed COEF.R and TAP.R from 16 bit to */</span>
|
||
<a name="l00084"></a>00084 <span class="comment">/* 32 bit */</span>
|
||
<a name="l00085"></a>00085 <span class="comment">/* 2.0 K. Odenthal 12/February/2010 */</span>
|
||
<a name="l00086"></a>00086 <span class="comment">/* TSENS - Temperature Sensor Module added to */</span>
|
||
<a name="l00087"></a>00087 <span class="comment">/* header file */</span>
|
||
<a name="l00088"></a>00088 <span class="comment">/* ANSI C Compliance - Register structures have a */</span>
|
||
<a name="l00089"></a>00089 <span class="comment">/* Bitfield Tag ('B') tag only if there is */</span>
|
||
<a name="l00090"></a>00090 <span class="comment">/* at least one Bitfiels defined. Empty */</span>
|
||
<a name="l00091"></a>00091 <span class="comment">/* tags like 'vuint32_t:32;' are not */</span>
|
||
<a name="l00092"></a>00092 <span class="comment">/* allowed. */</span>
|
||
<a name="l00093"></a>00093 <span class="comment">/* DECFIL - removed MXCR register. This register is */</span>
|
||
<a name="l00094"></a>00094 <span class="comment">/* not supported on this part */</span>
|
||
<a name="l00095"></a>00095 <span class="comment">/* SIU - SWT_SEL bit added in SIU DIRER register */</span>
|
||
<a name="l00096"></a>00096 <span class="comment">/* EDMA - removed HRSL, HRSH and GPOR registers. */</span>
|
||
<a name="l00097"></a>00097 <span class="comment">/* Those registers are not supported in */</span>
|
||
<a name="l00098"></a>00098 <span class="comment">/* that part. */</span>
|
||
<a name="l00099"></a>00099 <span class="comment">/* ESCI - removed LDBG and DSF bits from LCR */</span>
|
||
<a name="l00100"></a>00100 <span class="comment">/* registers. Those bits are not supported */</span>
|
||
<a name="l00101"></a>00101 <span class="comment">/* in that part. */</span>
|
||
<a name="l00102"></a>00102 <span class="comment">/* Those registers are not supported in */</span>
|
||
<a name="l00103"></a>00103 <span class="comment">/* that part. */</span>
|
||
<a name="l00104"></a>00104 <span class="comment">/**************************************************************************/</span>
|
||
<a name="l00105"></a>00105 <span class="comment">/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/</span>
|
||
<a name="l00106"></a>00106
|
||
<a name="l00107"></a>00107 <span class="preprocessor">#ifndef _MPC563M_H_</span>
|
||
<a name="l00108"></a>00108 <span class="preprocessor"></span><span class="preprocessor">#define _MPC563M_H_</span>
|
||
<a name="l00109"></a>00109 <span class="preprocessor"></span>
|
||
<a name="l00110"></a>00110 <span class="preprocessor">#include "<a class="code" href="typedefs_8h.html" title="Dummy typedefs file.">typedefs.h</a>"</span>
|
||
<a name="l00111"></a>00111
|
||
<a name="l00112"></a>00112 <span class="preprocessor">#ifdef __cplusplus</span>
|
||
<a name="l00113"></a>00113 <span class="preprocessor"></span><span class="keyword">extern</span> <span class="stringliteral">"C"</span> {
|
||
<a name="l00114"></a>00114
|
||
<a name="l00115"></a>00115 <span class="preprocessor">#endif </span><span class="comment">/* </span>
|
||
<a name="l00116"></a>00116 <span class="comment"> */</span>
|
||
<a name="l00117"></a>00117
|
||
<a name="l00118"></a>00118 <span class="preprocessor">#ifdef __MWERKS__</span>
|
||
<a name="l00119"></a>00119 <span class="preprocessor"></span><span class="preprocessor">#pragma push</span>
|
||
<a name="l00120"></a>00120 <span class="preprocessor"></span><span class="preprocessor">#pragma ANSI_strict off</span>
|
||
<a name="l00121"></a>00121 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/* </span>
|
||
<a name="l00122"></a>00122 <span class="comment"> */</span>
|
||
<a name="l00123"></a>00123
|
||
<a name="l00124"></a>00124 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l00125"></a>00125 <span class="comment">/* MODULE : FMPLL */</span>
|
||
<a name="l00126"></a>00126 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l00127"></a>00127 <span class="keyword">struct </span>FMPLL_tag {
|
||
<a name="l00128"></a>00128 <span class="keyword">union </span>{
|
||
<a name="l00129"></a>00129 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00130"></a>00130 <span class="keyword">struct </span>{
|
||
<a name="l00131"></a>00131 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1;
|
||
<a name="l00132"></a>00132 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PREDIV:3;
|
||
<a name="l00133"></a>00133 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MFD:5;
|
||
<a name="l00134"></a>00134 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1;
|
||
<a name="l00135"></a>00135 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RFD:3;
|
||
<a name="l00136"></a>00136 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LOCEN:1;
|
||
<a name="l00137"></a>00137 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LOLRE:1;
|
||
<a name="l00138"></a>00138 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LOCRE:1;
|
||
<a name="l00139"></a>00139 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* Reserved in MPC563xM </span>
|
||
<a name="l00140"></a>00140 <span class="comment"></span>
|
||
<a name="l00141"></a>00141 <span class="comment"> Deleted for legacy header version [mpc5534.h]: </span>
|
||
<a name="l00142"></a>00142 <span class="comment"></span>
|
||
<a name="l00143"></a>00143 <span class="comment"> <vuint32_t DISCLK:1> */</span>
|
||
<a name="l00144"></a>00144 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LOLIRQ:1;
|
||
<a name="l00145"></a>00145 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LOCIRQ:1;
|
||
<a name="l00146"></a>00146 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:13; <span class="comment">/* Reserved in MPC563xM </span>
|
||
<a name="l00147"></a>00147 <span class="comment"></span>
|
||
<a name="l00148"></a>00148 <span class="comment"> Deleted for legacy header version [mpc5534.h]:</span>
|
||
<a name="l00149"></a>00149 <span class="comment"></span>
|
||
<a name="l00150"></a>00150 <span class="comment"> <vuint32_t RATE:1 > </span>
|
||
<a name="l00151"></a>00151 <span class="comment"></span>
|
||
<a name="l00152"></a>00152 <span class="comment"> <vuint32_t DEPTH:2></span>
|
||
<a name="l00153"></a>00153 <span class="comment"></span>
|
||
<a name="l00154"></a>00154 <span class="comment"> <vuint32_t EXP:10 > */</span>
|
||
<a name="l00155"></a>00155 } B;
|
||
<a name="l00156"></a>00156 } SYNCR;
|
||
<a name="l00157"></a>00157 <span class="keyword">union </span>{
|
||
<a name="l00158"></a>00158 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00159"></a>00159 <span class="keyword">struct </span>{
|
||
<a name="l00160"></a>00160 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:22;
|
||
<a name="l00161"></a>00161 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LOLF:1;
|
||
<a name="l00162"></a>00162 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LOC:1;
|
||
<a name="l00163"></a>00163 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MODE:1;
|
||
<a name="l00164"></a>00164 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PLLSEL:1;
|
||
<a name="l00165"></a>00165 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PLLREF:1;
|
||
<a name="l00166"></a>00166 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LOCKS:1;
|
||
<a name="l00167"></a>00167 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LOCK:1;
|
||
<a name="l00168"></a>00168 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LOCF:1;
|
||
<a name="l00169"></a>00169 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:2; <span class="comment">/* Reserved in MPC563xM</span>
|
||
<a name="l00170"></a>00170 <span class="comment"></span>
|
||
<a name="l00171"></a>00171 <span class="comment"> Deleted for legacy header version [mpc5534.h]:</span>
|
||
<a name="l00172"></a>00172 <span class="comment"></span>
|
||
<a name="l00173"></a>00173 <span class="comment"> <vuint32_t CALDONE:1></span>
|
||
<a name="l00174"></a>00174 <span class="comment"></span>
|
||
<a name="l00175"></a>00175 <span class="comment"> <vuint32_t CALPASS:1> */</span>
|
||
<a name="l00176"></a>00176 } B;
|
||
<a name="l00177"></a>00177 } SYNSR;
|
||
<a name="l00178"></a>00178 <span class="keyword">union </span>{
|
||
<a name="l00179"></a>00179 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00180"></a>00180 <span class="keyword">struct </span>{
|
||
<a name="l00181"></a>00181 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EMODE:1;
|
||
<a name="l00182"></a>00182 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CLKCFG:3;
|
||
<a name="l00183"></a>00183 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:8;
|
||
<a name="l00184"></a>00184 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EPREDIV:4;
|
||
<a name="l00185"></a>00185 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:9;
|
||
<a name="l00186"></a>00186 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EMFD:7;
|
||
<a name="l00187"></a>00187 } B;
|
||
<a name="l00188"></a>00188 } ESYNCR1; <span class="comment">/* Enhanced Synthesizer Control Register 1 (ESYNCR1) (new in MPC563xM) Offset 0x0008 */</span>
|
||
<a name="l00189"></a>00189 <span class="keyword">union </span>{
|
||
<a name="l00190"></a>00190 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00191"></a>00191 <span class="keyword">struct </span>{
|
||
<a name="l00192"></a>00192 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:8;
|
||
<a name="l00193"></a>00193 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LOCEN:1;
|
||
<a name="l00194"></a>00194 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LOLRE:1;
|
||
<a name="l00195"></a>00195 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LOCRE:1;
|
||
<a name="l00196"></a>00196 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LOLIRQ:1;
|
||
<a name="l00197"></a>00197 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LOCIRQ:1;
|
||
<a name="l00198"></a>00198 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:17;
|
||
<a name="l00199"></a>00199 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERFD:2;
|
||
<a name="l00200"></a>00200 } B;
|
||
<a name="l00201"></a>00201 } ESYNCR2; <span class="comment">/* Enhanced Synthesizer Control Register 2 (ESYNCR2) (new in MPC563xM) Offset 0x000C */</span>
|
||
<a name="l00202"></a>00202 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> FMPLL_reserved0[2];
|
||
<a name="l00203"></a>00203 <span class="keyword">union </span>{
|
||
<a name="l00204"></a>00204 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00205"></a>00205 <span class="keyword">struct </span>{
|
||
<a name="l00206"></a>00206 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BSY:1;
|
||
<a name="l00207"></a>00207 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MODEN:1;
|
||
<a name="l00208"></a>00208 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MODSEL:1;
|
||
<a name="l00209"></a>00209 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MODPERIOD:13;
|
||
<a name="l00210"></a>00210 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1;
|
||
<a name="l00211"></a>00211 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> INCSTEP:15;
|
||
<a name="l00212"></a>00212 } B;
|
||
<a name="l00213"></a>00213 } SYNFMMR; <span class="comment">/* Synthesizer FM Modulation Register (SYNFMMR) (new in MPC563xM) Offset 0x0018 */</span>
|
||
<a name="l00214"></a>00214 };
|
||
<a name="l00215"></a>00215 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l00216"></a>00216 <span class="comment">/* MODULE : EBI */</span>
|
||
<a name="l00217"></a>00217 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l00218"></a>00218 <span class="keyword">struct </span>CS_tag {
|
||
<a name="l00219"></a>00219 <span class="keyword">union </span>{
|
||
<a name="l00220"></a>00220 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00221"></a>00221 <span class="keyword">struct </span>{
|
||
<a name="l00222"></a>00222 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BA:17; <span class="comment">/* */</span>
|
||
<a name="l00223"></a>00223 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:3; <span class="comment">/* */</span>
|
||
<a name="l00224"></a>00224 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PS:1; <span class="comment">/* */</span>
|
||
<a name="l00225"></a>00225 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:3; <span class="comment">/* */</span>
|
||
<a name="l00226"></a>00226 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> AD_MUX:1; <span class="comment">/* new in MPC563xM */</span>
|
||
<a name="l00227"></a>00227 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BL:1; <span class="comment">/* */</span>
|
||
<a name="l00228"></a>00228 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WEBS:1; <span class="comment">/* */</span>
|
||
<a name="l00229"></a>00229 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TBDIP:1; <span class="comment">/* */</span>
|
||
<a name="l00230"></a>00230 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* */</span>
|
||
<a name="l00231"></a>00231 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SETA:1; <span class="comment">/* new in MPC563xM */</span>
|
||
<a name="l00232"></a>00232 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BI:1; <span class="comment">/* */</span>
|
||
<a name="l00233"></a>00233 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> V:1; <span class="comment">/* */</span>
|
||
<a name="l00234"></a>00234 } B;
|
||
<a name="l00235"></a>00235 } BR; <span class="comment">/* <URM>EBI_BR</URM> */</span>
|
||
<a name="l00236"></a>00236 <span class="keyword">union </span>{
|
||
<a name="l00237"></a>00237 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00238"></a>00238 <span class="keyword">struct </span>{
|
||
<a name="l00239"></a>00239 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> AM:17; <span class="comment">/* */</span>
|
||
<a name="l00240"></a>00240 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:7; <span class="comment">/* */</span>
|
||
<a name="l00241"></a>00241 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SCY:4; <span class="comment">/* */</span>
|
||
<a name="l00242"></a>00242 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* */</span>
|
||
<a name="l00243"></a>00243 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BSCY:2; <span class="comment">/* */</span>
|
||
<a name="l00244"></a>00244 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* */</span>
|
||
<a name="l00245"></a>00245 } B;
|
||
<a name="l00246"></a>00246 } OR; <span class="comment">/* <URM>EBI_OR</URM> */</span>
|
||
<a name="l00247"></a>00247 };
|
||
<a name="l00248"></a>00248 <span class="keyword">struct </span>CAL_CS_tag {
|
||
<a name="l00249"></a>00249 <span class="keyword">union </span>{
|
||
<a name="l00250"></a>00250 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00251"></a>00251 <span class="keyword">struct </span>{
|
||
<a name="l00252"></a>00252 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BA:17; <span class="comment">/* */</span>
|
||
<a name="l00253"></a>00253 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:3; <span class="comment">/* */</span>
|
||
<a name="l00254"></a>00254 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PS:1; <span class="comment">/* */</span>
|
||
<a name="l00255"></a>00255 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:3; <span class="comment">/* */</span>
|
||
<a name="l00256"></a>00256 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> AD_MUX:1; <span class="comment">/* new in MPC563xM */</span>
|
||
<a name="l00257"></a>00257 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BL:1; <span class="comment">/* */</span>
|
||
<a name="l00258"></a>00258 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WEBS:1; <span class="comment">/* */</span>
|
||
<a name="l00259"></a>00259 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TBDIP:1; <span class="comment">/* */</span>
|
||
<a name="l00260"></a>00260 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* */</span>
|
||
<a name="l00261"></a>00261 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SETA:1; <span class="comment">/* new in MPC563xM */</span>
|
||
<a name="l00262"></a>00262 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BI:1; <span class="comment">/* */</span>
|
||
<a name="l00263"></a>00263 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> V:1; <span class="comment">/* */</span>
|
||
<a name="l00264"></a>00264 } B;
|
||
<a name="l00265"></a>00265 } BR; <span class="comment">/* <URM>EBI_CAL_BR</URM> */</span>
|
||
<a name="l00266"></a>00266
|
||
<a name="l00267"></a>00267 <span class="keyword">union </span>{
|
||
<a name="l00268"></a>00268 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00269"></a>00269 <span class="keyword">struct </span>{
|
||
<a name="l00270"></a>00270 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> AM:17; <span class="comment">/* */</span>
|
||
<a name="l00271"></a>00271 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:7; <span class="comment">/* */</span>
|
||
<a name="l00272"></a>00272 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SCY:4; <span class="comment">/* */</span>
|
||
<a name="l00273"></a>00273 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* */</span>
|
||
<a name="l00274"></a>00274 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BSCY:2; <span class="comment">/* */</span>
|
||
<a name="l00275"></a>00275 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* */</span>
|
||
<a name="l00276"></a>00276 } B;
|
||
<a name="l00277"></a>00277 } OR; <span class="comment">/* <URM>EBI_CAL_OR</URM> */</span>
|
||
<a name="l00278"></a>00278
|
||
<a name="l00279"></a>00279 };
|
||
<a name="l00280"></a>00280
|
||
<a name="l00281"></a>00281 <span class="keyword">struct </span>EBI_tag {
|
||
<a name="l00282"></a>00282 <span class="keyword">union </span>{
|
||
<a name="l00283"></a>00283 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00284"></a>00284 <span class="keyword">struct </span>{
|
||
<a name="l00285"></a>00285 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:5; <span class="comment">/* */</span>
|
||
<a name="l00286"></a>00286 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SIZEEN:1; <span class="comment">/* <URM>SIZEN</URM> */</span>
|
||
<a name="l00287"></a>00287 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SIZE:2; <span class="comment">/* */</span>
|
||
<a name="l00288"></a>00288 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:8; <span class="comment">/* */</span>
|
||
<a name="l00289"></a>00289 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ACGE:1; <span class="comment">/* */</span>
|
||
<a name="l00290"></a>00290 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EXTM:1; <span class="comment">/* */</span>
|
||
<a name="l00291"></a>00291 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EARB:1; <span class="comment">/* */</span>
|
||
<a name="l00292"></a>00292 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EARP:2; <span class="comment">/* */</span>
|
||
<a name="l00293"></a>00293 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:4; <span class="comment">/* */</span>
|
||
<a name="l00294"></a>00294 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MDIS:1; <span class="comment">/* */</span>
|
||
<a name="l00295"></a>00295 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:3; <span class="comment">/* */</span>
|
||
<a name="l00296"></a>00296 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> D16_31:1; <span class="comment">/* new in MPC563xM */</span>
|
||
<a name="l00297"></a>00297 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> AD_MUX:1; <span class="comment">/* new in MPC563xM */</span>
|
||
<a name="l00298"></a>00298 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DBM:1; <span class="comment">/* */</span>
|
||
<a name="l00299"></a>00299 } B;
|
||
<a name="l00300"></a>00300 } MCR; <span class="comment">/* EBI Module Configuration Register (MCR) <URM>EBI_MCR</URM> @baseaddress + 0x00 */</span>
|
||
<a name="l00301"></a>00301
|
||
<a name="l00302"></a>00302 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> EBI_reserved1[1];
|
||
<a name="l00303"></a>00303
|
||
<a name="l00304"></a>00304 <span class="keyword">union </span>{
|
||
<a name="l00305"></a>00305 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00306"></a>00306 <span class="keyword">struct </span>{
|
||
<a name="l00307"></a>00307 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:30; <span class="comment">/* */</span>
|
||
<a name="l00308"></a>00308 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TEAF:1; <span class="comment">/* */</span>
|
||
<a name="l00309"></a>00309 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BMTF:1; <span class="comment">/* */</span>
|
||
<a name="l00310"></a>00310 } B;
|
||
<a name="l00311"></a>00311 } TESR; <span class="comment">/* EBI Transfer Error Status Register (TESR) <URM>EBI_TESR</URM> @baseaddress + 0x08 */</span>
|
||
<a name="l00312"></a>00312
|
||
<a name="l00313"></a>00313 <span class="keyword">union </span>{
|
||
<a name="l00314"></a>00314 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00315"></a>00315 <span class="keyword">struct </span>{
|
||
<a name="l00316"></a>00316 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:16; <span class="comment">/* */</span>
|
||
<a name="l00317"></a>00317 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BMT:8; <span class="comment">/* */</span>
|
||
<a name="l00318"></a>00318 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BME:1; <span class="comment">/* */</span>
|
||
<a name="l00319"></a>00319 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:7; <span class="comment">/* */</span>
|
||
<a name="l00320"></a>00320 } B;
|
||
<a name="l00321"></a>00321 } BMCR; <span class="comment">/* <URM>EBI_BMCR</URM> @baseaddress + 0x0C */</span>
|
||
<a name="l00322"></a>00322
|
||
<a name="l00323"></a>00323 <span class="keyword">struct </span>CS_tag CS[4];
|
||
<a name="l00324"></a>00324
|
||
<a name="l00325"></a>00325 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> EBI_reserved2[4];
|
||
<a name="l00326"></a>00326
|
||
<a name="l00327"></a>00327 <span class="comment">/* Calibration registers */</span>
|
||
<a name="l00328"></a>00328 <span class="keyword">struct </span>CAL_CS_tag CAL_CS[4];
|
||
<a name="l00329"></a>00329
|
||
<a name="l00330"></a>00330 }; <span class="comment">/* end of EBI_tag */</span>
|
||
<a name="l00331"></a>00331 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l00332"></a>00332 <span class="comment">/* MODULE : FLASH */</span>
|
||
<a name="l00333"></a>00333 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l00334"></a>00334 <span class="comment">/* 3 flash modules implemented. */</span>
|
||
<a name="l00335"></a>00335 <span class="comment">/* HBL and HBS not used in Bank 0 / Array 0 */</span>
|
||
<a name="l00336"></a>00336 <span class="comment">/* LML, SLL, LMS, PFCR1, PFAPR, PFCR2, and PFCR3 not used in */</span>
|
||
<a name="l00337"></a>00337 <span class="comment">/* Bank 1 / Array 1 or Bank 1 / Array 3 */</span>
|
||
<a name="l00338"></a>00338 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l00339"></a>00339 <span class="keyword">struct </span>FLASH_tag {
|
||
<a name="l00340"></a>00340 <span class="keyword">union </span>{ <span class="comment">/* Module Configuration Register (MCR)@baseaddress + 0x00 */</span>
|
||
<a name="l00341"></a>00341 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00342"></a>00342 <span class="keyword">struct </span>{
|
||
<a name="l00343"></a>00343 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EDC:1; <span class="comment">/* ECC Data Correction (Read/Clear) */</span>
|
||
<a name="l00344"></a>00344 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:4; <span class="comment">/* Reserved */</span>
|
||
<a name="l00345"></a>00345 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SIZE:3; <span class="comment">/* Array Size (Read Only) */</span>
|
||
<a name="l00346"></a>00346 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* Reserved */</span>
|
||
<a name="l00347"></a>00347 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LAS:3; <span class="comment">/* Low Address Space (Read Only) */</span>
|
||
<a name="l00348"></a>00348 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:3; <span class="comment">/* Reserved */</span>
|
||
<a name="l00349"></a>00349 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MAS:1; <span class="comment">/* Mid Address Space (Read Only) */</span>
|
||
<a name="l00350"></a>00350 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EER:1; <span class="comment">/* ECC Event Error (Read/Clear) */</span><span class="comment">/* <LEGACY> BBEPE and EPE </LEGACY> */</span>
|
||
<a name="l00351"></a>00351 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RWE:1; <span class="comment">/* Read While Write Event Error (Read/Clear) */</span>
|
||
<a name="l00352"></a>00352 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:2; <span class="comment">/* Reserved */</span>
|
||
<a name="l00353"></a>00353 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PEAS:1; <span class="comment">/* Program/Erase Access Space (Read Only) */</span>
|
||
<a name="l00354"></a>00354 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DONE:1; <span class="comment">/* Status (Read Only) */</span>
|
||
<a name="l00355"></a>00355 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PEG:1; <span class="comment">/* Program/Erase Good (Read Only) */</span>
|
||
<a name="l00356"></a>00356 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:4; <span class="comment">/* Reserved */</span><span class="comment">/* <LEGACY> RSD PEG STOP RSVD </LEGACY> */</span>
|
||
<a name="l00357"></a>00357 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PGM:1; <span class="comment">/* Program (Read/Write) */</span>
|
||
<a name="l00358"></a>00358 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PSUS:1; <span class="comment">/* Program Suspend (Read/Write) */</span>
|
||
<a name="l00359"></a>00359 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERS:1; <span class="comment">/* Erase (Read/Write) */</span>
|
||
<a name="l00360"></a>00360 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ESUS:1; <span class="comment">/* Erase Suspend (Read/Write) */</span>
|
||
<a name="l00361"></a>00361 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EHV:1; <span class="comment">/* Enable High Voltage (Read/Write) */</span>
|
||
<a name="l00362"></a>00362 } B;
|
||
<a name="l00363"></a>00363 } MCR;
|
||
<a name="l00364"></a>00364
|
||
<a name="l00365"></a>00365 <span class="keyword">union </span>{ <span class="comment">/* Low/Mid-Address Space Block Locking Register (LML)@baseaddress + 0x04 */</span>
|
||
<a name="l00366"></a>00366 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00367"></a>00367 <span class="keyword">struct </span>{
|
||
<a name="l00368"></a>00368 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LME:1; <span class="comment">/* Low/Mid address space block enable (Read Only) */</span>
|
||
<a name="l00369"></a>00369 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:10; <span class="comment">/* Reserved */</span>
|
||
<a name="l00370"></a>00370 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SLOCK:1; <span class="comment">/*<URM>SLK</URM> */</span><span class="comment">/* Shadow address space block lock (Read/Write) */</span>
|
||
<a name="l00371"></a>00371 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:2; <span class="comment">/* Reserved */</span>
|
||
<a name="l00372"></a>00372 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MLOCK:2; <span class="comment">/*<URM>MLK</URM> */</span><span class="comment">/* Mid address space block lock (Read/Write) */</span>
|
||
<a name="l00373"></a>00373 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:8; <span class="comment">/* Reserved */</span>
|
||
<a name="l00374"></a>00374 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LLOCK:8; <span class="comment">/*<URM>LLK</URM> */</span><span class="comment">/* Low address space block lock (Read/Write) */</span>
|
||
<a name="l00375"></a>00375 } B;
|
||
<a name="l00376"></a>00376 } LMLR; <span class="comment">/*<URM>LML</URM> */</span>
|
||
<a name="l00377"></a>00377
|
||
<a name="l00378"></a>00378 <span class="keyword">union </span>{ <span class="comment">/* High-Address Space Block Locking Register (HBL) - @baseaddress + 0x08 */</span>
|
||
<a name="l00379"></a>00379 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00380"></a>00380 <span class="keyword">struct </span>{
|
||
<a name="l00381"></a>00381 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> HBE:1; <span class="comment">/* High address space Block Enable (Read Only) */</span>
|
||
<a name="l00382"></a>00382 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:27; <span class="comment">/* Reserved */</span>
|
||
<a name="l00383"></a>00383 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> HBLOCK:4; <span class="comment">/* High address space block lock (Read/Write) */</span>
|
||
<a name="l00384"></a>00384 } B;
|
||
<a name="l00385"></a>00385 } HLR; <span class="comment">/*<URM>HBL</URM> */</span>
|
||
<a name="l00386"></a>00386
|
||
<a name="l00387"></a>00387 <span class="keyword">union </span>{ <span class="comment">/* Secondary Low/Mid-Address Space Block Locking Register (SLL)@baseaddress + 0x0C */</span>
|
||
<a name="l00388"></a>00388 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00389"></a>00389 <span class="keyword">struct </span>{
|
||
<a name="l00390"></a>00390 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SLE:1; <span class="comment">/* Secondary low/mid address space block enable (Read Only) */</span>
|
||
<a name="l00391"></a>00391 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:10; <span class="comment">/* Reserved */</span>
|
||
<a name="l00392"></a>00392 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SSLOCK:1; <span class="comment">/*<URM>SSLK</URM> */</span><span class="comment">/* Secondary shadow address space block lock (Read/Write) */</span>
|
||
<a name="l00393"></a>00393 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:2; <span class="comment">/* Reserved */</span>
|
||
<a name="l00394"></a>00394 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SMLOCK:2; <span class="comment">/*<URM>SMK</URM> */</span><span class="comment">/* Secondary mid address space block lock (Read/Write) */</span>
|
||
<a name="l00395"></a>00395 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:8; <span class="comment">/* Reserved */</span>
|
||
<a name="l00396"></a>00396 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SLLOCK:8; <span class="comment">/*<URM>SLK</URM> */</span><span class="comment">/* Secondary low address space block lock (Read/Write) */</span>
|
||
<a name="l00397"></a>00397 } B;
|
||
<a name="l00398"></a>00398 } SLMLR; <span class="comment">/*<URM>SLL</URM> */</span>
|
||
<a name="l00399"></a>00399
|
||
<a name="l00400"></a>00400 <span class="keyword">union </span>{ <span class="comment">/* Low/Mid-Address Space Block Select Register (LMS)@baseaddress + 0x10 */</span>
|
||
<a name="l00401"></a>00401 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00402"></a>00402 <span class="keyword">struct </span>{
|
||
<a name="l00403"></a>00403 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:14; <span class="comment">/* Reserved */</span>
|
||
<a name="l00404"></a>00404 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MSEL:2; <span class="comment">/*<URM>MSL</URM> */</span><span class="comment">/* Mid address space block select (Read/Write) */</span>
|
||
<a name="l00405"></a>00405 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:8; <span class="comment">/* Reserved */</span>
|
||
<a name="l00406"></a>00406 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LSEL:8; <span class="comment">/*<URM>LSL</URM> */</span><span class="comment">/* Low address space block select (Read/Write) */</span>
|
||
<a name="l00407"></a>00407 } B;
|
||
<a name="l00408"></a>00408 } LMSR; <span class="comment">/*<URM>LMS</URM> */</span>
|
||
<a name="l00409"></a>00409
|
||
<a name="l00410"></a>00410 <span class="keyword">union </span>{ <span class="comment">/* High-Address Space Block Select Register (HBS) - not used@baseaddress + 0x14 */</span>
|
||
<a name="l00411"></a>00411 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00412"></a>00412 <span class="keyword">struct </span>{
|
||
<a name="l00413"></a>00413 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:28; <span class="comment">/* Reserved */</span>
|
||
<a name="l00414"></a>00414 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> HBSEL:4; <span class="comment">/*<URM>HSL</URM> */</span><span class="comment">/* High address space block select (Read/Write) */</span>
|
||
<a name="l00415"></a>00415 } B;
|
||
<a name="l00416"></a>00416 } HSR; <span class="comment">/*<URM>HBS</URM> */</span>
|
||
<a name="l00417"></a>00417
|
||
<a name="l00418"></a>00418 <span class="keyword">union </span>{ <span class="comment">/* Address Register (ADR)@baseaddress + 0x18 */</span>
|
||
<a name="l00419"></a>00419 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00420"></a>00420 <span class="keyword">struct </span>{
|
||
<a name="l00421"></a>00421 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SAD:1; <span class="comment">/* Shadow address (Read Only) */</span>
|
||
<a name="l00422"></a>00422 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:10; <span class="comment">/* Reserved */</span>
|
||
<a name="l00423"></a>00423 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ADDR:18; <span class="comment">/*<URM>AD</URM> */</span><span class="comment">/* Address 20-3 (Read Only) */</span>
|
||
<a name="l00424"></a>00424 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:3; <span class="comment">/* Reserved */</span>
|
||
<a name="l00425"></a>00425 } B;
|
||
<a name="l00426"></a>00426 } AR; <span class="comment">/*<URM>ADR</URM> */</span>
|
||
<a name="l00427"></a>00427
|
||
<a name="l00428"></a>00428 <span class="keyword">union </span>{ <span class="comment">/* @baseaddress + 0x1C */</span>
|
||
<a name="l00429"></a>00429 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00430"></a>00430 <span class="keyword">struct </span>{
|
||
<a name="l00431"></a>00431 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:7; <span class="comment">/* Reserved */</span>
|
||
<a name="l00432"></a>00432 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> GCE:1; <span class="comment">/* Global Configuration Enable (Read/Write) */</span>
|
||
<a name="l00433"></a>00433 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:4; <span class="comment">/* Reserved */</span>
|
||
<a name="l00434"></a>00434 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> M3PFE:1; <span class="comment">/* Master 3 Prefetch Enable (Read/Write) */</span>
|
||
<a name="l00435"></a>00435 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> M2PFE:1; <span class="comment">/* Master 2 Prefetch Enable (Read/Write) */</span>
|
||
<a name="l00436"></a>00436 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> M1PFE:1; <span class="comment">/* Master 1 Prefetch Enable (Read/Write) */</span>
|
||
<a name="l00437"></a>00437 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> M0PFE:1; <span class="comment">/* Master 0 Prefetch Enable (Read/Write) */</span>
|
||
<a name="l00438"></a>00438 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> APC:3; <span class="comment">/* Address Pipelining Control (Read/Write) */</span>
|
||
<a name="l00439"></a>00439 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WWSC:2; <span class="comment">/* Write Wait State Control (Read/Write) */</span>
|
||
<a name="l00440"></a>00440 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RWSC:3; <span class="comment">/* Read Wait State Control (Read/Write) */</span>
|
||
<a name="l00441"></a>00441 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* Reserved */</span>
|
||
<a name="l00442"></a>00442 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DPFEN:1; <span class="comment">/*<URM>DPFE</URM> */</span><span class="comment">/* Data Prefetch Enable (Read/Write) */</span>
|
||
<a name="l00443"></a>00443 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* Reserved */</span>
|
||
<a name="l00444"></a>00444 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IPFEN:1; <span class="comment">/*<URM>IPFE</URM> */</span><span class="comment">/* Instruction Prefetch Enable (Read/Write) */</span>
|
||
<a name="l00445"></a>00445 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* Reserved */</span>
|
||
<a name="l00446"></a>00446 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PFLIM:2; <span class="comment">/* Prefetch Limit (Read/Write) */</span>
|
||
<a name="l00447"></a>00447 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BFEN:1; <span class="comment">/*<URM>BFE</URM> */</span><span class="comment">/* Buffer Enable (Read/Write) */</span>
|
||
<a name="l00448"></a>00448 } B;
|
||
<a name="l00449"></a>00449 } BIUCR; <span class="comment">/*<URM>PFCR1</URM> */</span>
|
||
<a name="l00450"></a>00450
|
||
<a name="l00451"></a>00451 <span class="keyword">union </span>{ <span class="comment">/* @baseaddress + 0x20 */</span>
|
||
<a name="l00452"></a>00452 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00453"></a>00453 <span class="keyword">struct </span>{
|
||
<a name="l00454"></a>00454 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:24; <span class="comment">/* Reserved */</span>
|
||
<a name="l00455"></a>00455 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> M3AP:2; <span class="comment">/* Master 3 Access Protection (Read/Write) */</span>
|
||
<a name="l00456"></a>00456 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> M2AP:2; <span class="comment">/* Master 2 Access Protection (Read/Write) */</span>
|
||
<a name="l00457"></a>00457 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> M1AP:2; <span class="comment">/* Master 1 Access Protection (Read/Write) */</span>
|
||
<a name="l00458"></a>00458 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> M0AP:2; <span class="comment">/* Master 0 Access Protection (Read/Write) */</span>
|
||
<a name="l00459"></a>00459 } B;
|
||
<a name="l00460"></a>00460 } BIUAPR; <span class="comment">/*<URM>PFAPR</URM> */</span>
|
||
<a name="l00461"></a>00461
|
||
<a name="l00462"></a>00462 <span class="keyword">union </span>{ <span class="comment">/* @baseaddress + 0x24 */</span>
|
||
<a name="l00463"></a>00463 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00464"></a>00464 <span class="keyword">struct </span>{
|
||
<a name="l00465"></a>00465 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LBCFG:2; <span class="comment">/* Line Buffer Configuration (Read/Write) */</span>
|
||
<a name="l00466"></a>00466 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:30; <span class="comment">/* Reserved */</span>
|
||
<a name="l00467"></a>00467 } B;
|
||
<a name="l00468"></a>00468 } BIUCR2;
|
||
<a name="l00469"></a>00469
|
||
<a name="l00470"></a>00470 <span class="keyword">union </span>{ <span class="comment">/* @baseaddress + 0x28 */</span>
|
||
<a name="l00471"></a>00471 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00472"></a>00472 <span class="keyword">struct </span>{
|
||
<a name="l00473"></a>00473 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:25; <span class="comment">/* Reserved */</span>
|
||
<a name="l00474"></a>00474 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> B1_DPFE:1; <span class="comment">/* Bank1 Data Prefetch Enable (Read/Write) */</span>
|
||
<a name="l00475"></a>00475 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* Reserved */</span>
|
||
<a name="l00476"></a>00476 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> B1_IPFE:1; <span class="comment">/* Bank1 Instruction Prefetch Enable (Read/Write) */</span>
|
||
<a name="l00477"></a>00477 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* Reserved */</span>
|
||
<a name="l00478"></a>00478 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> B1_PFLIM:2; <span class="comment">/* Bank1 Prefetch Limit (Read/Write) */</span>
|
||
<a name="l00479"></a>00479 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> B1_BFE:1; <span class="comment">/* Bank1 Buffer Enable (Read/Write) */</span>
|
||
<a name="l00480"></a>00480 } B;
|
||
<a name="l00481"></a>00481 } PFCR3;
|
||
<a name="l00482"></a>00482
|
||
<a name="l00483"></a>00483 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> FLASH_reserverd_89[4];
|
||
<a name="l00484"></a>00484
|
||
<a name="l00485"></a>00485 <span class="keyword">union </span>{ <span class="comment">/* User Test 0 (UT0) register@baseaddress + 0x3c */</span>
|
||
<a name="l00486"></a>00486 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00487"></a>00487 <span class="keyword">struct </span>{
|
||
<a name="l00488"></a>00488 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> UTE:1; <span class="comment">/* User test enable (Read/Clear) */</span>
|
||
<a name="l00489"></a>00489 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SBCE:1; <span class="comment">/* Single bit correction enable (Read/Clear) */</span>
|
||
<a name="l00490"></a>00490 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:6; <span class="comment">/* Reserved */</span>
|
||
<a name="l00491"></a>00491 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DSI:8; <span class="comment">/* Data syndrome input (Read/Write) */</span>
|
||
<a name="l00492"></a>00492 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:9; <span class="comment">/* Reserved */</span>
|
||
<a name="l00493"></a>00493 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* Reserved (Read/Write) */</span>
|
||
<a name="l00494"></a>00494 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MRE:1; <span class="comment">/* Margin Read Enable (Read/Write) */</span>
|
||
<a name="l00495"></a>00495 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MRV:1; <span class="comment">/* Margin Read Value (Read/Write) */</span>
|
||
<a name="l00496"></a>00496 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EIE:1; <span class="comment">/* ECC data Input Enable (Read/Write) */</span>
|
||
<a name="l00497"></a>00497 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> AIS:1; <span class="comment">/* Array Integrity Sequence (Read/Write) */</span>
|
||
<a name="l00498"></a>00498 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> AIE:1; <span class="comment">/* Array Integrity Enable (Read/Write) */</span>
|
||
<a name="l00499"></a>00499 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> AID:1; <span class="comment">/* Array Integrity Done (Read Only) */</span>
|
||
<a name="l00500"></a>00500 } B;
|
||
<a name="l00501"></a>00501 } UT0;
|
||
<a name="l00502"></a>00502
|
||
<a name="l00503"></a>00503 <span class="keyword">union </span>{ <span class="comment">/* User Test 1 (UT1) register@baseaddress + 0x40 */</span>
|
||
<a name="l00504"></a>00504 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00505"></a>00505 <span class="keyword">struct </span>{
|
||
<a name="l00506"></a>00506 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DAI:32; <span class="comment">/* Data Array Input (Read/Write) */</span>
|
||
<a name="l00507"></a>00507 } B;
|
||
<a name="l00508"></a>00508 } UT1;
|
||
<a name="l00509"></a>00509
|
||
<a name="l00510"></a>00510 <span class="keyword">union </span>{ <span class="comment">/* User Test 2 (UT2) register@baseaddress + 0x44 */</span>
|
||
<a name="l00511"></a>00511 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00512"></a>00512 <span class="keyword">struct </span>{
|
||
<a name="l00513"></a>00513 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DAI:32; <span class="comment">/* Data Array Input (Read/Write) */</span>
|
||
<a name="l00514"></a>00514 } B;
|
||
<a name="l00515"></a>00515 } UT2;
|
||
<a name="l00516"></a>00516
|
||
<a name="l00517"></a>00517 <span class="keyword">union </span>{ <span class="comment">/* User Multiple Input Signature Register 0-5 (UMISR[5])@baseaddress + 0x48 */</span>
|
||
<a name="l00518"></a>00518 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00519"></a>00519 <span class="keyword">struct </span>{
|
||
<a name="l00520"></a>00520 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MS:32; <span class="comment">/* Multiple input Signature (Read/Write) */</span>
|
||
<a name="l00521"></a>00521 } B;
|
||
<a name="l00522"></a>00522 } UMISR[5];
|
||
<a name="l00523"></a>00523
|
||
<a name="l00524"></a>00524 }; <span class="comment">/* end of FLASH_tag */</span>
|
||
<a name="l00525"></a>00525 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l00526"></a>00526 <span class="comment">/* MODULE : SIU */</span>
|
||
<a name="l00527"></a>00527 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l00528"></a>00528 <span class="keyword">struct </span>SIU_tag {
|
||
<a name="l00529"></a>00529 <span class="keyword">union </span>{
|
||
<a name="l00530"></a>00530 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00531"></a>00531 <span class="keyword">struct </span>{
|
||
<a name="l00532"></a>00532 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> S_F:1; <span class="comment">/* Identifies the Manufacturer <URM>S/F</URM> */</span>
|
||
<a name="l00533"></a>00533 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> FLASH_SIZE_1:4; <span class="comment">/* Define major Flash memory size (see Table 15-4 for details) <URM>Flash Size 1</URM> */</span>
|
||
<a name="l00534"></a>00534 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> FLASH_SIZE_2:4; <span class="comment">/* Define Flash memory size, small granularity (see Table 15-5 for details) <URM>Flash Size 1</URM> */</span>
|
||
<a name="l00535"></a>00535 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TEMP_RANGE:2; <span class="comment">/* Define maximum operating range <URM>Temp Range</URM> */</span>
|
||
<a name="l00536"></a>00536 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* Reserved for future enhancements */</span>
|
||
<a name="l00537"></a>00537 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MAX_FREQ:2; <span class="comment">/* Define maximum device speed <URM>Max Freq</URM> */</span>
|
||
<a name="l00538"></a>00538 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* Reserved for future enhancements */</span>
|
||
<a name="l00539"></a>00539 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SUPPLY:1; <span class="comment">/* Defines if the part is 5V or 3V <URM>Supply</URM> */</span>
|
||
<a name="l00540"></a>00540 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PART_NUMBER:8; <span class="comment">/* Contain the ASCII representation of the character that indicates the product <URM>Part Number</URM> */</span>
|
||
<a name="l00541"></a>00541 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TBD:1; <span class="comment">/* 1-bit field defined by SoC to describe optional feature, e.g., additional SPI */</span>
|
||
<a name="l00542"></a>00542 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:2; <span class="comment">/* Reserved for future enhancements */</span>
|
||
<a name="l00543"></a>00543 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EE:1; <span class="comment">/* Indicates if Data Flash is present */</span>
|
||
<a name="l00544"></a>00544 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:3; <span class="comment">/* Reserved for future enhancements */</span>
|
||
<a name="l00545"></a>00545 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> FR:1; <span class="comment">/* Indicates if Data FlexRay is present */</span>
|
||
<a name="l00546"></a>00546 } B;
|
||
<a name="l00547"></a>00547 } MIDR2; <span class="comment">/* MCU ID Register 2 <URM>SIU_MIDR2</URM> @baseaddress + 0x4 */</span>
|
||
<a name="l00548"></a>00548
|
||
<a name="l00549"></a>00549 <span class="keyword">union </span>{
|
||
<a name="l00550"></a>00550 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00551"></a>00551 <span class="keyword">struct </span>{
|
||
<a name="l00552"></a>00552 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PARTNUM:16; <span class="comment">/* Device part number: 0x5633 */</span>
|
||
<a name="l00553"></a>00553 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CSP:1; <span class="comment">/* CSP configuration (new in MPC563xM) */</span>
|
||
<a name="l00554"></a>00554 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PKG:5; <span class="comment">/* Indicate the package the die is mounted in. (new in MPC563xM) */</span>
|
||
<a name="l00555"></a>00555 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:2; <span class="comment">/* Reserved */</span>
|
||
<a name="l00556"></a>00556 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MASKNUM:8; <span class="comment">/* MCU major mask number; updated for each complete resynthesis. MCU minor mask number; updated for each mask revision */</span>
|
||
<a name="l00557"></a>00557 } B;
|
||
<a name="l00558"></a>00558 } MIDR; <span class="comment">/* MCU ID Register (MIDR) <URM>SIU_MIDR</URM> @baseaddress + 0x8 */</span>
|
||
<a name="l00559"></a>00559
|
||
<a name="l00560"></a>00560 <span class="keyword">union </span>{
|
||
<a name="l00561"></a>00561 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00562"></a>00562 } TST; <span class="comment">/* SIU Test Register (SIU_TST) <URM>SIU_TST</URM> @baseaddress + 0xC */</span>
|
||
<a name="l00563"></a>00563
|
||
<a name="l00564"></a>00564 <span class="keyword">union </span>{
|
||
<a name="l00565"></a>00565 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00566"></a>00566 <span class="keyword">struct </span>{
|
||
<a name="l00567"></a>00567 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PORS:1; <span class="comment">/* Power-On Reset Status */</span>
|
||
<a name="l00568"></a>00568 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERS:1; <span class="comment">/* External Reset Status */</span>
|
||
<a name="l00569"></a>00569 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LLRS:1; <span class="comment">/* Loss of Lock Reset Status */</span>
|
||
<a name="l00570"></a>00570 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LCRS:1; <span class="comment">/* Loss of Clock Reset Status */</span>
|
||
<a name="l00571"></a>00571 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WDRS:1; <span class="comment">/* Watchdog Timer/Debug Reset Status */</span>
|
||
<a name="l00572"></a>00572 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CRS:1; <span class="comment">/* Checkstop Reset Status */</span>
|
||
<a name="l00573"></a>00573 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SWTRS:1; <span class="comment">/* Software Watchdog Timer Reset Status (new in MPC563xM) */</span>
|
||
<a name="l00574"></a>00574 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:7; <span class="comment">/* */</span>
|
||
<a name="l00575"></a>00575 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SSRS:1; <span class="comment">/* Software System Reset Status */</span>
|
||
<a name="l00576"></a>00576 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SERF:1; <span class="comment">/* Software External Reset Flag */</span>
|
||
<a name="l00577"></a>00577 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WKPCFG:1; <span class="comment">/* Weak Pull Configuration Pin Status */</span>
|
||
<a name="l00578"></a>00578 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:11; <span class="comment">/* */</span>
|
||
<a name="l00579"></a>00579 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ABR:1; <span class="comment">/* Auto Baud Rate (new in MPC563xM) */</span>
|
||
<a name="l00580"></a>00580 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BOOTCFG:2; <span class="comment">/* Reset Configuration Pin Status */</span>
|
||
<a name="l00581"></a>00581 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RGF:1; <span class="comment">/* RESET Glitch Flag */</span>
|
||
<a name="l00582"></a>00582 } B;
|
||
<a name="l00583"></a>00583 } RSR; <span class="comment">/* Reset Status Register (SIU_RSR) <URM>SIU_RSR</URM> @baseaddress + 0x10 */</span>
|
||
<a name="l00584"></a>00584
|
||
<a name="l00585"></a>00585 <span class="keyword">union </span>{
|
||
<a name="l00586"></a>00586 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00587"></a>00587 <span class="keyword">struct </span>{
|
||
<a name="l00588"></a>00588 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SSR:1; <span class="comment">/* Software System Reset */</span>
|
||
<a name="l00589"></a>00589 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SER:1; <span class="comment">/* Software External Reset */</span>
|
||
<a name="l00590"></a>00590 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:14; <span class="comment">/* */</span>
|
||
<a name="l00591"></a>00591 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CRE:1; <span class="comment">/* Checkstop Reset Enable */</span>
|
||
<a name="l00592"></a>00592 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:15; <span class="comment">/* */</span>
|
||
<a name="l00593"></a>00593 } B;
|
||
<a name="l00594"></a>00594 } SRCR; <span class="comment">/* System Reset Control Register (SRCR) <URM>SIU_SRCR</URM> @baseaddress + 0x14 */</span>
|
||
<a name="l00595"></a>00595
|
||
<a name="l00596"></a>00596 <span class="keyword">union </span>{
|
||
<a name="l00597"></a>00597 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00598"></a>00598 <span class="keyword">struct </span>{
|
||
<a name="l00599"></a>00599 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> NMI:1; <span class="comment">/* Non-Maskable Interrupt Flag (new in MPC563xM) */</span>
|
||
<a name="l00600"></a>00600 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:7; <span class="comment">/* */</span>
|
||
<a name="l00601"></a>00601 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SWT:1; <span class="comment">/* Software Watch Dog Timer Interrupt Flag, from platform (new in MPC563xM) */</span>
|
||
<a name="l00602"></a>00602 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:7; <span class="comment">/* */</span>
|
||
<a name="l00603"></a>00603 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EIF15:1; <span class="comment">/* External Interrupt Request Flag x */</span>
|
||
<a name="l00604"></a>00604 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EIF14:1; <span class="comment">/* External Interrupt Request Flag x */</span>
|
||
<a name="l00605"></a>00605 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EIF13:1; <span class="comment">/* External Interrupt Request Flag x */</span>
|
||
<a name="l00606"></a>00606 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EIF12:1; <span class="comment">/* External Interrupt Request Flag x */</span>
|
||
<a name="l00607"></a>00607 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EIF11:1; <span class="comment">/* External Interrupt Request Flag x */</span>
|
||
<a name="l00608"></a>00608 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EIF10:1; <span class="comment">/* External Interrupt Request Flag x */</span>
|
||
<a name="l00609"></a>00609 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EIF9:1; <span class="comment">/* External Interrupt Request Flag x */</span>
|
||
<a name="l00610"></a>00610 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EIF8:1; <span class="comment">/* External Interrupt Request Flag x */</span>
|
||
<a name="l00611"></a>00611 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:3; <span class="comment">/* (reserved in MPC563xM) */</span>
|
||
<a name="l00612"></a>00612 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EIF4:1; <span class="comment">/* External Interrupt Request Flag x */</span>
|
||
<a name="l00613"></a>00613 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EIF3:1; <span class="comment">/* External Interrupt Request Flag x */</span>
|
||
<a name="l00614"></a>00614 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:2; <span class="comment">/* (reserved in MPC563xM) */</span>
|
||
<a name="l00615"></a>00615 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EIF0:1; <span class="comment">/* External Interrupt Request Flag x */</span>
|
||
<a name="l00616"></a>00616 } B;
|
||
<a name="l00617"></a>00617 } EISR; <span class="comment">/* SIU External Interrupt Status Register (EISR) <URM>SIU_EISR</URM> @baseaddress + 0x18 */</span>
|
||
<a name="l00618"></a>00618
|
||
<a name="l00619"></a>00619 <span class="keyword">union </span>{
|
||
<a name="l00620"></a>00620 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00621"></a>00621 <span class="keyword">struct </span>{
|
||
<a name="l00622"></a>00622 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> NMI_SEL:1; <span class="comment">/* NMI Interrupt Platform Input Selection (new in MPC563xM) */</span>
|
||
<a name="l00623"></a>00623 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:7; <span class="comment">/* */</span>
|
||
<a name="l00624"></a>00624 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SWT_SEL:1;
|
||
<a name="l00625"></a>00625 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:7;
|
||
<a name="l00626"></a>00626 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EIRE15:1; <span class="comment">/* External DMA/Interrupt Request Enable x */</span>
|
||
<a name="l00627"></a>00627 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EIRE14:1; <span class="comment">/* External DMA/Interrupt Request Enable x */</span>
|
||
<a name="l00628"></a>00628 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EIRE13:1; <span class="comment">/* External DMA/Interrupt Request Enable x */</span>
|
||
<a name="l00629"></a>00629 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EIRE12:1; <span class="comment">/* External DMA/Interrupt Request Enable x */</span>
|
||
<a name="l00630"></a>00630 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EIRE11:1; <span class="comment">/* External DMA/Interrupt Request Enable x */</span>
|
||
<a name="l00631"></a>00631 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EIRE10:1; <span class="comment">/* External DMA/Interrupt Request Enable x */</span>
|
||
<a name="l00632"></a>00632 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EIRE9:1; <span class="comment">/* External DMA/Interrupt Request Enable x */</span>
|
||
<a name="l00633"></a>00633 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EIRE8:1; <span class="comment">/* External DMA/Interrupt Request Enable x */</span>
|
||
<a name="l00634"></a>00634 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EIRE7:1; <span class="comment">/* External DMA/Interrupt Request Enable x */</span>
|
||
<a name="l00635"></a>00635 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EIRE6:1; <span class="comment">/* External DMA/Interrupt Request Enable x */</span>
|
||
<a name="l00636"></a>00636 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EIRE5:1; <span class="comment">/* External DMA/Interrupt Request Enable x */</span>
|
||
<a name="l00637"></a>00637 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EIRE4:1; <span class="comment">/* External DMA/Interrupt Request Enable x */</span>
|
||
<a name="l00638"></a>00638 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EIRE3:1; <span class="comment">/* External DMA/Interrupt Request Enable x */</span>
|
||
<a name="l00639"></a>00639 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EIRE2:1; <span class="comment">/* External DMA/Interrupt Request Enable x */</span>
|
||
<a name="l00640"></a>00640 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EIRE1:1; <span class="comment">/* External DMA/Interrupt Request Enable x */</span>
|
||
<a name="l00641"></a>00641 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EIRE0:1; <span class="comment">/* External DMA/Interrupt Request Enable x */</span>
|
||
<a name="l00642"></a>00642 } B;
|
||
<a name="l00643"></a>00643 } DIRER; <span class="comment">/* DMA/Interrupt Request Enable Register (DIRER) <URM>SIU_DIRER</URM> @baseaddress + 0x1C */</span>
|
||
<a name="l00644"></a>00644
|
||
<a name="l00645"></a>00645 <span class="keyword">union </span>{
|
||
<a name="l00646"></a>00646 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00647"></a>00647 <span class="keyword">struct </span>{
|
||
<a name="l00648"></a>00648 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:28; <span class="comment">/* */</span>
|
||
<a name="l00649"></a>00649 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DIRS3:1; <span class="comment">/* DMA/Interrupt Request Select x */</span>
|
||
<a name="l00650"></a>00650 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:2; <span class="comment">/* reserved in MPC563xM */</span>
|
||
<a name="l00651"></a>00651 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DIRS0:1; <span class="comment">/* DMA/Interrupt Request Select x */</span>
|
||
<a name="l00652"></a>00652 } B;
|
||
<a name="l00653"></a>00653 } DIRSR; <span class="comment">/* DMA/Interrupt Request Select Register (DIRSR) <URM>SIU_DIRSR</URM> @baseaddress + 0x20 */</span>
|
||
<a name="l00654"></a>00654
|
||
<a name="l00655"></a>00655 <span class="keyword">union </span>{
|
||
<a name="l00656"></a>00656 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00657"></a>00657 <span class="keyword">struct </span>{
|
||
<a name="l00658"></a>00658 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:16; <span class="comment">/* */</span>
|
||
<a name="l00659"></a>00659 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OVF15:1; <span class="comment">/* Overrun Flag x */</span>
|
||
<a name="l00660"></a>00660 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OVF14:1; <span class="comment">/* Overrun Flag x */</span>
|
||
<a name="l00661"></a>00661 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OVF13:1; <span class="comment">/* Overrun Flag x */</span>
|
||
<a name="l00662"></a>00662 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OVF12:1; <span class="comment">/* Overrun Flag x */</span>
|
||
<a name="l00663"></a>00663 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OVF11:1; <span class="comment">/* Overrun Flag x */</span>
|
||
<a name="l00664"></a>00664 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OVF10:1; <span class="comment">/* Overrun Flag x */</span>
|
||
<a name="l00665"></a>00665 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OVF9:1; <span class="comment">/* Overrun Flag x */</span>
|
||
<a name="l00666"></a>00666 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OVF8:1; <span class="comment">/* Overrun Flag x */</span>
|
||
<a name="l00667"></a>00667 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:3; <span class="comment">/* reserved in MPC563xM */</span>
|
||
<a name="l00668"></a>00668 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OVF4:1; <span class="comment">/* Overrun Flag x */</span>
|
||
<a name="l00669"></a>00669 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OVF3:1; <span class="comment">/* Overrun Flag x */</span>
|
||
<a name="l00670"></a>00670 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:2; <span class="comment">/* reserved in MPC563xM */</span>
|
||
<a name="l00671"></a>00671 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OVF0:1; <span class="comment">/* Overrun Flag x */</span>
|
||
<a name="l00672"></a>00672 } B;
|
||
<a name="l00673"></a>00673 } OSR; <span class="comment">/* Overrun Status Register (OSR) <URM>SIU_OSR</URM> @baseaddress + 0x24 */</span>
|
||
<a name="l00674"></a>00674
|
||
<a name="l00675"></a>00675 <span class="keyword">union </span>{
|
||
<a name="l00676"></a>00676 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00677"></a>00677 <span class="keyword">struct </span>{
|
||
<a name="l00678"></a>00678 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:16; <span class="comment">/* */</span>
|
||
<a name="l00679"></a>00679 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ORE15:1; <span class="comment">/* Overrun Request Enable x */</span>
|
||
<a name="l00680"></a>00680 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ORE14:1; <span class="comment">/* Overrun Request Enable x */</span>
|
||
<a name="l00681"></a>00681 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ORE13:1; <span class="comment">/* Overrun Request Enable x */</span>
|
||
<a name="l00682"></a>00682 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ORE12:1; <span class="comment">/* Overrun Request Enable x */</span>
|
||
<a name="l00683"></a>00683 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ORE11:1; <span class="comment">/* Overrun Request Enable x */</span>
|
||
<a name="l00684"></a>00684 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ORE10:1; <span class="comment">/* Overrun Request Enable x */</span>
|
||
<a name="l00685"></a>00685 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ORE9:1; <span class="comment">/* Overrun Request Enable x */</span>
|
||
<a name="l00686"></a>00686 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ORE8:1; <span class="comment">/* Overrun Request Enable x */</span>
|
||
<a name="l00687"></a>00687 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:3; <span class="comment">/* reserved in MPC563xM */</span>
|
||
<a name="l00688"></a>00688 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ORE4:1; <span class="comment">/* Overrun Request Enable x */</span>
|
||
<a name="l00689"></a>00689 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ORE3:1; <span class="comment">/* Overrun Request Enable x */</span>
|
||
<a name="l00690"></a>00690 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:2; <span class="comment">/* reserved in MPC563xM */</span>
|
||
<a name="l00691"></a>00691 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ORE0:1; <span class="comment">/* Overrun Request Enable x */</span>
|
||
<a name="l00692"></a>00692 } B;
|
||
<a name="l00693"></a>00693 } ORER; <span class="comment">/* Overrun Request Enable Register (ORER) <URM>SIU_ORER</URM> @baseaddress + 0x28 */</span>
|
||
<a name="l00694"></a>00694
|
||
<a name="l00695"></a>00695 <span class="keyword">union </span>{
|
||
<a name="l00696"></a>00696 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00697"></a>00697 <span class="keyword">struct </span>{
|
||
<a name="l00698"></a>00698 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> NMIRE:1; <span class="comment">/* NMI Rising-Edge Event Enable x (new in MPC563xM) */</span>
|
||
<a name="l00699"></a>00699 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:15; <span class="comment">/* reserved in MPC563xM */</span>
|
||
<a name="l00700"></a>00700 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IREE15:1; <span class="comment">/* IRQ Rising-Edge Event Enable x */</span>
|
||
<a name="l00701"></a>00701 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IREE14:1; <span class="comment">/* IRQ Rising-Edge Event Enable x */</span>
|
||
<a name="l00702"></a>00702 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IREE13:1; <span class="comment">/* IRQ Rising-Edge Event Enable x */</span>
|
||
<a name="l00703"></a>00703 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IREE12:1; <span class="comment">/* IRQ Rising-Edge Event Enable x */</span>
|
||
<a name="l00704"></a>00704 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IREE11:1; <span class="comment">/* IRQ Rising-Edge Event Enable x */</span>
|
||
<a name="l00705"></a>00705 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IREE10:1; <span class="comment">/* IRQ Rising-Edge Event Enable x */</span>
|
||
<a name="l00706"></a>00706 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IREE9:1; <span class="comment">/* IRQ Rising-Edge Event Enable x */</span>
|
||
<a name="l00707"></a>00707 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IREE8:1; <span class="comment">/* IRQ Rising-Edge Event Enable x */</span>
|
||
<a name="l00708"></a>00708 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:3; <span class="comment">/* reserved in MPC563xM */</span>
|
||
<a name="l00709"></a>00709 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IREE4:1; <span class="comment">/* IRQ Rising-Edge Event Enable x */</span>
|
||
<a name="l00710"></a>00710 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IREE3:1; <span class="comment">/* IRQ Rising-Edge Event Enable x */</span>
|
||
<a name="l00711"></a>00711 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:2; <span class="comment">/* reserved in MPC563xM */</span>
|
||
<a name="l00712"></a>00712 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IREE0:1; <span class="comment">/* IRQ Rising-Edge Event Enable x */</span>
|
||
<a name="l00713"></a>00713 } B;
|
||
<a name="l00714"></a>00714 } IREER; <span class="comment">/* External IRQ Rising-Edge Event Enable Register (IREER) <URM>SIU_IREER</URM> @baseaddress + 0x2C */</span>
|
||
<a name="l00715"></a>00715
|
||
<a name="l00716"></a>00716 <span class="keyword">union </span>{
|
||
<a name="l00717"></a>00717 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00718"></a>00718 <span class="keyword">struct </span>{
|
||
<a name="l00719"></a>00719 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> NMIFE:1; <span class="comment">/* NMI Falling-Edge Event Enable x (new in MPC563xM) */</span>
|
||
<a name="l00720"></a>00720 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> Reserverd:15; <span class="comment">/* */</span>
|
||
<a name="l00721"></a>00721 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IFEE15:1; <span class="comment">/* IRQ Falling-Edge Event Enable x */</span>
|
||
<a name="l00722"></a>00722 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IFEE14:1; <span class="comment">/* IRQ Falling-Edge Event Enable x */</span>
|
||
<a name="l00723"></a>00723 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IFEE13:1; <span class="comment">/* IRQ Falling-Edge Event Enable x */</span>
|
||
<a name="l00724"></a>00724 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IFEE12:1; <span class="comment">/* IRQ Falling-Edge Event Enable x */</span>
|
||
<a name="l00725"></a>00725 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IFEE11:1; <span class="comment">/* IRQ Falling-Edge Event Enable x */</span>
|
||
<a name="l00726"></a>00726 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IFEE10:1; <span class="comment">/* IRQ Falling-Edge Event Enable x */</span>
|
||
<a name="l00727"></a>00727 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IFEE9:1; <span class="comment">/* IRQ Falling-Edge Event Enable x */</span>
|
||
<a name="l00728"></a>00728 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IFEE8:1; <span class="comment">/* IRQ Falling-Edge Event Enable x */</span>
|
||
<a name="l00729"></a>00729 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:3; <span class="comment">/* reserved in MPC563xM */</span>
|
||
<a name="l00730"></a>00730 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IFEE4:1; <span class="comment">/* IRQ Falling-Edge Event Enable x */</span>
|
||
<a name="l00731"></a>00731 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IFEE3:1; <span class="comment">/* IRQ Falling-Edge Event Enable x */</span>
|
||
<a name="l00732"></a>00732 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:2; <span class="comment">/* reserved in MPC563xM */</span>
|
||
<a name="l00733"></a>00733 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IFEE0:1; <span class="comment">/* IRQ Falling-Edge Event Enable x */</span>
|
||
<a name="l00734"></a>00734 } B;
|
||
<a name="l00735"></a>00735 } IFEER; <span class="comment">/* External IRQ Falling-Edge Event Enable Regi (IFEER) <URM>SIU_IFEER</URM> @baseaddress + 0x30 */</span>
|
||
<a name="l00736"></a>00736
|
||
<a name="l00737"></a>00737 <span class="keyword">union </span>{
|
||
<a name="l00738"></a>00738 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00739"></a>00739 <span class="keyword">struct </span>{
|
||
<a name="l00740"></a>00740 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:28; <span class="comment">/* */</span>
|
||
<a name="l00741"></a>00741 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DFL:4; <span class="comment">/* Digital Filter Length */</span>
|
||
<a name="l00742"></a>00742 } B;
|
||
<a name="l00743"></a>00743 } IDFR; <span class="comment">/* External IRQ Digital Filter Register (IDFR) <URM>SIU_IDFR</URM> @baseaddress + 0x40 */</span>
|
||
<a name="l00744"></a>00744
|
||
<a name="l00745"></a>00745 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> SIU_reserverd_153[3];
|
||
<a name="l00746"></a>00746
|
||
<a name="l00747"></a>00747 <span class="keyword">union </span>{
|
||
<a name="l00748"></a>00748 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> R;
|
||
<a name="l00749"></a>00749 <span class="keyword">struct </span>{
|
||
<a name="l00750"></a>00750 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a>:2; <span class="comment">/* */</span>
|
||
<a name="l00751"></a>00751 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> PA:4; <span class="comment">/* */</span>
|
||
<a name="l00752"></a>00752 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> OBE:1; <span class="comment">/* */</span>
|
||
<a name="l00753"></a>00753 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> IBE:1; <span class="comment">/* */</span>
|
||
<a name="l00754"></a>00754 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> DSC:2; <span class="comment">/* */</span>
|
||
<a name="l00755"></a>00755 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> ODE:1; <span class="comment">/* */</span>
|
||
<a name="l00756"></a>00756 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> HYS:1; <span class="comment">/* */</span>
|
||
<a name="l00757"></a>00757 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> SRC:2; <span class="comment">/* */</span>
|
||
<a name="l00758"></a>00758 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> WPE:1; <span class="comment">/* */</span>
|
||
<a name="l00759"></a>00759 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> WPS:1; <span class="comment">/* */</span>
|
||
<a name="l00760"></a>00760 } B;
|
||
<a name="l00761"></a>00761 } PCR[512]; <span class="comment">/* Pad Configuration Register (PCR) <URM>SIU_PCR</URM> @baseaddress + 0x600 */</span>
|
||
<a name="l00762"></a>00762
|
||
<a name="l00763"></a>00763 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> SIU_reserverd_164[112];
|
||
<a name="l00764"></a>00764
|
||
<a name="l00765"></a>00765 <span class="keyword">union </span>{
|
||
<a name="l00766"></a>00766 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> R;
|
||
<a name="l00767"></a>00767 <span class="keyword">struct </span>{
|
||
<a name="l00768"></a>00768 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a>:7; <span class="comment">/* */</span>
|
||
<a name="l00769"></a>00769 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> PDO:1; <span class="comment">/* */</span>
|
||
<a name="l00770"></a>00770 } B;
|
||
<a name="l00771"></a>00771 } GPDO[512]; <span class="comment">/* GPIO Pin Data Output Register (GPDO) <URM>SIU_GDPO</URM> @baseaddress + 0x800 */</span>
|
||
<a name="l00772"></a>00772
|
||
<a name="l00773"></a>00773 <span class="keyword">union </span>{
|
||
<a name="l00774"></a>00774 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> R;
|
||
<a name="l00775"></a>00775 <span class="keyword">struct </span>{
|
||
<a name="l00776"></a>00776 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a>:7; <span class="comment">/* */</span>
|
||
<a name="l00777"></a>00777 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> PDI:1; <span class="comment">/* */</span>
|
||
<a name="l00778"></a>00778 } B;
|
||
<a name="l00779"></a>00779 } GPDI[256]; <span class="comment">/* GPIO Pin Data Input Register (GDPI) <URM>SIU_GDPI</URM> @baseaddress + 0x900 */</span>
|
||
<a name="l00780"></a>00780
|
||
<a name="l00781"></a>00781 <span class="keyword">union </span>{
|
||
<a name="l00782"></a>00782 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00783"></a>00783 <span class="keyword">struct </span>{
|
||
<a name="l00784"></a>00784 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TSEL5:2; <span class="comment">/* eQADC Trigger 5 Input */</span>
|
||
<a name="l00785"></a>00785 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TSEL4:2; <span class="comment">/* eQADC Trigger 4 Input */</span>
|
||
<a name="l00786"></a>00786 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TSEL3:2; <span class="comment">/* eQADC Trigger 3 Input */</span>
|
||
<a name="l00787"></a>00787 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TSEL2:2; <span class="comment">/* eQADC Trigger 4 Input */</span>
|
||
<a name="l00788"></a>00788 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TSEL1:2; <span class="comment">/* eQADC Trigger 1 Input */</span>
|
||
<a name="l00789"></a>00789 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TSEL0:2; <span class="comment">/* eQADC Trigger 0 Input */</span>
|
||
<a name="l00790"></a>00790 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:20; <span class="comment">/* */</span>
|
||
<a name="l00791"></a>00791 } B;
|
||
<a name="l00792"></a>00792 } ETISR; <span class="comment">/* eQADC Trigger Input Select Register (ETISR) <URM>SIU_ETISR</URM> @baseaddress + 0x904 */</span>
|
||
<a name="l00793"></a>00793
|
||
<a name="l00794"></a>00794 <span class="keyword">union </span>{
|
||
<a name="l00795"></a>00795 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00796"></a>00796 <span class="keyword">struct </span>{
|
||
<a name="l00797"></a>00797 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ESEL15:2; <span class="comment">/* External IRQ Input Select x */</span>
|
||
<a name="l00798"></a>00798 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ESEL14:2; <span class="comment">/* External IRQ Input Select x */</span>
|
||
<a name="l00799"></a>00799 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ESEL13:2; <span class="comment">/* External IRQ Input Select x */</span>
|
||
<a name="l00800"></a>00800 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ESEL12:2; <span class="comment">/* External IRQ Input Select x */</span>
|
||
<a name="l00801"></a>00801 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ESEL11:2; <span class="comment">/* External IRQ Input Select x */</span>
|
||
<a name="l00802"></a>00802 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ESEL10:2; <span class="comment">/* External IRQ Input Select x */</span>
|
||
<a name="l00803"></a>00803 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ESEL9:2; <span class="comment">/* External IRQ Input Select x */</span>
|
||
<a name="l00804"></a>00804 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ESEL8:2; <span class="comment">/* External IRQ Input Select x */</span>
|
||
<a name="l00805"></a>00805 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ESEL7:2; <span class="comment">/* External IRQ Input Select x */</span>
|
||
<a name="l00806"></a>00806 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ESEL6:2; <span class="comment">/* External IRQ Input Select x */</span>
|
||
<a name="l00807"></a>00807 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ESEL5:2; <span class="comment">/* External IRQ Input Select x */</span>
|
||
<a name="l00808"></a>00808 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ESEL4:2; <span class="comment">/* External IRQ Input Select x */</span>
|
||
<a name="l00809"></a>00809 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ESEL3:2; <span class="comment">/* External IRQ Input Select x */</span>
|
||
<a name="l00810"></a>00810 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ESEL2:2; <span class="comment">/* External IRQ Input Select x */</span>
|
||
<a name="l00811"></a>00811 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ESEL1:2; <span class="comment">/* External IRQ Input Select x */</span>
|
||
<a name="l00812"></a>00812 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ESEL0:2; <span class="comment">/* External IRQ Input Select x */</span>
|
||
<a name="l00813"></a>00813 } B;
|
||
<a name="l00814"></a>00814 } EIISR; <span class="comment">/* External IRQ Input Select Register (EIISR) <URM>SIU_EIISR</URM> @baseaddress + 0x908 */</span>
|
||
<a name="l00815"></a>00815
|
||
<a name="l00816"></a>00816 <span class="keyword">union </span>{
|
||
<a name="l00817"></a>00817 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00818"></a>00818 <span class="keyword">struct </span>{
|
||
<a name="l00819"></a>00819 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:8; <span class="comment">/* reserved in MPC563xM */</span>
|
||
<a name="l00820"></a>00820 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SINSELB:2; <span class="comment">/* DSPI_B Data Input Select <URM>SIN-SELB</URM> */</span>
|
||
<a name="l00821"></a>00821 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SSSELB:2; <span class="comment">/* DSPI_B Slave Select Input Select <URM>SS-SELB</URM> */</span>
|
||
<a name="l00822"></a>00822 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SCKSELB:2; <span class="comment">/* DSPI_B Clock Input Select <URM>SCK-SELB</URM> */</span>
|
||
<a name="l00823"></a>00823 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TRIGSELB:2; <span class="comment">/* DSPI_B Trigger Input Select <URM>TRIG-SELB</URM> */</span>
|
||
<a name="l00824"></a>00824 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SINSELC:2; <span class="comment">/* DSPI_C Data Input Select <URM>SIN-SELC</URM> */</span>
|
||
<a name="l00825"></a>00825 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SSSELC:2; <span class="comment">/* DSPI_C Slave Select Input Select <URM>SSSELC</URM> */</span>
|
||
<a name="l00826"></a>00826 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SCKSELC:2; <span class="comment">/* DSPI_C Clock Input Select <URM>SCK-SELC</URM> */</span>
|
||
<a name="l00827"></a>00827 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TRIGSELC:2; <span class="comment">/* DSPI_C Trigger Input Select <URM>TRIG-SELC</URM> */</span>
|
||
<a name="l00828"></a>00828 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:8; <span class="comment">/* reserved in MPC563xM */</span>
|
||
<a name="l00829"></a>00829 } B;
|
||
<a name="l00830"></a>00830 } DISR; <span class="comment">/* DSPI Input Select Register (DISR) <URM>SIU_DISR</URM> @baseaddress + 0x90c */</span>
|
||
<a name="l00831"></a>00831
|
||
<a name="l00832"></a>00832 <span class="keyword">union </span>{
|
||
<a name="l00833"></a>00833 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00834"></a>00834 <span class="keyword">struct </span>{
|
||
<a name="l00835"></a>00835 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:2; <span class="comment">/* */</span>
|
||
<a name="l00836"></a>00836 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ETSEL5:5; <span class="comment">/* eQADC queue X Enhanced Trigger Selection <URM>eTSEL5</URM> */</span>
|
||
<a name="l00837"></a>00837 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ETSEL4:5; <span class="comment">/* eQADC queue X Enhanced Trigger Selection <URM>eTSEL4</URM> */</span>
|
||
<a name="l00838"></a>00838 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ETSEL3:5; <span class="comment">/* eQADC queue X Enhanced Trigger Selection <URM>eTSEL3</URM> */</span>
|
||
<a name="l00839"></a>00839 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ETSEL2:5; <span class="comment">/* eQADC queue X Enhanced Trigger Selection <URM>eTSEL2</URM> */</span>
|
||
<a name="l00840"></a>00840 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ETSEL1:5; <span class="comment">/* eQADC queue X Enhanced Trigger Selection <URM>eTSEL1</URM> */</span>
|
||
<a name="l00841"></a>00841 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ETSEL0:5; <span class="comment">/* eQADC queue X Enhanced Trigger Selection <URM>eTSEL0</URM> */</span>
|
||
<a name="l00842"></a>00842 } B;
|
||
<a name="l00843"></a>00843 } ISEL3; <span class="comment">/* MUX Select Register 3 (ISEL3) (new in MPC563xM) <URM>SIU_ISEL3</URM> @baseaddress + 0x920 */</span>
|
||
<a name="l00844"></a>00844
|
||
<a name="l00845"></a>00845 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> SIU_reserverd_214[4];
|
||
<a name="l00846"></a>00846
|
||
<a name="l00847"></a>00847 <span class="keyword">union </span>{
|
||
<a name="l00848"></a>00848 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00849"></a>00849 <span class="keyword">struct </span>{
|
||
<a name="l00850"></a>00850 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:11; <span class="comment">/* */</span>
|
||
<a name="l00851"></a>00851 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ESEL5:1; <span class="comment">/* <URM>eSEL5</URM> */</span>
|
||
<a name="l00852"></a>00852 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:3; <span class="comment">/* */</span>
|
||
<a name="l00853"></a>00853 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ESEL4:1; <span class="comment">/* <URM>eSEL4</URM> */</span>
|
||
<a name="l00854"></a>00854 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:3; <span class="comment">/* */</span>
|
||
<a name="l00855"></a>00855 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ESEL3:1; <span class="comment">/* <URM>eSEL3</URM> */</span>
|
||
<a name="l00856"></a>00856 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:3; <span class="comment">/* */</span>
|
||
<a name="l00857"></a>00857 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ESEL2:1; <span class="comment">/* <URM>eSEL2</URM> */</span>
|
||
<a name="l00858"></a>00858 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:3; <span class="comment">/* */</span>
|
||
<a name="l00859"></a>00859 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ESEL1:1; <span class="comment">/* <URM>eSEL1</URM> */</span>
|
||
<a name="l00860"></a>00860 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:3; <span class="comment">/* */</span>
|
||
<a name="l00861"></a>00861 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ESEL0:1; <span class="comment">/* <URM>eSEL0</URM> */</span>
|
||
<a name="l00862"></a>00862 } B;
|
||
<a name="l00863"></a>00863 } ISEL8; <span class="comment">/* MUX Select Register 8 (ISEL8) (new in MPC563xM) <URM>SIU_ISEL8</URM> @baseaddress + 0x924 */</span>
|
||
<a name="l00864"></a>00864
|
||
<a name="l00865"></a>00865 <span class="keyword">union </span>{
|
||
<a name="l00866"></a>00866 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00867"></a>00867 <span class="keyword">struct </span>{
|
||
<a name="l00868"></a>00868 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:27; <span class="comment">/* */</span>
|
||
<a name="l00869"></a>00869 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ETSEL0A:5; <span class="comment">/* <URM>eTSEL0A</URM> */</span>
|
||
<a name="l00870"></a>00870 } B;
|
||
<a name="l00871"></a>00871 } ISEL9; <span class="comment">/* MUX Select Register 9(ISEL9) <URM>SIU_ISEL9</URM> @baseaddress + 0x980 */</span>
|
||
<a name="l00872"></a>00872
|
||
<a name="l00873"></a>00873 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> SIU_reserverd_230[22];
|
||
<a name="l00874"></a>00874
|
||
<a name="l00875"></a>00875 <span class="keyword">union </span>{
|
||
<a name="l00876"></a>00876 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00877"></a>00877 <span class="keyword">struct </span>{
|
||
<a name="l00878"></a>00878 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:14; <span class="comment">/* */</span>
|
||
<a name="l00879"></a>00879 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MATCH:1; <span class="comment">/* Compare Register Match */</span>
|
||
<a name="l00880"></a>00880 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DISNEX:1; <span class="comment">/* Disable Nexus */</span>
|
||
<a name="l00881"></a>00881 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:14; <span class="comment">/* */</span>
|
||
<a name="l00882"></a>00882 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CRSE:1; <span class="comment">/* Calibration Reflection Suppression Enable (new in MPC563xM) */</span>
|
||
<a name="l00883"></a>00883 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* */</span>
|
||
<a name="l00884"></a>00884 } B;
|
||
<a name="l00885"></a>00885 } CCR; <span class="comment">/* Chip Configuration Register (CCR) <URM>SIU_CCR</URM> @baseaddress + 0x984 */</span>
|
||
<a name="l00886"></a>00886
|
||
<a name="l00887"></a>00887 <span class="keyword">union </span>{
|
||
<a name="l00888"></a>00888 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00889"></a>00889 <span class="keyword">struct </span>{
|
||
<a name="l00890"></a>00890 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:28; <span class="comment">/* The ENGDIV bit is reserved in MPC563xM */</span>
|
||
<a name="l00891"></a>00891 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EBTS:1; <span class="comment">/* External Bus Tap Select */</span>
|
||
<a name="l00892"></a>00892 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* */</span>
|
||
<a name="l00893"></a>00893 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EBDF:2; <span class="comment">/* External Bus Division Factor */</span>
|
||
<a name="l00894"></a>00894 } B;
|
||
<a name="l00895"></a>00895 } ECCR; <span class="comment">/* External Clock Control Register (ECCR) <URM>SIU_ECCR</URM> @baseaddress + 0x988 */</span>
|
||
<a name="l00896"></a>00896
|
||
<a name="l00897"></a>00897 <span class="keyword">union </span>{
|
||
<a name="l00898"></a>00898 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00899"></a>00899 } CARH; <span class="comment">/* Compare A High Register (CARH) <URM>SIU_CMPAH</URM> @baseaddress + 0x98C */</span>
|
||
<a name="l00900"></a>00900
|
||
<a name="l00901"></a>00901 <span class="keyword">union </span>{
|
||
<a name="l00902"></a>00902 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00903"></a>00903 } CARL; <span class="comment">/* Compare A Low Register (CARL) <URM>SIU_CMPAL</URM> @baseaddress + 0x990 */</span>
|
||
<a name="l00904"></a>00904
|
||
<a name="l00905"></a>00905 <span class="keyword">union </span>{
|
||
<a name="l00906"></a>00906 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00907"></a>00907 } CBRH; <span class="comment">/* Compare B High Register (CBRH) <URM>SIU_CMPBH</URM> @baseaddress + 0x994 */</span>
|
||
<a name="l00908"></a>00908
|
||
<a name="l00909"></a>00909 <span class="keyword">union </span>{
|
||
<a name="l00910"></a>00910 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00911"></a>00911 } CBRL; <span class="comment">/* Compare B Low Register (CBRL) <URM>SIU_CMPBL</URM> @baseaddress + 0x9A0 */</span>
|
||
<a name="l00912"></a>00912
|
||
<a name="l00913"></a>00913 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> SIU_reserverd_250[2];
|
||
<a name="l00914"></a>00914
|
||
<a name="l00915"></a>00915 <span class="keyword">union </span>{
|
||
<a name="l00916"></a>00916 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00917"></a>00917 <span class="keyword">struct </span>{
|
||
<a name="l00918"></a>00918 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:27; <span class="comment">/* Reserved */</span>
|
||
<a name="l00919"></a>00919 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BYPASS:1; <span class="comment">/* Bypass bit <URM>BY-PASS</URM> */</span>
|
||
<a name="l00920"></a>00920 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SYSCLKDIV:2; <span class="comment">/* System Clock Divide <URM>SYS-CLKDIV</URM> */</span>
|
||
<a name="l00921"></a>00921 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:2; <span class="comment">/* Reserved */</span>
|
||
<a name="l00922"></a>00922 } B;
|
||
<a name="l00923"></a>00923 } SYSDIV; <span class="comment">/* System Clock Register (SYSDIV) (new in MPC563xM) <URM>SIU_SYSDIV</URM> @baseaddress + 0x9A4 */</span>
|
||
<a name="l00924"></a>00924
|
||
<a name="l00925"></a>00925 <span class="keyword">union </span>{
|
||
<a name="l00926"></a>00926 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00927"></a>00927 <span class="keyword">struct </span>{
|
||
<a name="l00928"></a>00928 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CPUSTP:1; <span class="comment">/* CPU stop request. When asserted, a stop request is sent to the following modules: */</span>
|
||
<a name="l00929"></a>00929 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:2; <span class="comment">/* Reserved */</span>
|
||
<a name="l00930"></a>00930 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SWTSTP:1; <span class="comment">/* SWT stop request. When asserted, a stop request is sent to the Software Watchdog */</span>
|
||
<a name="l00931"></a>00931 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* Reserved */</span>
|
||
<a name="l00932"></a>00932 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TPUSTP:1; <span class="comment">/* eTPU stop request. When asserted, a stop request is sent to the eTPU module. */</span>
|
||
<a name="l00933"></a>00933 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> NPCSTP:1; <span class="comment">/* Nexus stop request. When asserted, a stop request is sent to the Nexus Controller. */</span>
|
||
<a name="l00934"></a>00934 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EBISTP:1; <span class="comment">/* EBI stop request. When asserted, a stop request is sent to the external bus */</span>
|
||
<a name="l00935"></a>00935 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ADCSTP:1; <span class="comment">/* eQADC stop request. When asserted, a stop request is sent to the eQADC module. */</span>
|
||
<a name="l00936"></a>00936 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* Reserved */</span>
|
||
<a name="l00937"></a>00937 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MIOSSTP:1; <span class="comment">/* Stop mode request */</span>
|
||
<a name="l00938"></a>00938 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DFILSTP:1; <span class="comment">/* Decimation filter stop request. When asserted, a stop request is sent to the */</span>
|
||
<a name="l00939"></a>00939 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* Reserved */</span>
|
||
<a name="l00940"></a>00940 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PITSTP:1; <span class="comment">/* PIT stop request. When asserted, a stop request is sent to the periodical internal */</span>
|
||
<a name="l00941"></a>00941 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:3; <span class="comment">/* Reserved */</span>
|
||
<a name="l00942"></a>00942 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CNCSTP:1; <span class="comment">/* FlexCAN C stop request. When asserted, a stop request is sent to the FlexCAN C */</span>
|
||
<a name="l00943"></a>00943 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* Reserved */</span>
|
||
<a name="l00944"></a>00944 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CNASTP:1; <span class="comment">/* FlexCAN A stop request. When asserted, a stop request is sent to the FlexCAN A */</span>
|
||
<a name="l00945"></a>00945 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* Reserved */</span>
|
||
<a name="l00946"></a>00946 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SPICSTP:1; <span class="comment">/* DSPI C stop request. When asserted, a stop request is sent to the DSPI C. */</span>
|
||
<a name="l00947"></a>00947 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SPIBSTP:1; <span class="comment">/* DSPI B stop request. When asserted, a stop request is sent to the DSPI B. */</span>
|
||
<a name="l00948"></a>00948 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:7; <span class="comment">/* Reserved */</span>
|
||
<a name="l00949"></a>00949 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SCIBSTP:1; <span class="comment">/* eSCI B stop request. When asserted, a stop request is sent to the eSCI B module. */</span>
|
||
<a name="l00950"></a>00950 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SCIASTP:1; <span class="comment">/* eSCI A stop request. When asserted, a stop request is sent to the eSCIA module. */</span>
|
||
<a name="l00951"></a>00951 } B;
|
||
<a name="l00952"></a>00952 } HLT; <span class="comment">/* Halt Register (HLT) (new in MPC563xM) <URM>SIU_HLT</URM> @baseaddress + 0x9A8 */</span>
|
||
<a name="l00953"></a>00953
|
||
<a name="l00954"></a>00954 <span class="keyword">union </span>{
|
||
<a name="l00955"></a>00955 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00956"></a>00956 <span class="keyword">struct </span>{
|
||
<a name="l00957"></a>00957 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CPUACK:1; <span class="comment">/* CPU stop acknowledge. When asserted, indicates that a stop acknowledge was */</span>
|
||
<a name="l00958"></a>00958 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:2; <span class="comment">/* Reserved */</span>
|
||
<a name="l00959"></a>00959 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SWTACK:1; <span class="comment">/* SWT stop acknowledge. When asserted, indicates that a stop acknowledge was */</span>
|
||
<a name="l00960"></a>00960 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* Reserved */</span>
|
||
<a name="l00961"></a>00961 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TPUACK:1; <span class="comment">/* eTPU stop acknowledge. When asserted, indicates that a stop acknowledge was */</span>
|
||
<a name="l00962"></a>00962 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> NPCACK:1; <span class="comment">/* Nexus stop acknowledge. When asserted, indicates that a stop acknowledge was */</span>
|
||
<a name="l00963"></a>00963 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EBIACK:1; <span class="comment">/* EBI stop acknowledge. When asserted, indicates that a stop acknowledge was */</span>
|
||
<a name="l00964"></a>00964 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ADCACK:1; <span class="comment">/* eQADC stop acknowledge. When asserted, indicates that a stop acknowledge was */</span>
|
||
<a name="l00965"></a>00965 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* Reserved */</span>
|
||
<a name="l00966"></a>00966 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MIOSACK:1; <span class="comment">/* eMIOS stop acknowledge. When asserted, indicates that a stop acknowledge was */</span>
|
||
<a name="l00967"></a>00967 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DFILACK:1; <span class="comment">/* Decimation filter stop acknowledge. When asserted, indicates that a stop */</span>
|
||
<a name="l00968"></a>00968 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* Reserved */</span>
|
||
<a name="l00969"></a>00969 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PITACK:1; <span class="comment">/* PIT stop acknowledge. When asserted, indicates that a stop acknowledge was */</span>
|
||
<a name="l00970"></a>00970 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:3; <span class="comment">/* Reserved */</span>
|
||
<a name="l00971"></a>00971 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CNCACK:1; <span class="comment">/* FlexCAN C stop acknowledge. When asserted, indicates that a stop acknowledge */</span>
|
||
<a name="l00972"></a>00972 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* Reserved */</span>
|
||
<a name="l00973"></a>00973 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CNAACK:1; <span class="comment">/* FlexCAN A stop acknowledge. When asserted, indicates that a stop acknowledge */</span>
|
||
<a name="l00974"></a>00974 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* Reserved */</span>
|
||
<a name="l00975"></a>00975 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SPICACK:1; <span class="comment">/* DSPI C stop acknowledge. When asserted, indicates that a stop acknowledge was */</span>
|
||
<a name="l00976"></a>00976 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SPIBACK:1; <span class="comment">/* DSPI B stop acknowledge. When asserted, indicates that a stop acknowledge was */</span>
|
||
<a name="l00977"></a>00977 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:7; <span class="comment">/* Reserved */</span>
|
||
<a name="l00978"></a>00978 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SCIBACK:1; <span class="comment">/* eSCI B stop acknowledge */</span>
|
||
<a name="l00979"></a>00979 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SCIAACK:1; <span class="comment">/* eSCI A stop acknowledge. */</span>
|
||
<a name="l00980"></a>00980 } B;
|
||
<a name="l00981"></a>00981 } HLTACK; <span class="comment">/* Halt Acknowledge Register (HLTACK) (new in MPC563xM) <URM>SIU_HLTACK</URM> @baseaddress + 0x9ac */</span>
|
||
<a name="l00982"></a>00982
|
||
<a name="l00983"></a>00983 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> SIU_reserved3[21];
|
||
<a name="l00984"></a>00984
|
||
<a name="l00985"></a>00985 }; <span class="comment">/* end of SIU_tag */</span>
|
||
<a name="l00986"></a>00986 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l00987"></a>00987 <span class="comment">/* MODULE : EMIOS */</span>
|
||
<a name="l00988"></a>00988 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l00989"></a>00989 <span class="keyword">struct </span>EMIOS_tag {
|
||
<a name="l00990"></a>00990 <span class="keyword">union </span>{
|
||
<a name="l00991"></a>00991 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l00992"></a>00992 <span class="keyword">struct </span>{
|
||
<a name="l00993"></a>00993 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DOZEEN:1; <span class="comment">/* new in MPC563xM */</span>
|
||
<a name="l00994"></a>00994 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MDIS:1;
|
||
<a name="l00995"></a>00995 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> FRZ:1;
|
||
<a name="l00996"></a>00996 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> GTBE:1;
|
||
<a name="l00997"></a>00997 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ETB:1;
|
||
<a name="l00998"></a>00998 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> GPREN:1;
|
||
<a name="l00999"></a>00999 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:6;
|
||
<a name="l01000"></a>01000 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SRV:4;
|
||
<a name="l01001"></a>01001 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> GPRE:8;
|
||
<a name="l01002"></a>01002 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:8;
|
||
<a name="l01003"></a>01003 } B;
|
||
<a name="l01004"></a>01004 } MCR; <span class="comment">/* Module Configuration Register <URM>EMIOSMCR</URM> */</span>
|
||
<a name="l01005"></a>01005
|
||
<a name="l01006"></a>01006 <span class="keyword">union </span>{
|
||
<a name="l01007"></a>01007 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01008"></a>01008 <span class="keyword">struct </span>{
|
||
<a name="l01009"></a>01009 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:8;
|
||
<a name="l01010"></a>01010 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> F23:1;
|
||
<a name="l01011"></a>01011 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> F22:1;
|
||
<a name="l01012"></a>01012 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> F21:1;
|
||
<a name="l01013"></a>01013 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> F20:1;
|
||
<a name="l01014"></a>01014 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> F19:1;
|
||
<a name="l01015"></a>01015 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> F18:1;
|
||
<a name="l01016"></a>01016 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> F17:1;
|
||
<a name="l01017"></a>01017 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> F16:1;
|
||
<a name="l01018"></a>01018 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> F15:1;
|
||
<a name="l01019"></a>01019 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> F14:1;
|
||
<a name="l01020"></a>01020 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> F13:1;
|
||
<a name="l01021"></a>01021 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> F12:1;
|
||
<a name="l01022"></a>01022 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> F11:1;
|
||
<a name="l01023"></a>01023 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> F10:1;
|
||
<a name="l01024"></a>01024 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> F9:1;
|
||
<a name="l01025"></a>01025 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> F8:1;
|
||
<a name="l01026"></a>01026 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> F7:1;
|
||
<a name="l01027"></a>01027 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> F6:1;
|
||
<a name="l01028"></a>01028 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> F5:1;
|
||
<a name="l01029"></a>01029 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> F4:1;
|
||
<a name="l01030"></a>01030 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> F3:1;
|
||
<a name="l01031"></a>01031 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> F2:1;
|
||
<a name="l01032"></a>01032 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> F1:1;
|
||
<a name="l01033"></a>01033 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> F0:1;
|
||
<a name="l01034"></a>01034 } B;
|
||
<a name="l01035"></a>01035 } GFR; <span class="comment">/* Global FLAG Register <URM>EMIOSGFLAG</URM> */</span>
|
||
<a name="l01036"></a>01036
|
||
<a name="l01037"></a>01037 <span class="keyword">union </span>{
|
||
<a name="l01038"></a>01038 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01039"></a>01039 <span class="keyword">struct </span>{
|
||
<a name="l01040"></a>01040 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:8;
|
||
<a name="l01041"></a>01041 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OU23:1;
|
||
<a name="l01042"></a>01042 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OU22:1;
|
||
<a name="l01043"></a>01043 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OU21:1;
|
||
<a name="l01044"></a>01044 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OU20:1;
|
||
<a name="l01045"></a>01045 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OU19:1;
|
||
<a name="l01046"></a>01046 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OU18:1;
|
||
<a name="l01047"></a>01047 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OU17:1;
|
||
<a name="l01048"></a>01048 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OU16:1;
|
||
<a name="l01049"></a>01049 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OU15:1;
|
||
<a name="l01050"></a>01050 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OU14:1;
|
||
<a name="l01051"></a>01051 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OU13:1;
|
||
<a name="l01052"></a>01052 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OU12:1;
|
||
<a name="l01053"></a>01053 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OU11:1;
|
||
<a name="l01054"></a>01054 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OU10:1;
|
||
<a name="l01055"></a>01055 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OU9:1;
|
||
<a name="l01056"></a>01056 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OU8:1;
|
||
<a name="l01057"></a>01057 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OU7:1;
|
||
<a name="l01058"></a>01058 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OU6:1;
|
||
<a name="l01059"></a>01059 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OU5:1;
|
||
<a name="l01060"></a>01060 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OU4:1;
|
||
<a name="l01061"></a>01061 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OU3:1;
|
||
<a name="l01062"></a>01062 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OU2:1;
|
||
<a name="l01063"></a>01063 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OU1:1;
|
||
<a name="l01064"></a>01064 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OU0:1;
|
||
<a name="l01065"></a>01065 } B;
|
||
<a name="l01066"></a>01066 } OUDR; <span class="comment">/* Output Update Disable Register <URM>EMIOSOUDIS</URM> */</span>
|
||
<a name="l01067"></a>01067
|
||
<a name="l01068"></a>01068 <span class="keyword">union </span>{
|
||
<a name="l01069"></a>01069 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01070"></a>01070 <span class="keyword">struct </span>{
|
||
<a name="l01071"></a>01071 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:8; <span class="comment">/* */</span>
|
||
<a name="l01072"></a>01072 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CHDIS23:1; <span class="comment">/* Enable Channel [n] bit */</span>
|
||
<a name="l01073"></a>01073 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CHDIS22:1; <span class="comment">/* Enable Channel [n] bit */</span>
|
||
<a name="l01074"></a>01074 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CHDIS21:1; <span class="comment">/* Enable Channel [n] bit */</span>
|
||
<a name="l01075"></a>01075 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CHDIS20:1; <span class="comment">/* Enable Channel [n] bit */</span>
|
||
<a name="l01076"></a>01076 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CHDIS19:1; <span class="comment">/* Enable Channel [n] bit */</span>
|
||
<a name="l01077"></a>01077 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CHDIS18:1; <span class="comment">/* Enable Channel [n] bit */</span>
|
||
<a name="l01078"></a>01078 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CHDIS17:1; <span class="comment">/* Enable Channel [n] bit */</span>
|
||
<a name="l01079"></a>01079 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CHDIS16:1; <span class="comment">/* Enable Channel [n] bit */</span>
|
||
<a name="l01080"></a>01080 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CHDIS15:1; <span class="comment">/* Enable Channel [n] bit */</span>
|
||
<a name="l01081"></a>01081 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CHDIS14:1; <span class="comment">/* Enable Channel [n] bit */</span>
|
||
<a name="l01082"></a>01082 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CHDIS13:1; <span class="comment">/* Enable Channel [n] bit */</span>
|
||
<a name="l01083"></a>01083 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CHDIS12:1; <span class="comment">/* Enable Channel [n] bit */</span>
|
||
<a name="l01084"></a>01084 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CHDIS11:1; <span class="comment">/* Enable Channel [n] bit */</span>
|
||
<a name="l01085"></a>01085 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CHDIS10:1; <span class="comment">/* Enable Channel [n] bit */</span>
|
||
<a name="l01086"></a>01086 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CHDIS9:1; <span class="comment">/* Enable Channel [n] bit */</span>
|
||
<a name="l01087"></a>01087 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CHDIS8:1; <span class="comment">/* Enable Channel [n] bit */</span>
|
||
<a name="l01088"></a>01088 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CHDIS7:1; <span class="comment">/* Enable Channel [n] bit */</span>
|
||
<a name="l01089"></a>01089 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CHDIS6:1; <span class="comment">/* Enable Channel [n] bit */</span>
|
||
<a name="l01090"></a>01090 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CHDIS5:1; <span class="comment">/* Enable Channel [n] bit */</span>
|
||
<a name="l01091"></a>01091 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CHDIS4:1; <span class="comment">/* Enable Channel [n] bit */</span>
|
||
<a name="l01092"></a>01092 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CHDIS3:1; <span class="comment">/* Enable Channel [n] bit */</span>
|
||
<a name="l01093"></a>01093 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CHDIS2:1; <span class="comment">/* Enable Channel [n] bit */</span>
|
||
<a name="l01094"></a>01094 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CHDIS1:1; <span class="comment">/* Enable Channel [n] bit */</span>
|
||
<a name="l01095"></a>01095 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CHDIS0:1; <span class="comment">/* Enable Channel [n] bit */</span>
|
||
<a name="l01096"></a>01096 } B;
|
||
<a name="l01097"></a>01097 } UCDIS; <span class="comment">/* Disable Channel (EMIOSUCDIS) <URM>EMIOSUCDIS</URM> (new in MPC563xM) @baseaddress + 0x0C */</span>
|
||
<a name="l01098"></a>01098
|
||
<a name="l01099"></a>01099 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> EMIOS_reserverd_30[4];
|
||
<a name="l01100"></a>01100
|
||
<a name="l01101"></a>01101 <span class="keyword">struct </span>{
|
||
<a name="l01102"></a>01102 <span class="keyword">union </span>{
|
||
<a name="l01103"></a>01103 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R; <span class="comment">/* Channel A Data Register */</span>
|
||
<a name="l01104"></a>01104 } CADR; <span class="comment">/* <URM>EMIOSA</URM> */</span>
|
||
<a name="l01105"></a>01105
|
||
<a name="l01106"></a>01106 <span class="keyword">union </span>{
|
||
<a name="l01107"></a>01107 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R; <span class="comment">/* Channel B Data Register */</span>
|
||
<a name="l01108"></a>01108 } CBDR; <span class="comment">/* <URM>EMIOSB</URM> */</span>
|
||
<a name="l01109"></a>01109
|
||
<a name="l01110"></a>01110 <span class="keyword">union </span>{
|
||
<a name="l01111"></a>01111 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R; <span class="comment">/* Channel Counter Register */</span>
|
||
<a name="l01112"></a>01112 } CCNTR; <span class="comment">/* <URM>EMIOSCNT</URM> */</span>
|
||
<a name="l01113"></a>01113
|
||
<a name="l01114"></a>01114 <span class="keyword">union </span>{
|
||
<a name="l01115"></a>01115 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01116"></a>01116 <span class="keyword">struct </span>{
|
||
<a name="l01117"></a>01117 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> FREN:1;
|
||
<a name="l01118"></a>01118 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ODIS:1;
|
||
<a name="l01119"></a>01119 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ODISSL:2;
|
||
<a name="l01120"></a>01120 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> UCPRE:2;
|
||
<a name="l01121"></a>01121 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> UCPREN:1;
|
||
<a name="l01122"></a>01122 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DMA:1;
|
||
<a name="l01123"></a>01123 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1;
|
||
<a name="l01124"></a>01124 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IF:4;
|
||
<a name="l01125"></a>01125 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> FCK:1;
|
||
<a name="l01126"></a>01126 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> FEN:1;
|
||
<a name="l01127"></a>01127 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:3;
|
||
<a name="l01128"></a>01128 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> FORCMA:1;
|
||
<a name="l01129"></a>01129 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> FORCMB:1;
|
||
<a name="l01130"></a>01130 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1;
|
||
<a name="l01131"></a>01131 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BSL:2;
|
||
<a name="l01132"></a>01132 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EDSEL:1;
|
||
<a name="l01133"></a>01133 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EDPOL:1;
|
||
<a name="l01134"></a>01134 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MODE:7;
|
||
<a name="l01135"></a>01135 } B;
|
||
<a name="l01136"></a>01136 } CCR; <span class="comment">/* Channel Control Register <URM>EMIOSC</URM> */</span>
|
||
<a name="l01137"></a>01137
|
||
<a name="l01138"></a>01138 <span class="keyword">union </span>{
|
||
<a name="l01139"></a>01139 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01140"></a>01140 <span class="keyword">struct </span>{
|
||
<a name="l01141"></a>01141 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OVR:1;
|
||
<a name="l01142"></a>01142 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:15;
|
||
<a name="l01143"></a>01143 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OVFL:1;
|
||
<a name="l01144"></a>01144 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:12;
|
||
<a name="l01145"></a>01145 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> UCIN:1;
|
||
<a name="l01146"></a>01146 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> UCOUT:1;
|
||
<a name="l01147"></a>01147 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> FLAG:1;
|
||
<a name="l01148"></a>01148 } B;
|
||
<a name="l01149"></a>01149 } CSR; <span class="comment">/* Channel Status Register <URM>EMIOSS</URM> */</span>
|
||
<a name="l01150"></a>01150
|
||
<a name="l01151"></a>01151 <span class="keyword">union </span>{
|
||
<a name="l01152"></a>01152 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R; <span class="comment">/* Alternate Channel A Data Register */</span>
|
||
<a name="l01153"></a>01153 } ALTA; <span class="comment">/* new in MPC563xM <URM>EMIOSALTA</URM> */</span>
|
||
<a name="l01154"></a>01154
|
||
<a name="l01155"></a>01155 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> emios_channel_reserved[2];
|
||
<a name="l01156"></a>01156
|
||
<a name="l01157"></a>01157 } CH[24];
|
||
<a name="l01158"></a>01158
|
||
<a name="l01159"></a>01159 }; <span class="comment">/* end of EMIOS_tag */</span>
|
||
<a name="l01160"></a>01160 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l01161"></a>01161 <span class="comment">/* MODULE : ETPU */</span>
|
||
<a name="l01162"></a>01162 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l01163"></a>01163 <span class="keyword">struct </span>ETPU_tag { <span class="comment">/* offset 0x0000 */</span>
|
||
<a name="l01164"></a>01164 <span class="keyword">union </span>{ <span class="comment">/* eTPU module configuration register@baseaddress + 0x00 */</span>
|
||
<a name="l01165"></a>01165 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01166"></a>01166 <span class="keyword">struct </span>{
|
||
<a name="l01167"></a>01167 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> GEC:1; <span class="comment">/* Global Exception Clear */</span>
|
||
<a name="l01168"></a>01168 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SDMERR:1; <span class="comment">/* */</span>
|
||
<a name="l01169"></a>01169 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WDTOA:1; <span class="comment">/* */</span>
|
||
<a name="l01170"></a>01170 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WDTOB:1; <span class="comment">/* */</span>
|
||
<a name="l01171"></a>01171 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MGE1:1; <span class="comment">/* <URM>MGEA</URM> */</span>
|
||
<a name="l01172"></a>01172 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MGE2:1; <span class="comment">/* <URM>MGEB</URM> */</span>
|
||
<a name="l01173"></a>01173 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ILF1:1; <span class="comment">/* Invalid instruction flag eTPU A. <URM>ILFFA</URM> */</span>
|
||
<a name="l01174"></a>01174 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ILF2:1; <span class="comment">/* Invalid instruction flag eTPU B. <URM>ILFFB</URM> */</span>
|
||
<a name="l01175"></a>01175 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SCMERR:1; <span class="comment">/* . */</span>
|
||
<a name="l01176"></a>01176 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:2; <span class="comment">/* */</span>
|
||
<a name="l01177"></a>01177 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SCMSIZE:5; <span class="comment">/* Shared Code Memory size */</span>
|
||
<a name="l01178"></a>01178 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:4; <span class="comment">/* */</span>
|
||
<a name="l01179"></a>01179 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SCMMISC:1; <span class="comment">/* SCM MISC Flag */</span>
|
||
<a name="l01180"></a>01180 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SCMMISF:1; <span class="comment">/* SCM MISC Flag */</span>
|
||
<a name="l01181"></a>01181 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SCMMISEN:1; <span class="comment">/* SCM MISC Enable */</span>
|
||
<a name="l01182"></a>01182 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:2; <span class="comment">/* */</span>
|
||
<a name="l01183"></a>01183 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> VIS:1; <span class="comment">/* SCM Visability */</span>
|
||
<a name="l01184"></a>01184 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:5; <span class="comment">/* */</span>
|
||
<a name="l01185"></a>01185 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> GTBE:1; <span class="comment">/* Global Time Base Enable */</span>
|
||
<a name="l01186"></a>01186 } B;
|
||
<a name="l01187"></a>01187 } MCR; <span class="comment">/* <URM>ETPU_MCR</URM> */</span>
|
||
<a name="l01188"></a>01188
|
||
<a name="l01189"></a>01189 <span class="comment">/* offset 0x0004 */</span>
|
||
<a name="l01190"></a>01190 <span class="keyword">union </span>{ <span class="comment">/* eTPU coherent dual-parameter controller register@baseaddress + 0x04 */</span>
|
||
<a name="l01191"></a>01191 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01192"></a>01192 <span class="keyword">struct </span>{
|
||
<a name="l01193"></a>01193 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> STS:1; <span class="comment">/* Start Status bit */</span>
|
||
<a name="l01194"></a>01194 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CTBASE:5; <span class="comment">/* Channel Transfer Base */</span>
|
||
<a name="l01195"></a>01195 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PBASE:10; <span class="comment">/* Parameter Buffer Base Address <URM>PBBASE</URM> */</span>
|
||
<a name="l01196"></a>01196 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PWIDTH:1; <span class="comment">/* Parameter Width */</span>
|
||
<a name="l01197"></a>01197 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PARAM0:7; <span class="comment">/* Channel Parameter 0 <URM>PARM0</URM> */</span>
|
||
<a name="l01198"></a>01198 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WR:1; <span class="comment">/* */</span>
|
||
<a name="l01199"></a>01199 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PARAM1:7; <span class="comment">/* Channel Parameter 1 <URM>PARM1</URM> */</span>
|
||
<a name="l01200"></a>01200 } B;
|
||
<a name="l01201"></a>01201 } CDCR; <span class="comment">/*<URM>ETPU_CDCR</URM> */</span>
|
||
<a name="l01202"></a>01202
|
||
<a name="l01203"></a>01203 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ETPU_reserved_0;
|
||
<a name="l01204"></a>01204
|
||
<a name="l01205"></a>01205 <span class="comment">/* offset 0x000C */</span>
|
||
<a name="l01206"></a>01206 <span class="keyword">union </span>{ <span class="comment">/* eTPU MISC Compare Register@baseaddress + 0x0c */</span>
|
||
<a name="l01207"></a>01207 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01208"></a>01208 <span class="keyword">struct </span>{
|
||
<a name="l01209"></a>01209 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ETPUMISCCMP:32; <span class="comment">/* Expected multiple input signature calculator compare register value. <URM>EMISCCMP</URM> */</span>
|
||
<a name="l01210"></a>01210 } B;
|
||
<a name="l01211"></a>01211 } MISCCMPR <span class="comment">/*<URM>ETPU_MISCCMPR</URM> */</span> ;
|
||
<a name="l01212"></a>01212
|
||
<a name="l01213"></a>01213 <span class="comment">/* offset 0x0010 */</span>
|
||
<a name="l01214"></a>01214 <span class="keyword">union </span>{ <span class="comment">/* eTPU SCM Off-Range Data Register@baseaddress + 0x10 */</span>
|
||
<a name="l01215"></a>01215 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01216"></a>01216 <span class="keyword">struct </span>{
|
||
<a name="l01217"></a>01217 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ETPUSCMOFFDATA:32; <span class="comment">/* SCM Off-range read data value. */</span>
|
||
<a name="l01218"></a>01218 } B;
|
||
<a name="l01219"></a>01219 } SCMOFFDATAR; <span class="comment">/*<URM>ETPU_SCMOFFDATAR</URM> */</span>
|
||
<a name="l01220"></a>01220
|
||
<a name="l01221"></a>01221 <span class="comment">/* offset 0x0014 */</span>
|
||
<a name="l01222"></a>01222 <span class="keyword">union </span>{ <span class="comment">/* eTPU Engine Configuration Register (ETPUA_ECR)@baseaddress + 0x14 */</span>
|
||
<a name="l01223"></a>01223 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01224"></a>01224 <span class="keyword">struct </span>{
|
||
<a name="l01225"></a>01225 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> FEND:1; <span class="comment">/* Force END */</span>
|
||
<a name="l01226"></a>01226 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MDIS:1; <span class="comment">/* Low power Stop */</span>
|
||
<a name="l01227"></a>01227 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* */</span>
|
||
<a name="l01228"></a>01228 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> STF:1; <span class="comment">/* Stop Flag */</span>
|
||
<a name="l01229"></a>01229 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:4; <span class="comment">/* */</span>
|
||
<a name="l01230"></a>01230 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> HLTF:1; <span class="comment">/* Halt Mode Flag */</span>
|
||
<a name="l01231"></a>01231 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:3; <span class="comment">/* */</span>
|
||
<a name="l01232"></a>01232 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> FCSS:1;
|
||
<a name="l01233"></a>01233 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> FPSCK:3; <span class="comment">/* Filter Prescaler Clock Control */</span>
|
||
<a name="l01234"></a>01234 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CDFC:2; <span class="comment">/* */</span>
|
||
<a name="l01235"></a>01235 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* */</span>
|
||
<a name="l01236"></a>01236 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERBA:5; <span class="comment">/* */</span>
|
||
<a name="l01237"></a>01237 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SPPDIS:1; <span class="comment">/* */</span>
|
||
<a name="l01238"></a>01238 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:2; <span class="comment">/* */</span>
|
||
<a name="l01239"></a>01239 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ETB:5; <span class="comment">/* Entry Table Base */</span>
|
||
<a name="l01240"></a>01240 } B;
|
||
<a name="l01241"></a>01241 } ECR_A; <span class="comment">/*<URM>ETPU_ECR</URM> */</span>
|
||
<a name="l01242"></a>01242
|
||
<a name="l01243"></a>01243 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ETPU_reserved_1[2];
|
||
<a name="l01244"></a>01244
|
||
<a name="l01245"></a>01245 <span class="comment">/* offset 0x0020 */</span>
|
||
<a name="l01246"></a>01246 <span class="keyword">union </span>{ <span class="comment">/* eTPU Time Base Configuration Register (ETPU_TBCR)@baseaddress + 0x20 */</span>
|
||
<a name="l01247"></a>01247 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01248"></a>01248 <span class="keyword">struct </span>{
|
||
<a name="l01249"></a>01249 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TCR2CTL:3; <span class="comment">/* TCR2 Clock/Gate Control */</span>
|
||
<a name="l01250"></a>01250 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TCRCF:2; <span class="comment">/* TCRCLK Signal Filter Control */</span>
|
||
<a name="l01251"></a>01251 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> AM:2; <span class="comment">/* Angle Mode */</span>
|
||
<a name="l01252"></a>01252 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:3; <span class="comment">/* */</span>
|
||
<a name="l01253"></a>01253 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TCR2P:6; <span class="comment">/* TCR2 Prescaler Control */</span>
|
||
<a name="l01254"></a>01254 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TCR1CTL:2; <span class="comment">/* TCR1 Clock/Gate Control */</span>
|
||
<a name="l01255"></a>01255 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TCR1CS:1; <span class="comment">/* */</span>
|
||
<a name="l01256"></a>01256 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:5; <span class="comment">/* */</span>
|
||
<a name="l01257"></a>01257 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TCR1P:8; <span class="comment">/* TCR1 Prescaler Control */</span>
|
||
<a name="l01258"></a>01258 } B;
|
||
<a name="l01259"></a>01259 } TBCR_A; <span class="comment">/*<URM>ETPU_TBCR</URM> */</span>
|
||
<a name="l01260"></a>01260
|
||
<a name="l01261"></a>01261 <span class="comment">/* offset 0x0024 */</span>
|
||
<a name="l01262"></a>01262 <span class="keyword">union </span>{ <span class="comment">/* eTPU Time Base 1 (TCR1) Visibility Register (ETPU_TB1R)@baseaddress + 0x24 */</span>
|
||
<a name="l01263"></a>01263 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01264"></a>01264 <span class="keyword">struct </span>{
|
||
<a name="l01265"></a>01265 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:8; <span class="comment">/* */</span>
|
||
<a name="l01266"></a>01266 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TCR1:24; <span class="comment">/* TCR1 value. Used on matches and captures. For more information, see the eTPU reference manual. */</span>
|
||
<a name="l01267"></a>01267 } B;
|
||
<a name="l01268"></a>01268 } TB1R_A; <span class="comment">/*<URM>ETPU_TB1R</URM> */</span>
|
||
<a name="l01269"></a>01269
|
||
<a name="l01270"></a>01270 <span class="comment">/* offset 0x0028 */</span>
|
||
<a name="l01271"></a>01271 <span class="keyword">union </span>{ <span class="comment">/* eTPU Time Base 2 (TCR2) Visibility Register (ETPU_TB2R)@baseaddress + 0x28 */</span>
|
||
<a name="l01272"></a>01272 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01273"></a>01273 <span class="keyword">struct </span>{
|
||
<a name="l01274"></a>01274 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:8; <span class="comment">/* */</span>
|
||
<a name="l01275"></a>01275 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TCR2:24; <span class="comment">/* TCR2 value. Used on matches and captures. For information on TCR2, see the eTPU reference manual. */</span>
|
||
<a name="l01276"></a>01276 } B;
|
||
<a name="l01277"></a>01277 } TB2R_A; <span class="comment">/*<URM>ETPU_TB2R</URM> */</span>
|
||
<a name="l01278"></a>01278
|
||
<a name="l01279"></a>01279 <span class="comment">/* offset 0x002C */</span>
|
||
<a name="l01280"></a>01280 <span class="keyword">union </span>{ <span class="comment">/* STAC Bus Configuration Register (ETPU_STACCR)@baseaddress + 0x2c */</span>
|
||
<a name="l01281"></a>01281 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01282"></a>01282 <span class="keyword">struct </span>{
|
||
<a name="l01283"></a>01283 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> REN1:1; <span class="comment">/* Resource Enable TCR1 */</span>
|
||
<a name="l01284"></a>01284 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RSC1:1; <span class="comment">/* Resource Control TCR1 */</span>
|
||
<a name="l01285"></a>01285 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:2; <span class="comment">/* */</span>
|
||
<a name="l01286"></a>01286 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SERVER_ID1:4; <span class="comment">/* */</span>
|
||
<a name="l01287"></a>01287 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:4; <span class="comment">/* */</span>
|
||
<a name="l01288"></a>01288 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SRV1:4; <span class="comment">/* Resource Server Slot */</span>
|
||
<a name="l01289"></a>01289 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> REN2:1; <span class="comment">/* Resource Enable TCR2 */</span>
|
||
<a name="l01290"></a>01290 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RSC2:1; <span class="comment">/* Resource Control TCR2 */</span>
|
||
<a name="l01291"></a>01291 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:2; <span class="comment">/* */</span>
|
||
<a name="l01292"></a>01292 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SERVER_ID2:4; <span class="comment">/* */</span>
|
||
<a name="l01293"></a>01293 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:4; <span class="comment">/* */</span>
|
||
<a name="l01294"></a>01294 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SRV2:4; <span class="comment">/* Resource Server Slot */</span>
|
||
<a name="l01295"></a>01295 } B;
|
||
<a name="l01296"></a>01296 } REDCR_A; <span class="comment">/*<URM>ETPU_REDCR</URM> */</span>
|
||
<a name="l01297"></a>01297
|
||
<a name="l01298"></a>01298 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ETPU_reserved_2[12];
|
||
<a name="l01299"></a>01299
|
||
<a name="l01300"></a>01300 <span class="comment">/* offset 0x0060 */</span>
|
||
<a name="l01301"></a>01301 <span class="keyword">union </span>{ <span class="comment">/* ETPU1 WDTR Register */</span>
|
||
<a name="l01302"></a>01302 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01303"></a>01303 <span class="keyword">struct </span>{
|
||
<a name="l01304"></a>01304 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WDM:2;
|
||
<a name="l01305"></a>01305 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:14;
|
||
<a name="l01306"></a>01306 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WDCNT:16;
|
||
<a name="l01307"></a>01307 } B;
|
||
<a name="l01308"></a>01308 } WDTR_A;
|
||
<a name="l01309"></a>01309
|
||
<a name="l01310"></a>01310 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ETPU1_reserved_3;
|
||
<a name="l01311"></a>01311
|
||
<a name="l01312"></a>01312 <span class="comment">/* offset 0x0068 */</span>
|
||
<a name="l01313"></a>01313 <span class="keyword">union </span>{ <span class="comment">/* ETPU1 IDLE Register */</span>
|
||
<a name="l01314"></a>01314 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01315"></a>01315 <span class="keyword">struct </span>{
|
||
<a name="l01316"></a>01316 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IDLE_CNT:31;
|
||
<a name="l01317"></a>01317 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ICLR:1;
|
||
<a name="l01318"></a>01318 } B;
|
||
<a name="l01319"></a>01319 } IDLE_A;
|
||
<a name="l01320"></a>01320
|
||
<a name="l01321"></a>01321 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ETPU_reserved_4[101];
|
||
<a name="l01322"></a>01322
|
||
<a name="l01323"></a>01323 <span class="comment">/* offset 0x0200 */</span>
|
||
<a name="l01324"></a>01324 <span class="keyword">union </span>{ <span class="comment">/* eTPU Channel Interrupt Status Register (ETPU_CISR)@baseaddress + 0x200 */</span>
|
||
<a name="l01325"></a>01325 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01326"></a>01326 <span class="keyword">struct </span>{
|
||
<a name="l01327"></a>01327 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIS31:1; <span class="comment">/* Channel 31 Interrut Status */</span>
|
||
<a name="l01328"></a>01328 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIS30:1; <span class="comment">/* Channel 30 Interrut Status */</span>
|
||
<a name="l01329"></a>01329 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIS29:1; <span class="comment">/* Channel 29 Interrut Status */</span>
|
||
<a name="l01330"></a>01330 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIS28:1; <span class="comment">/* Channel 28 Interrut Status */</span>
|
||
<a name="l01331"></a>01331 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIS27:1; <span class="comment">/* Channel 27 Interrut Status */</span>
|
||
<a name="l01332"></a>01332 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIS26:1; <span class="comment">/* Channel 26 Interrut Status */</span>
|
||
<a name="l01333"></a>01333 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIS25:1; <span class="comment">/* Channel 25 Interrut Status */</span>
|
||
<a name="l01334"></a>01334 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIS24:1; <span class="comment">/* Channel 24 Interrut Status */</span>
|
||
<a name="l01335"></a>01335 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIS23:1; <span class="comment">/* Channel 23 Interrut Status */</span>
|
||
<a name="l01336"></a>01336 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIS22:1; <span class="comment">/* Channel 22 Interrut Status */</span>
|
||
<a name="l01337"></a>01337 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIS21:1; <span class="comment">/* Channel 21 Interrut Status */</span>
|
||
<a name="l01338"></a>01338 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIS20:1; <span class="comment">/* Channel 20 Interrut Status */</span>
|
||
<a name="l01339"></a>01339 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIS19:1; <span class="comment">/* Channel 19 Interrut Status */</span>
|
||
<a name="l01340"></a>01340 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIS18:1; <span class="comment">/* Channel 18 Interrut Status */</span>
|
||
<a name="l01341"></a>01341 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIS17:1; <span class="comment">/* Channel 17 Interrut Status */</span>
|
||
<a name="l01342"></a>01342 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIS16:1; <span class="comment">/* Channel 16 Interrut Status */</span>
|
||
<a name="l01343"></a>01343 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIS15:1; <span class="comment">/* Channel 15 Interrut Status */</span>
|
||
<a name="l01344"></a>01344 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIS14:1; <span class="comment">/* Channel 14 Interrut Status */</span>
|
||
<a name="l01345"></a>01345 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIS13:1; <span class="comment">/* Channel 13 Interrut Status */</span>
|
||
<a name="l01346"></a>01346 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIS12:1; <span class="comment">/* Channel 12 Interrut Status */</span>
|
||
<a name="l01347"></a>01347 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIS11:1; <span class="comment">/* Channel 11 Interrut Status */</span>
|
||
<a name="l01348"></a>01348 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIS10:1; <span class="comment">/* Channel 10 Interrut Status */</span>
|
||
<a name="l01349"></a>01349 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIS9:1; <span class="comment">/* Channel 9 Interrut Status */</span>
|
||
<a name="l01350"></a>01350 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIS8:1; <span class="comment">/* Channel 8 Interrut Status */</span>
|
||
<a name="l01351"></a>01351 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIS7:1; <span class="comment">/* Channel 7 Interrut Status */</span>
|
||
<a name="l01352"></a>01352 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIS6:1; <span class="comment">/* Channel 6 Interrut Status */</span>
|
||
<a name="l01353"></a>01353 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIS5:1; <span class="comment">/* Channel 5 Interrut Status */</span>
|
||
<a name="l01354"></a>01354 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIS4:1; <span class="comment">/* Channel 4 Interrut Status */</span>
|
||
<a name="l01355"></a>01355 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIS3:1; <span class="comment">/* Channel 3 Interrut Status */</span>
|
||
<a name="l01356"></a>01356 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIS2:1; <span class="comment">/* Channel 2 Interrut Status */</span>
|
||
<a name="l01357"></a>01357 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIS1:1; <span class="comment">/* Channel 1 Interrut Status */</span>
|
||
<a name="l01358"></a>01358 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIS0:1; <span class="comment">/* Channel 0 Interrut Status */</span>
|
||
<a name="l01359"></a>01359 } B;
|
||
<a name="l01360"></a>01360 } CISR_A; <span class="comment">/* <URM>ETPU_CISR</URM> */</span>
|
||
<a name="l01361"></a>01361
|
||
<a name="l01362"></a>01362 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> ETPU_reserved_5[3];
|
||
<a name="l01363"></a>01363
|
||
<a name="l01364"></a>01364 <span class="comment">/* offset 0x0210 */</span>
|
||
<a name="l01365"></a>01365 <span class="keyword">union </span>{ <span class="comment">/* @baseaddress + 0x210 */</span>
|
||
<a name="l01366"></a>01366 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01367"></a>01367 <span class="keyword">struct </span>{
|
||
<a name="l01368"></a>01368 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRS31:1; <span class="comment">/* Channel 31 Data Transfer Request Status */</span>
|
||
<a name="l01369"></a>01369 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRS30:1; <span class="comment">/* Channel 30 Data Transfer Request Status */</span>
|
||
<a name="l01370"></a>01370 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRS29:1; <span class="comment">/* Channel 29 Data Transfer Request Status */</span>
|
||
<a name="l01371"></a>01371 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRS28:1; <span class="comment">/* Channel 28 Data Transfer Request Status */</span>
|
||
<a name="l01372"></a>01372 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRS27:1; <span class="comment">/* Channel 27 Data Transfer Request Status */</span>
|
||
<a name="l01373"></a>01373 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRS26:1; <span class="comment">/* Channel 26 Data Transfer Request Status */</span>
|
||
<a name="l01374"></a>01374 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRS25:1; <span class="comment">/* Channel 25 Data Transfer Request Status */</span>
|
||
<a name="l01375"></a>01375 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRS24:1; <span class="comment">/* Channel 24 Data Transfer Request Status */</span>
|
||
<a name="l01376"></a>01376 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRS23:1; <span class="comment">/* Channel 23 Data Transfer Request Status */</span>
|
||
<a name="l01377"></a>01377 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRS22:1; <span class="comment">/* Channel 22 Data Transfer Request Status */</span>
|
||
<a name="l01378"></a>01378 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRS21:1; <span class="comment">/* Channel 21 Data Transfer Request Status */</span>
|
||
<a name="l01379"></a>01379 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRS20:1; <span class="comment">/* Channel 20 Data Transfer Request Status */</span>
|
||
<a name="l01380"></a>01380 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRS19:1; <span class="comment">/* Channel 19 Data Transfer Request Status */</span>
|
||
<a name="l01381"></a>01381 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRS18:1; <span class="comment">/* Channel 18 Data Transfer Request Status */</span>
|
||
<a name="l01382"></a>01382 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRS17:1; <span class="comment">/* Channel 17 Data Transfer Request Status */</span>
|
||
<a name="l01383"></a>01383 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRS16:1; <span class="comment">/* Channel 16 Data Transfer Request Status */</span>
|
||
<a name="l01384"></a>01384 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRS15:1; <span class="comment">/* Channel 15 Data Transfer Request Status */</span>
|
||
<a name="l01385"></a>01385 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRS14:1; <span class="comment">/* Channel 14 Data Transfer Request Status */</span>
|
||
<a name="l01386"></a>01386 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRS13:1; <span class="comment">/* Channel 13 Data Transfer Request Status */</span>
|
||
<a name="l01387"></a>01387 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRS12:1; <span class="comment">/* Channel 12 Data Transfer Request Status */</span>
|
||
<a name="l01388"></a>01388 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRS11:1; <span class="comment">/* Channel 11 Data Transfer Request Status */</span>
|
||
<a name="l01389"></a>01389 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRS10:1; <span class="comment">/* Channel 10 Data Transfer Request Status */</span>
|
||
<a name="l01390"></a>01390 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRS9:1; <span class="comment">/* Channel 9 Data Transfer Request Status */</span>
|
||
<a name="l01391"></a>01391 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRS8:1; <span class="comment">/* Channel 8 Data Transfer Request Status */</span>
|
||
<a name="l01392"></a>01392 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRS7:1; <span class="comment">/* Channel 7 Data Transfer Request Status */</span>
|
||
<a name="l01393"></a>01393 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRS6:1; <span class="comment">/* Channel 6 Data Transfer Request Status */</span>
|
||
<a name="l01394"></a>01394 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRS5:1; <span class="comment">/* Channel 5 Data Transfer Request Status */</span>
|
||
<a name="l01395"></a>01395 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRS4:1; <span class="comment">/* Channel 4 Data Transfer Request Status */</span>
|
||
<a name="l01396"></a>01396 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRS3:1; <span class="comment">/* Channel 3 Data Transfer Request Status */</span>
|
||
<a name="l01397"></a>01397 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRS2:1; <span class="comment">/* Channel 2 Data Transfer Request Status */</span>
|
||
<a name="l01398"></a>01398 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRS1:1; <span class="comment">/* Channel 1 Data Transfer Request Status */</span>
|
||
<a name="l01399"></a>01399 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRS0:1; <span class="comment">/* Channel 0 Data Transfer Request Status */</span>
|
||
<a name="l01400"></a>01400 } B;
|
||
<a name="l01401"></a>01401 } CDTRSR_A; <span class="comment">/* <URM>ETPU_CDTRSR</URM> */</span>
|
||
<a name="l01402"></a>01402
|
||
<a name="l01403"></a>01403 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> ETPU_reserved_6[3];
|
||
<a name="l01404"></a>01404
|
||
<a name="l01405"></a>01405 <span class="comment">/* offset 0x0220 */</span>
|
||
<a name="l01406"></a>01406 <span class="keyword">union </span>{ <span class="comment">/* eTPU Channel Interrupt Overflow Status Register (ETPU_CIOSR)@baseaddress + 0x220 */</span>
|
||
<a name="l01407"></a>01407 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01408"></a>01408 <span class="keyword">struct </span>{
|
||
<a name="l01409"></a>01409 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIOS31:1; <span class="comment">/* Channel 31 Interruput Overflow Status */</span>
|
||
<a name="l01410"></a>01410 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIOS30:1; <span class="comment">/* Channel 30 Interruput Overflow Status */</span>
|
||
<a name="l01411"></a>01411 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIOS29:1; <span class="comment">/* Channel 29 Interruput Overflow Status */</span>
|
||
<a name="l01412"></a>01412 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIOS28:1; <span class="comment">/* Channel 28 Interruput Overflow Status */</span>
|
||
<a name="l01413"></a>01413 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIOS27:1; <span class="comment">/* Channel 27 Interruput Overflow Status */</span>
|
||
<a name="l01414"></a>01414 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIOS26:1; <span class="comment">/* Channel 26 Interruput Overflow Status */</span>
|
||
<a name="l01415"></a>01415 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIOS25:1; <span class="comment">/* Channel 25 Interruput Overflow Status */</span>
|
||
<a name="l01416"></a>01416 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIOS24:1; <span class="comment">/* Channel 24 Interruput Overflow Status */</span>
|
||
<a name="l01417"></a>01417 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIOS23:1; <span class="comment">/* Channel 23 Interruput Overflow Status */</span>
|
||
<a name="l01418"></a>01418 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIOS22:1; <span class="comment">/* Channel 22 Interruput Overflow Status */</span>
|
||
<a name="l01419"></a>01419 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIOS21:1; <span class="comment">/* Channel 21 Interruput Overflow Status */</span>
|
||
<a name="l01420"></a>01420 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIOS20:1; <span class="comment">/* Channel 20 Interruput Overflow Status */</span>
|
||
<a name="l01421"></a>01421 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIOS19:1; <span class="comment">/* Channel 19 Interruput Overflow Status */</span>
|
||
<a name="l01422"></a>01422 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIOS18:1; <span class="comment">/* Channel 18 Interruput Overflow Status */</span>
|
||
<a name="l01423"></a>01423 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIOS17:1; <span class="comment">/* Channel 17 Interruput Overflow Status */</span>
|
||
<a name="l01424"></a>01424 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIOS16:1; <span class="comment">/* Channel 16 Interruput Overflow Status */</span>
|
||
<a name="l01425"></a>01425 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIOS15:1; <span class="comment">/* Channel 15 Interruput Overflow Status */</span>
|
||
<a name="l01426"></a>01426 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIOS14:1; <span class="comment">/* Channel 14 Interruput Overflow Status */</span>
|
||
<a name="l01427"></a>01427 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIOS13:1; <span class="comment">/* Channel 13 Interruput Overflow Status */</span>
|
||
<a name="l01428"></a>01428 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIOS12:1; <span class="comment">/* Channel 12 Interruput Overflow Status */</span>
|
||
<a name="l01429"></a>01429 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIOS11:1; <span class="comment">/* Channel 11 Interruput Overflow Status */</span>
|
||
<a name="l01430"></a>01430 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIOS10:1; <span class="comment">/* Channel 10 Interruput Overflow Status */</span>
|
||
<a name="l01431"></a>01431 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIOS9:1; <span class="comment">/* Channel 9 Interruput Overflow Status */</span>
|
||
<a name="l01432"></a>01432 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIOS8:1; <span class="comment">/* Channel 8 Interruput Overflow Status */</span>
|
||
<a name="l01433"></a>01433 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIOS7:1; <span class="comment">/* Channel 7 Interruput Overflow Status */</span>
|
||
<a name="l01434"></a>01434 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIOS6:1; <span class="comment">/* Channel 6 Interruput Overflow Status */</span>
|
||
<a name="l01435"></a>01435 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIOS5:1; <span class="comment">/* Channel 5 Interruput Overflow Status */</span>
|
||
<a name="l01436"></a>01436 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIOS4:1; <span class="comment">/* Channel 4 Interruput Overflow Status */</span>
|
||
<a name="l01437"></a>01437 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIOS3:1; <span class="comment">/* Channel 3 Interruput Overflow Status */</span>
|
||
<a name="l01438"></a>01438 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIOS2:1; <span class="comment">/* Channel 2 Interruput Overflow Status */</span>
|
||
<a name="l01439"></a>01439 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIOS1:1; <span class="comment">/* Channel 1 Interruput Overflow Status */</span>
|
||
<a name="l01440"></a>01440 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIOS0:1; <span class="comment">/* Channel 0 Interruput Overflow Status */</span>
|
||
<a name="l01441"></a>01441 } B;
|
||
<a name="l01442"></a>01442 } CIOSR_A; <span class="comment">/* <URM>ETPU_CIOSR</URM> */</span>
|
||
<a name="l01443"></a>01443
|
||
<a name="l01444"></a>01444 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> ETPU_reserved_7[3];
|
||
<a name="l01445"></a>01445
|
||
<a name="l01446"></a>01446 <span class="comment">/* offset 0x0230 */</span>
|
||
<a name="l01447"></a>01447 <span class="keyword">union </span>{ <span class="comment">/* eTPU Channel Data Transfer Request Overflow Status Register@baseaddress + 0x230 */</span>
|
||
<a name="l01448"></a>01448 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01449"></a>01449 <span class="keyword">struct </span>{
|
||
<a name="l01450"></a>01450 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTROS31:1; <span class="comment">/* Channel 31 Data Transfer Overflow Status */</span>
|
||
<a name="l01451"></a>01451 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTROS30:1; <span class="comment">/* Channel 30 Data Transfer Overflow Status */</span>
|
||
<a name="l01452"></a>01452 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTROS29:1; <span class="comment">/* Channel 29 Data Transfer Overflow Status */</span>
|
||
<a name="l01453"></a>01453 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTROS28:1; <span class="comment">/* Channel 28 Data Transfer Overflow Status */</span>
|
||
<a name="l01454"></a>01454 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTROS27:1; <span class="comment">/* Channel 27 Data Transfer Overflow Status */</span>
|
||
<a name="l01455"></a>01455 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTROS26:1; <span class="comment">/* Channel 26 Data Transfer Overflow Status */</span>
|
||
<a name="l01456"></a>01456 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTROS25:1; <span class="comment">/* Channel 25 Data Transfer Overflow Status */</span>
|
||
<a name="l01457"></a>01457 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTROS24:1; <span class="comment">/* Channel 24 Data Transfer Overflow Status */</span>
|
||
<a name="l01458"></a>01458 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTROS23:1; <span class="comment">/* Channel 23 Data Transfer Overflow Status */</span>
|
||
<a name="l01459"></a>01459 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTROS22:1; <span class="comment">/* Channel 22 Data Transfer Overflow Status */</span>
|
||
<a name="l01460"></a>01460 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTROS21:1; <span class="comment">/* Channel 21 Data Transfer Overflow Status */</span>
|
||
<a name="l01461"></a>01461 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTROS20:1; <span class="comment">/* Channel 20 Data Transfer Overflow Status */</span>
|
||
<a name="l01462"></a>01462 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTROS19:1; <span class="comment">/* Channel 19 Data Transfer Overflow Status */</span>
|
||
<a name="l01463"></a>01463 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTROS18:1; <span class="comment">/* Channel 18 Data Transfer Overflow Status */</span>
|
||
<a name="l01464"></a>01464 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTROS17:1; <span class="comment">/* Channel 17 Data Transfer Overflow Status */</span>
|
||
<a name="l01465"></a>01465 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTROS16:1; <span class="comment">/* Channel 16 Data Transfer Overflow Status */</span>
|
||
<a name="l01466"></a>01466 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTROS15:1; <span class="comment">/* Channel 15 Data Transfer Overflow Status */</span>
|
||
<a name="l01467"></a>01467 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTROS14:1; <span class="comment">/* Channel 14 Data Transfer Overflow Status */</span>
|
||
<a name="l01468"></a>01468 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTROS13:1; <span class="comment">/* Channel 13 Data Transfer Overflow Status */</span>
|
||
<a name="l01469"></a>01469 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTROS12:1; <span class="comment">/* Channel 12 Data Transfer Overflow Status */</span>
|
||
<a name="l01470"></a>01470 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTROS11:1; <span class="comment">/* Channel 11 Data Transfer Overflow Status */</span>
|
||
<a name="l01471"></a>01471 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTROS10:1; <span class="comment">/* Channel 10 Data Transfer Overflow Status */</span>
|
||
<a name="l01472"></a>01472 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTROS9:1; <span class="comment">/* Channel 9 Data Transfer Overflow Status */</span>
|
||
<a name="l01473"></a>01473 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTROS8:1; <span class="comment">/* Channel 8 Data Transfer Overflow Status */</span>
|
||
<a name="l01474"></a>01474 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTROS7:1; <span class="comment">/* Channel 7 Data Transfer Overflow Status */</span>
|
||
<a name="l01475"></a>01475 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTROS6:1; <span class="comment">/* Channel 6 Data Transfer Overflow Status */</span>
|
||
<a name="l01476"></a>01476 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTROS5:1; <span class="comment">/* Channel 5 Data Transfer Overflow Status */</span>
|
||
<a name="l01477"></a>01477 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTROS4:1; <span class="comment">/* Channel 4 Data Transfer Overflow Status */</span>
|
||
<a name="l01478"></a>01478 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTROS3:1; <span class="comment">/* Channel 3 Data Transfer Overflow Status */</span>
|
||
<a name="l01479"></a>01479 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTROS2:1; <span class="comment">/* Channel 2 Data Transfer Overflow Status */</span>
|
||
<a name="l01480"></a>01480 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTROS1:1; <span class="comment">/* Channel 1 Data Transfer Overflow Status */</span>
|
||
<a name="l01481"></a>01481 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTROS0:1; <span class="comment">/* Channel 0 Data Transfer Overflow Status */</span>
|
||
<a name="l01482"></a>01482 } B;
|
||
<a name="l01483"></a>01483 } CDTROSR_A; <span class="comment">/* <URM>ETPU_CDTROSR</URM> */</span>
|
||
<a name="l01484"></a>01484
|
||
<a name="l01485"></a>01485 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> ETPU_reserved_8[3];
|
||
<a name="l01486"></a>01486
|
||
<a name="l01487"></a>01487 <span class="comment">/* offset 0x0240 */</span>
|
||
<a name="l01488"></a>01488 <span class="keyword">union </span>{ <span class="comment">/* eTPU Channel Interrupt Enable Register (ETPU_CIER)@baseaddress + 0x240 */</span>
|
||
<a name="l01489"></a>01489 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01490"></a>01490 <span class="keyword">struct </span>{
|
||
<a name="l01491"></a>01491 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIE31:1; <span class="comment">/* Channel 31 Interruput Enable */</span>
|
||
<a name="l01492"></a>01492 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIE30:1; <span class="comment">/* Channel 30 Interruput Enable */</span>
|
||
<a name="l01493"></a>01493 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIE29:1; <span class="comment">/* Channel 29 Interruput Enable */</span>
|
||
<a name="l01494"></a>01494 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIE28:1; <span class="comment">/* Channel 28 Interruput Enable */</span>
|
||
<a name="l01495"></a>01495 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIE27:1; <span class="comment">/* Channel 27 Interruput Enable */</span>
|
||
<a name="l01496"></a>01496 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIE26:1; <span class="comment">/* Channel 26 Interruput Enable */</span>
|
||
<a name="l01497"></a>01497 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIE25:1; <span class="comment">/* Channel 25 Interruput Enable */</span>
|
||
<a name="l01498"></a>01498 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIE24:1; <span class="comment">/* Channel 24 Interruput Enable */</span>
|
||
<a name="l01499"></a>01499 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIE23:1; <span class="comment">/* Channel 23 Interruput Enable */</span>
|
||
<a name="l01500"></a>01500 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIE22:1; <span class="comment">/* Channel 22 Interruput Enable */</span>
|
||
<a name="l01501"></a>01501 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIE21:1; <span class="comment">/* Channel 21 Interruput Enable */</span>
|
||
<a name="l01502"></a>01502 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIE20:1; <span class="comment">/* Channel 20 Interruput Enable */</span>
|
||
<a name="l01503"></a>01503 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIE19:1; <span class="comment">/* Channel 19 Interruput Enable */</span>
|
||
<a name="l01504"></a>01504 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIE18:1; <span class="comment">/* Channel 18 Interruput Enable */</span>
|
||
<a name="l01505"></a>01505 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIE17:1; <span class="comment">/* Channel 17 Interruput Enable */</span>
|
||
<a name="l01506"></a>01506 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIE16:1; <span class="comment">/* Channel 16 Interruput Enable */</span>
|
||
<a name="l01507"></a>01507 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIE15:1; <span class="comment">/* Channel 15 Interruput Enable */</span>
|
||
<a name="l01508"></a>01508 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIE14:1; <span class="comment">/* Channel 14 Interruput Enable */</span>
|
||
<a name="l01509"></a>01509 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIE13:1; <span class="comment">/* Channel 13 Interruput Enable */</span>
|
||
<a name="l01510"></a>01510 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIE12:1; <span class="comment">/* Channel 12 Interruput Enable */</span>
|
||
<a name="l01511"></a>01511 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIE11:1; <span class="comment">/* Channel 11 Interruput Enable */</span>
|
||
<a name="l01512"></a>01512 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIE10:1; <span class="comment">/* Channel 10 Interruput Enable */</span>
|
||
<a name="l01513"></a>01513 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIE9:1; <span class="comment">/* Channel 9 Interruput Enable */</span>
|
||
<a name="l01514"></a>01514 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIE8:1; <span class="comment">/* Channel 8 Interruput Enable */</span>
|
||
<a name="l01515"></a>01515 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIE7:1; <span class="comment">/* Channel 7 Interruput Enable */</span>
|
||
<a name="l01516"></a>01516 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIE6:1; <span class="comment">/* Channel 6 Interruput Enable */</span>
|
||
<a name="l01517"></a>01517 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIE5:1; <span class="comment">/* Channel 5 Interruput Enable */</span>
|
||
<a name="l01518"></a>01518 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIE4:1; <span class="comment">/* Channel 4 Interruput Enable */</span>
|
||
<a name="l01519"></a>01519 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIE3:1; <span class="comment">/* Channel 3 Interruput Enable */</span>
|
||
<a name="l01520"></a>01520 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIE2:1; <span class="comment">/* Channel 2 Interruput Enable */</span>
|
||
<a name="l01521"></a>01521 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIE1:1; <span class="comment">/* Channel 1 Interruput Enable */</span>
|
||
<a name="l01522"></a>01522 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIE0:1; <span class="comment">/* Channel 0 Interruput Enable */</span>
|
||
<a name="l01523"></a>01523 } B;
|
||
<a name="l01524"></a>01524 } CIER_A; <span class="comment">/* <URM>ETPU_CIER</URM> */</span>
|
||
<a name="l01525"></a>01525
|
||
<a name="l01526"></a>01526 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> ETPU_reserved_9[3];
|
||
<a name="l01527"></a>01527
|
||
<a name="l01528"></a>01528 <span class="comment">/* offset 0x0250 */</span>
|
||
<a name="l01529"></a>01529 <span class="keyword">union </span>{ <span class="comment">/* eTPU Channel Data Transfer Request Enable Register (ETPU_CDTRER)@baseaddress + 0x250 */</span>
|
||
<a name="l01530"></a>01530 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01531"></a>01531 <span class="keyword">struct </span>{
|
||
<a name="l01532"></a>01532 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRE31:1; <span class="comment">/* Channel 31 Data Transfer Request Enable */</span>
|
||
<a name="l01533"></a>01533 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRE30:1; <span class="comment">/* Channel 30 Data Transfer Request Enable */</span>
|
||
<a name="l01534"></a>01534 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRE29:1; <span class="comment">/* Channel 29 Data Transfer Request Enable */</span>
|
||
<a name="l01535"></a>01535 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRE28:1; <span class="comment">/* Channel 28 Data Transfer Request Enable */</span>
|
||
<a name="l01536"></a>01536 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRE27:1; <span class="comment">/* Channel 27 Data Transfer Request Enable */</span>
|
||
<a name="l01537"></a>01537 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRE26:1; <span class="comment">/* Channel 26 Data Transfer Request Enable */</span>
|
||
<a name="l01538"></a>01538 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRE25:1; <span class="comment">/* Channel 25 Data Transfer Request Enable */</span>
|
||
<a name="l01539"></a>01539 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRE24:1; <span class="comment">/* Channel 24 Data Transfer Request Enable */</span>
|
||
<a name="l01540"></a>01540 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRE23:1; <span class="comment">/* Channel 23 Data Transfer Request Enable */</span>
|
||
<a name="l01541"></a>01541 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRE22:1; <span class="comment">/* Channel 22 Data Transfer Request Enable */</span>
|
||
<a name="l01542"></a>01542 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRE21:1; <span class="comment">/* Channel 21 Data Transfer Request Enable */</span>
|
||
<a name="l01543"></a>01543 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRE20:1; <span class="comment">/* Channel 20 Data Transfer Request Enable */</span>
|
||
<a name="l01544"></a>01544 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRE19:1; <span class="comment">/* Channel 19 Data Transfer Request Enable */</span>
|
||
<a name="l01545"></a>01545 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRE18:1; <span class="comment">/* Channel 18 Data Transfer Request Enable */</span>
|
||
<a name="l01546"></a>01546 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRE17:1; <span class="comment">/* Channel 17 Data Transfer Request Enable */</span>
|
||
<a name="l01547"></a>01547 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRE16:1; <span class="comment">/* Channel 16 Data Transfer Request Enable */</span>
|
||
<a name="l01548"></a>01548 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRE15:1; <span class="comment">/* Channel 15 Data Transfer Request Enable */</span>
|
||
<a name="l01549"></a>01549 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRE14:1; <span class="comment">/* Channel 14 Data Transfer Request Enable */</span>
|
||
<a name="l01550"></a>01550 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRE13:1; <span class="comment">/* Channel 13 Data Transfer Request Enable */</span>
|
||
<a name="l01551"></a>01551 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRE12:1; <span class="comment">/* Channel 12 Data Transfer Request Enable */</span>
|
||
<a name="l01552"></a>01552 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRE11:1; <span class="comment">/* Channel 11 Data Transfer Request Enable */</span>
|
||
<a name="l01553"></a>01553 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRE10:1; <span class="comment">/* Channel 10 Data Transfer Request Enable */</span>
|
||
<a name="l01554"></a>01554 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRE9:1; <span class="comment">/* Channel 9 Data Transfer Request Enable */</span>
|
||
<a name="l01555"></a>01555 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRE8:1; <span class="comment">/* Channel 8 Data Transfer Request Enable */</span>
|
||
<a name="l01556"></a>01556 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRE7:1; <span class="comment">/* Channel 7 Data Transfer Request Enable */</span>
|
||
<a name="l01557"></a>01557 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRE6:1; <span class="comment">/* Channel 6 Data Transfer Request Enable */</span>
|
||
<a name="l01558"></a>01558 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRE5:1; <span class="comment">/* Channel 5 Data Transfer Request Enable */</span>
|
||
<a name="l01559"></a>01559 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRE4:1; <span class="comment">/* Channel 4 Data Transfer Request Enable */</span>
|
||
<a name="l01560"></a>01560 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRE3:1; <span class="comment">/* Channel 3 Data Transfer Request Enable */</span>
|
||
<a name="l01561"></a>01561 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRE2:1; <span class="comment">/* Channel 2 Data Transfer Request Enable */</span>
|
||
<a name="l01562"></a>01562 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRE1:1; <span class="comment">/* Channel 1 Data Transfer Request Enable */</span>
|
||
<a name="l01563"></a>01563 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRE0:1; <span class="comment">/* Channel 0 Data Transfer Request Enable */</span>
|
||
<a name="l01564"></a>01564 } B;
|
||
<a name="l01565"></a>01565 } CDTRER_A; <span class="comment">/* <URM>ETPU_CDTRER</URM> */</span>
|
||
<a name="l01566"></a>01566
|
||
<a name="l01567"></a>01567 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> ETPU_reserved_10[3];
|
||
<a name="l01568"></a>01568
|
||
<a name="l01569"></a>01569 <span class="comment">/* offset 0x0260 */</span>
|
||
<a name="l01570"></a>01570 <span class="keyword">union </span>{ <span class="comment">/* ETPUWDSR - eTPU Watchdog Status Register */</span>
|
||
<a name="l01571"></a>01571 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01572"></a>01572 <span class="keyword">struct </span>{
|
||
<a name="l01573"></a>01573 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WDS31:1; <span class="comment">/* Channel 31 Data Transfer Request Enable */</span>
|
||
<a name="l01574"></a>01574 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WDS30:1; <span class="comment">/* Channel 30 Data Transfer Request Enable */</span>
|
||
<a name="l01575"></a>01575 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WDS29:1; <span class="comment">/* Channel 29 Data Transfer Request Enable */</span>
|
||
<a name="l01576"></a>01576 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WDS28:1; <span class="comment">/* Channel 28 Data Transfer Request Enable */</span>
|
||
<a name="l01577"></a>01577 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WDS27:1; <span class="comment">/* Channel 27 Data Transfer Request Enable */</span>
|
||
<a name="l01578"></a>01578 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WDS26:1; <span class="comment">/* Channel 26 Data Transfer Request Enable */</span>
|
||
<a name="l01579"></a>01579 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WDS25:1; <span class="comment">/* Channel 25 Data Transfer Request Enable */</span>
|
||
<a name="l01580"></a>01580 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WDS24:1; <span class="comment">/* Channel 24 Data Transfer Request Enable */</span>
|
||
<a name="l01581"></a>01581 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WDS23:1; <span class="comment">/* Channel 23 Data Transfer Request Enable */</span>
|
||
<a name="l01582"></a>01582 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WDS22:1; <span class="comment">/* Channel 22 Data Transfer Request Enable */</span>
|
||
<a name="l01583"></a>01583 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WDS21:1; <span class="comment">/* Channel 21 Data Transfer Request Enable */</span>
|
||
<a name="l01584"></a>01584 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WDS20:1; <span class="comment">/* Channel 20 Data Transfer Request Enable */</span>
|
||
<a name="l01585"></a>01585 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WDS19:1; <span class="comment">/* Channel 19 Data Transfer Request Enable */</span>
|
||
<a name="l01586"></a>01586 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WDS18:1; <span class="comment">/* Channel 18 Data Transfer Request Enable */</span>
|
||
<a name="l01587"></a>01587 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WDS17:1; <span class="comment">/* Channel 17 Data Transfer Request Enable */</span>
|
||
<a name="l01588"></a>01588 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WDS16:1; <span class="comment">/* Channel 16 Data Transfer Request Enable */</span>
|
||
<a name="l01589"></a>01589 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WDS15:1; <span class="comment">/* Channel 15 Data Transfer Request Enable */</span>
|
||
<a name="l01590"></a>01590 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WDS14:1; <span class="comment">/* Channel 14 Data Transfer Request Enable */</span>
|
||
<a name="l01591"></a>01591 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WDS13:1; <span class="comment">/* Channel 13 Data Transfer Request Enable */</span>
|
||
<a name="l01592"></a>01592 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WDS12:1; <span class="comment">/* Channel 12 Data Transfer Request Enable */</span>
|
||
<a name="l01593"></a>01593 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WDS11:1; <span class="comment">/* Channel 11 Data Transfer Request Enable */</span>
|
||
<a name="l01594"></a>01594 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WDS10:1; <span class="comment">/* Channel 10 Data Transfer Request Enable */</span>
|
||
<a name="l01595"></a>01595 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WDS9:1; <span class="comment">/* Channel 9 Data Transfer Request Enable */</span>
|
||
<a name="l01596"></a>01596 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WDS8:1; <span class="comment">/* Channel 8 Data Transfer Request Enable */</span>
|
||
<a name="l01597"></a>01597 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WDS7:1; <span class="comment">/* Channel 7 Data Transfer Request Enable */</span>
|
||
<a name="l01598"></a>01598 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WDS6:1; <span class="comment">/* Channel 6 Data Transfer Request Enable */</span>
|
||
<a name="l01599"></a>01599 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WDS5:1; <span class="comment">/* Channel 5 Data Transfer Request Enable */</span>
|
||
<a name="l01600"></a>01600 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WDS4:1; <span class="comment">/* Channel 4 Data Transfer Request Enable */</span>
|
||
<a name="l01601"></a>01601 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WDS3:1; <span class="comment">/* Channel 3 Data Transfer Request Enable */</span>
|
||
<a name="l01602"></a>01602 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WDS2:1; <span class="comment">/* Channel 2 Data Transfer Request Enable */</span>
|
||
<a name="l01603"></a>01603 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WDS1:1; <span class="comment">/* Channel 1 Data Transfer Request Enable */</span>
|
||
<a name="l01604"></a>01604 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WDS0:1; <span class="comment">/* Channel 0 Data Transfer Request Enable */</span>
|
||
<a name="l01605"></a>01605 } B;
|
||
<a name="l01606"></a>01606 } WDSR_A;
|
||
<a name="l01607"></a>01607
|
||
<a name="l01608"></a>01608 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> ETPU_reserved_11[7];
|
||
<a name="l01609"></a>01609
|
||
<a name="l01610"></a>01610 <span class="comment">/* offset 0x0280 */</span>
|
||
<a name="l01611"></a>01611 <span class="keyword">union </span>{ <span class="comment">/* ETPUCPSSR - eTPU Channel Pending Service Status Register */</span>
|
||
<a name="l01612"></a>01612 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01613"></a>01613 <span class="keyword">struct </span>{
|
||
<a name="l01614"></a>01614 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SR31:1; <span class="comment">/* Channel 31 Data Transfer Request Enable */</span>
|
||
<a name="l01615"></a>01615 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SR30:1; <span class="comment">/* Channel 30 Data Transfer Request Enable */</span>
|
||
<a name="l01616"></a>01616 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SR29:1; <span class="comment">/* Channel 29 Data Transfer Request Enable */</span>
|
||
<a name="l01617"></a>01617 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SR28:1; <span class="comment">/* Channel 28 Data Transfer Request Enable */</span>
|
||
<a name="l01618"></a>01618 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SR27:1; <span class="comment">/* Channel 27 Data Transfer Request Enable */</span>
|
||
<a name="l01619"></a>01619 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SR26:1; <span class="comment">/* Channel 26 Data Transfer Request Enable */</span>
|
||
<a name="l01620"></a>01620 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SR25:1; <span class="comment">/* Channel 25 Data Transfer Request Enable */</span>
|
||
<a name="l01621"></a>01621 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SR24:1; <span class="comment">/* Channel 24 Data Transfer Request Enable */</span>
|
||
<a name="l01622"></a>01622 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SR23:1; <span class="comment">/* Channel 23 Data Transfer Request Enable */</span>
|
||
<a name="l01623"></a>01623 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SR22:1; <span class="comment">/* Channel 22 Data Transfer Request Enable */</span>
|
||
<a name="l01624"></a>01624 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SR21:1; <span class="comment">/* Channel 21 Data Transfer Request Enable */</span>
|
||
<a name="l01625"></a>01625 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SR20:1; <span class="comment">/* Channel 20 Data Transfer Request Enable */</span>
|
||
<a name="l01626"></a>01626 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SR19:1; <span class="comment">/* Channel 19 Data Transfer Request Enable */</span>
|
||
<a name="l01627"></a>01627 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SR18:1; <span class="comment">/* Channel 18 Data Transfer Request Enable */</span>
|
||
<a name="l01628"></a>01628 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SR17:1; <span class="comment">/* Channel 17 Data Transfer Request Enable */</span>
|
||
<a name="l01629"></a>01629 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SR16:1; <span class="comment">/* Channel 16 Data Transfer Request Enable */</span>
|
||
<a name="l01630"></a>01630 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SR15:1; <span class="comment">/* Channel 15 Data Transfer Request Enable */</span>
|
||
<a name="l01631"></a>01631 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SR14:1; <span class="comment">/* Channel 14 Data Transfer Request Enable */</span>
|
||
<a name="l01632"></a>01632 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SR13:1; <span class="comment">/* Channel 13 Data Transfer Request Enable */</span>
|
||
<a name="l01633"></a>01633 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SR12:1; <span class="comment">/* Channel 12 Data Transfer Request Enable */</span>
|
||
<a name="l01634"></a>01634 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SR11:1; <span class="comment">/* Channel 11 Data Transfer Request Enable */</span>
|
||
<a name="l01635"></a>01635 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SR10:1; <span class="comment">/* Channel 10 Data Transfer Request Enable */</span>
|
||
<a name="l01636"></a>01636 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SR9:1; <span class="comment">/* Channel 9 Data Transfer Request Enable */</span>
|
||
<a name="l01637"></a>01637 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SR8:1; <span class="comment">/* Channel 8 Data Transfer Request Enable */</span>
|
||
<a name="l01638"></a>01638 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SR7:1; <span class="comment">/* Channel 7 Data Transfer Request Enable */</span>
|
||
<a name="l01639"></a>01639 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SR6:1; <span class="comment">/* Channel 6 Data Transfer Request Enable */</span>
|
||
<a name="l01640"></a>01640 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SR5:1; <span class="comment">/* Channel 5 Data Transfer Request Enable */</span>
|
||
<a name="l01641"></a>01641 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SR4:1; <span class="comment">/* Channel 4 Data Transfer Request Enable */</span>
|
||
<a name="l01642"></a>01642 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SR3:1; <span class="comment">/* Channel 3 Data Transfer Request Enable */</span>
|
||
<a name="l01643"></a>01643 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SR2:1; <span class="comment">/* Channel 2 Data Transfer Request Enable */</span>
|
||
<a name="l01644"></a>01644 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SR1:1; <span class="comment">/* Channel 1 Data Transfer Request Enable */</span>
|
||
<a name="l01645"></a>01645 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SR0:1; <span class="comment">/* Channel 0 Data Transfer Request Enable */</span>
|
||
<a name="l01646"></a>01646 } B;
|
||
<a name="l01647"></a>01647 } CPSSR_A; <span class="comment">/* <URM>ETPU_CPSSR</URM> */</span>
|
||
<a name="l01648"></a>01648
|
||
<a name="l01649"></a>01649 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> ETPU_reserved_12[3];
|
||
<a name="l01650"></a>01650
|
||
<a name="l01651"></a>01651 <span class="comment">/* offset 0x0290 */</span>
|
||
<a name="l01652"></a>01652 <span class="keyword">union </span>{ <span class="comment">/* ETPUCSSR - eTPU Channel Service Status Register */</span>
|
||
<a name="l01653"></a>01653 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01654"></a>01654 <span class="keyword">struct </span>{
|
||
<a name="l01655"></a>01655 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SS31:1; <span class="comment">/* Channel 31 Data Transfer Request Enable */</span>
|
||
<a name="l01656"></a>01656 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SS30:1; <span class="comment">/* Channel 30 Data Transfer Request Enable */</span>
|
||
<a name="l01657"></a>01657 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SS29:1; <span class="comment">/* Channel 29 Data Transfer Request Enable */</span>
|
||
<a name="l01658"></a>01658 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SS28:1; <span class="comment">/* Channel 28 Data Transfer Request Enable */</span>
|
||
<a name="l01659"></a>01659 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SS27:1; <span class="comment">/* Channel 27 Data Transfer Request Enable */</span>
|
||
<a name="l01660"></a>01660 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SS26:1; <span class="comment">/* Channel 26 Data Transfer Request Enable */</span>
|
||
<a name="l01661"></a>01661 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SS25:1; <span class="comment">/* Channel 25 Data Transfer Request Enable */</span>
|
||
<a name="l01662"></a>01662 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SS24:1; <span class="comment">/* Channel 24 Data Transfer Request Enable */</span>
|
||
<a name="l01663"></a>01663 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SS23:1; <span class="comment">/* Channel 23 Data Transfer Request Enable */</span>
|
||
<a name="l01664"></a>01664 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SS22:1; <span class="comment">/* Channel 22 Data Transfer Request Enable */</span>
|
||
<a name="l01665"></a>01665 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SS21:1; <span class="comment">/* Channel 21 Data Transfer Request Enable */</span>
|
||
<a name="l01666"></a>01666 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SS20:1; <span class="comment">/* Channel 20 Data Transfer Request Enable */</span>
|
||
<a name="l01667"></a>01667 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SS19:1; <span class="comment">/* Channel 19 Data Transfer Request Enable */</span>
|
||
<a name="l01668"></a>01668 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SS18:1; <span class="comment">/* Channel 18 Data Transfer Request Enable */</span>
|
||
<a name="l01669"></a>01669 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SS17:1; <span class="comment">/* Channel 17 Data Transfer Request Enable */</span>
|
||
<a name="l01670"></a>01670 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SS16:1; <span class="comment">/* Channel 16 Data Transfer Request Enable */</span>
|
||
<a name="l01671"></a>01671 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SS15:1; <span class="comment">/* Channel 15 Data Transfer Request Enable */</span>
|
||
<a name="l01672"></a>01672 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SS14:1; <span class="comment">/* Channel 14 Data Transfer Request Enable */</span>
|
||
<a name="l01673"></a>01673 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SS13:1; <span class="comment">/* Channel 13 Data Transfer Request Enable */</span>
|
||
<a name="l01674"></a>01674 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SS12:1; <span class="comment">/* Channel 12 Data Transfer Request Enable */</span>
|
||
<a name="l01675"></a>01675 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SS11:1; <span class="comment">/* Channel 11 Data Transfer Request Enable */</span>
|
||
<a name="l01676"></a>01676 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SS10:1; <span class="comment">/* Channel 10 Data Transfer Request Enable */</span>
|
||
<a name="l01677"></a>01677 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SS9:1; <span class="comment">/* Channel 9 Data Transfer Request Enable */</span>
|
||
<a name="l01678"></a>01678 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SS8:1; <span class="comment">/* Channel 8 Data Transfer Request Enable */</span>
|
||
<a name="l01679"></a>01679 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SS7:1; <span class="comment">/* Channel 7 Data Transfer Request Enable */</span>
|
||
<a name="l01680"></a>01680 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SS6:1; <span class="comment">/* Channel 6 Data Transfer Request Enable */</span>
|
||
<a name="l01681"></a>01681 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SS5:1; <span class="comment">/* Channel 5 Data Transfer Request Enable */</span>
|
||
<a name="l01682"></a>01682 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SS4:1; <span class="comment">/* Channel 4 Data Transfer Request Enable */</span>
|
||
<a name="l01683"></a>01683 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SS3:1; <span class="comment">/* Channel 3 Data Transfer Request Enable */</span>
|
||
<a name="l01684"></a>01684 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SS2:1; <span class="comment">/* Channel 2 Data Transfer Request Enable */</span>
|
||
<a name="l01685"></a>01685 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SS1:1; <span class="comment">/* Channel 1 Data Transfer Request Enable */</span>
|
||
<a name="l01686"></a>01686 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SS0:1; <span class="comment">/* Channel 0 Data Transfer Request Enable */</span>
|
||
<a name="l01687"></a>01687 } B;
|
||
<a name="l01688"></a>01688 } CSSR_A; <span class="comment">/* <URM>ETPU_CSSR</URM> */</span>
|
||
<a name="l01689"></a>01689
|
||
<a name="l01690"></a>01690 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> ETPU_reserved_13[3];
|
||
<a name="l01691"></a>01691 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> ETPU_reserved_14[88];
|
||
<a name="l01692"></a>01692
|
||
<a name="l01693"></a>01693 <span class="comment">/***************************** Channels ********************************/</span>
|
||
<a name="l01694"></a>01694 <span class="comment">/* Note not all devices implement all channels or even 2 engines */</span>
|
||
<a name="l01695"></a>01695 <span class="comment">/* Each eTPU engine can implement 64 channels, however most devcies */</span>
|
||
<a name="l01696"></a>01696 <span class="comment">/* only implemnet 32 channels. The eTPU block can implement 1 or 2 */</span>
|
||
<a name="l01697"></a>01697 <span class="comment">/* engines per instantiation */</span>
|
||
<a name="l01698"></a>01698 <span class="comment">/***********************************************************************/</span>
|
||
<a name="l01699"></a>01699
|
||
<a name="l01700"></a>01700 <span class="keyword">struct </span>{
|
||
<a name="l01701"></a>01701 <span class="keyword">union </span>{ <span class="comment">/* eTPU Channel n Configuration Register (ETPU_CnCR)@baseaddress + 0x400 */</span>
|
||
<a name="l01702"></a>01702 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01703"></a>01703 <span class="keyword">struct </span>{
|
||
<a name="l01704"></a>01704 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIE:1; <span class="comment">/* Channel Interruput Enable */</span>
|
||
<a name="l01705"></a>01705 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRE:1; <span class="comment">/* Data Transfer Request Enable */</span>
|
||
<a name="l01706"></a>01706 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CPR:2; <span class="comment">/* Channel Priority */</span>
|
||
<a name="l01707"></a>01707 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:2; <span class="comment">/* */</span>
|
||
<a name="l01708"></a>01708 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ETPD:1; <span class="comment">/* This bit selects which channel signal, input or output, is used in the entry point selection */</span>
|
||
<a name="l01709"></a>01709 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ETCS:1; <span class="comment">/* Entry Table Condition Select */</span>
|
||
<a name="l01710"></a>01710 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:3; <span class="comment">/* */</span>
|
||
<a name="l01711"></a>01711 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CFS:5; <span class="comment">/* Channel Function Select */</span>
|
||
<a name="l01712"></a>01712 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ODIS:1; <span class="comment">/* Output disable */</span>
|
||
<a name="l01713"></a>01713 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OPOL:1; <span class="comment">/* output polarity */</span>
|
||
<a name="l01714"></a>01714 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:3; <span class="comment">/* */</span>
|
||
<a name="l01715"></a>01715 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CPBA:11; <span class="comment">/* Channel Parameter Base Address */</span>
|
||
<a name="l01716"></a>01716 } B;
|
||
<a name="l01717"></a>01717 } CR; <span class="comment">/* <URM>ETPU_CnCR</URM> */</span>
|
||
<a name="l01718"></a>01718
|
||
<a name="l01719"></a>01719 <span class="keyword">union </span>{ <span class="comment">/* eTPU Channel n Status Control Register (ETPU_CnSCR)@baseaddress + 0x404 */</span>
|
||
<a name="l01720"></a>01720 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01721"></a>01721 <span class="keyword">struct </span>{
|
||
<a name="l01722"></a>01722 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIS:1; <span class="comment">/* Channel Interruput Status */</span>
|
||
<a name="l01723"></a>01723 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIOS:1; <span class="comment">/* Channel Interruput Overflow Status */</span>
|
||
<a name="l01724"></a>01724 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:6; <span class="comment">/* */</span>
|
||
<a name="l01725"></a>01725 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTRS:1; <span class="comment">/* Data Transfer Status */</span>
|
||
<a name="l01726"></a>01726 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DTROS:1; <span class="comment">/* Data Transfer Overflow Status */</span>
|
||
<a name="l01727"></a>01727 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:6; <span class="comment">/* */</span>
|
||
<a name="l01728"></a>01728 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IPS:1; <span class="comment">/* Input Pin State */</span>
|
||
<a name="l01729"></a>01729 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OPS:1; <span class="comment">/* Output Pin State */</span>
|
||
<a name="l01730"></a>01730 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OBE:1; <span class="comment">/* Output Pin State */</span>
|
||
<a name="l01731"></a>01731 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:11; <span class="comment">/* */</span>
|
||
<a name="l01732"></a>01732 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> FM1:1; <span class="comment">/* Function mode */</span>
|
||
<a name="l01733"></a>01733 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> FM0:1; <span class="comment">/* Function mode */</span>
|
||
<a name="l01734"></a>01734 } B;
|
||
<a name="l01735"></a>01735 } SCR; <span class="comment">/* <URM>ETPU_CnSCR</URM> */</span>
|
||
<a name="l01736"></a>01736
|
||
<a name="l01737"></a>01737 <span class="keyword">union </span>{ <span class="comment">/* eTPU channel host service request register (ETPU_CnHSRR)@baseaddress + 0x408 */</span>
|
||
<a name="l01738"></a>01738 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01739"></a>01739 <span class="keyword">struct </span>{
|
||
<a name="l01740"></a>01740 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:29; <span class="comment">/* Host Service Request */</span>
|
||
<a name="l01741"></a>01741 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> HSR:3; <span class="comment">/* */</span>
|
||
<a name="l01742"></a>01742 } B;
|
||
<a name="l01743"></a>01743 } HSRR; <span class="comment">/* <URM>ETPU_CnHSRR</URM> */</span>
|
||
<a name="l01744"></a>01744 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> ETPU_reserved_18;
|
||
<a name="l01745"></a>01745
|
||
<a name="l01746"></a>01746 } CHAN[127];
|
||
<a name="l01747"></a>01747 <span class="comment">/**** Note: Not all channels implemented on all devices. Up 64 can be implemented on */</span>
|
||
<a name="l01748"></a>01748 }; <span class="comment">/* end of ETPU_tag */</span>
|
||
<a name="l01749"></a>01749 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l01750"></a>01750 <span class="comment">/* MODULE : XBAR */</span>
|
||
<a name="l01751"></a>01751 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l01752"></a>01752 <span class="keyword">struct </span>XBAR_tag {
|
||
<a name="l01753"></a>01753 <span class="keyword">union </span>{
|
||
<a name="l01754"></a>01754 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01755"></a>01755 <span class="keyword">struct </span>{
|
||
<a name="l01756"></a>01756 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:4; <span class="comment">/* Master 7 Priority - Not implemented */</span>
|
||
<a name="l01757"></a>01757 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:4; <span class="comment">/* Master 6 Priority - Not implemented */</span>
|
||
<a name="l01758"></a>01758 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:4; <span class="comment">/* Master 5 Priority - Not implemented */</span>
|
||
<a name="l01759"></a>01759 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* */</span>
|
||
<a name="l01760"></a>01760 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MSTR4:3; <span class="comment">/* Master 4 Priority - Core load/store & Nexus port */</span>
|
||
<a name="l01761"></a>01761 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:4; <span class="comment">/* Master 3 Priority - Not implemented */</span>
|
||
<a name="l01762"></a>01762 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* */</span>
|
||
<a name="l01763"></a>01763 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MSTR2:3; <span class="comment">/* Master 2 Priority - Unused implemented master port */</span>
|
||
<a name="l01764"></a>01764 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* */</span>
|
||
<a name="l01765"></a>01765 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MSTR1:3; <span class="comment">/* Master 1 Priority - eDMA */</span>
|
||
<a name="l01766"></a>01766 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* */</span>
|
||
<a name="l01767"></a>01767 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MSTR0:3; <span class="comment">/* Master 0 Priority - e200z335 core Instruction */</span>
|
||
<a name="l01768"></a>01768 } B;
|
||
<a name="l01769"></a>01769 } MPR0; <span class="comment">/* Master Priority Register for Slave port 0 @baseaddress + 0x00 - Flash */</span>
|
||
<a name="l01770"></a>01770
|
||
<a name="l01771"></a>01771 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> XBAR_reserverd_35[3];
|
||
<a name="l01772"></a>01772
|
||
<a name="l01773"></a>01773 <span class="keyword">union </span>{
|
||
<a name="l01774"></a>01774 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01775"></a>01775 <span class="keyword">struct </span>{
|
||
<a name="l01776"></a>01776 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RO:1; <span class="comment">/* Read Only */</span>
|
||
<a name="l01777"></a>01777 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> HLP:1; <span class="comment">/* Halt Low Priority (new in MPC563xM) */</span>
|
||
<a name="l01778"></a>01778 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:6; <span class="comment">/* Slave General Purpose Control Register Reserved */</span>
|
||
<a name="l01779"></a>01779 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* High Priority Enable (new in MPC563xM - not implemented) */</span>
|
||
<a name="l01780"></a>01780 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* High Priority Enable (new in MPC563xM - not implemented) */</span>
|
||
<a name="l01781"></a>01781 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* High Priority Enable (new in MPC563xM - not implemented) */</span>
|
||
<a name="l01782"></a>01782 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> HPE4:1; <span class="comment">/* High Priority Enable (new in MPC563xM) */</span>
|
||
<a name="l01783"></a>01783 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* High Priority Enable (new in MPC563xM - not implemented) */</span>
|
||
<a name="l01784"></a>01784 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> HPE2:1; <span class="comment">/* High Priority Enable (new in MPC563xM) */</span>
|
||
<a name="l01785"></a>01785 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> HPE1:1; <span class="comment">/* High Priority Enable (new in MPC563xM) */</span>
|
||
<a name="l01786"></a>01786 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> HPE0:1; <span class="comment">/* High Priority Enable (new in MPC563xM) */</span>
|
||
<a name="l01787"></a>01787 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:6; <span class="comment">/* */</span>
|
||
<a name="l01788"></a>01788 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ARB:2; <span class="comment">/* Arbitration Mode */</span>
|
||
<a name="l01789"></a>01789 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:2; <span class="comment">/* */</span>
|
||
<a name="l01790"></a>01790 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PCTL:2; <span class="comment">/* Parking Control */</span>
|
||
<a name="l01791"></a>01791 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* */</span>
|
||
<a name="l01792"></a>01792 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PARK:3; <span class="comment">/* PARK */</span>
|
||
<a name="l01793"></a>01793 } B;
|
||
<a name="l01794"></a>01794 } SGPCR0; <span class="comment">/* Slave General Purpose Control Register 0 @baseaddress + 0x10 */</span>
|
||
<a name="l01795"></a>01795
|
||
<a name="l01796"></a>01796 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> XBAR_reserverd_71[59];
|
||
<a name="l01797"></a>01797
|
||
<a name="l01798"></a>01798 <span class="keyword">union </span>{
|
||
<a name="l01799"></a>01799 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01800"></a>01800 <span class="keyword">struct </span>{
|
||
<a name="l01801"></a>01801 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:4; <span class="comment">/* Master 7 Priority - Not implemented */</span>
|
||
<a name="l01802"></a>01802 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:4; <span class="comment">/* Master 6 Priority - Not implemented */</span>
|
||
<a name="l01803"></a>01803 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:4; <span class="comment">/* Master 5 Priority - Not implemented */</span>
|
||
<a name="l01804"></a>01804 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* */</span>
|
||
<a name="l01805"></a>01805 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MSTR4:3; <span class="comment">/* Master 4 Priority - Core load/store & Nexus port */</span>
|
||
<a name="l01806"></a>01806 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:4; <span class="comment">/* Master 3 Priority - Not implemented */</span>
|
||
<a name="l01807"></a>01807 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* */</span>
|
||
<a name="l01808"></a>01808 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MSTR2:3; <span class="comment">/* Master 2 Priority - Unused implemented master port */</span>
|
||
<a name="l01809"></a>01809 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* */</span>
|
||
<a name="l01810"></a>01810 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MSTR1:3; <span class="comment">/* Master 1 Priority - eDMA */</span>
|
||
<a name="l01811"></a>01811 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* */</span>
|
||
<a name="l01812"></a>01812 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MSTR0:3; <span class="comment">/* Master 0 Priority - e200z335 core Instruction */</span>
|
||
<a name="l01813"></a>01813 } B;
|
||
<a name="l01814"></a>01814 } MPR1; <span class="comment">/* Master Priority Register for Slave port 1 @baseaddress + 0x100 */</span>
|
||
<a name="l01815"></a>01815
|
||
<a name="l01816"></a>01816 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> XBAR_reserverd_105[3];
|
||
<a name="l01817"></a>01817
|
||
<a name="l01818"></a>01818 <span class="keyword">union </span>{
|
||
<a name="l01819"></a>01819 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01820"></a>01820 <span class="keyword">struct </span>{
|
||
<a name="l01821"></a>01821 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RO:1; <span class="comment">/* Read Only */</span>
|
||
<a name="l01822"></a>01822 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> HLP:1; <span class="comment">/* Halt Low Priority (new in MPC563xM) */</span>
|
||
<a name="l01823"></a>01823 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:6; <span class="comment">/* Slave General Purpose Control Register Reserved */</span>
|
||
<a name="l01824"></a>01824 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* High Priority Enable (new in MPC563xM - not implemented) */</span>
|
||
<a name="l01825"></a>01825 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* High Priority Enable (new in MPC563xM - not implemented) */</span>
|
||
<a name="l01826"></a>01826 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* High Priority Enable (new in MPC563xM - not implemented) */</span>
|
||
<a name="l01827"></a>01827 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> HPE4:1; <span class="comment">/* High Priority Enable (new in MPC563xM) */</span>
|
||
<a name="l01828"></a>01828 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* High Priority Enable (new in MPC563xM - not implemented) */</span>
|
||
<a name="l01829"></a>01829 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> HPE2:1; <span class="comment">/* High Priority Enable (new in MPC563xM) */</span>
|
||
<a name="l01830"></a>01830 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> HPE1:1; <span class="comment">/* High Priority Enable (new in MPC563xM) */</span>
|
||
<a name="l01831"></a>01831 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> HPE0:1; <span class="comment">/* High Priority Enable (new in MPC563xM) */</span>
|
||
<a name="l01832"></a>01832 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:6; <span class="comment">/* */</span>
|
||
<a name="l01833"></a>01833 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ARB:2; <span class="comment">/* Arbitration Mode */</span>
|
||
<a name="l01834"></a>01834 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:2; <span class="comment">/* */</span>
|
||
<a name="l01835"></a>01835 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PCTL:2; <span class="comment">/* Parking Control */</span>
|
||
<a name="l01836"></a>01836 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* */</span>
|
||
<a name="l01837"></a>01837 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PARK:3; <span class="comment">/* PARK */</span>
|
||
<a name="l01838"></a>01838 } B;
|
||
<a name="l01839"></a>01839 } SGPCR1; <span class="comment">/* Slave General Purpose Control Register 1 @baseaddress + 0x110 */</span>
|
||
<a name="l01840"></a>01840
|
||
<a name="l01841"></a>01841 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> XBAR_reserverd_141[59];
|
||
<a name="l01842"></a>01842
|
||
<a name="l01843"></a>01843 <span class="comment">/* Slave General Purpose Control Register 2 @baseaddress + 0x210 - not implemented */</span>
|
||
<a name="l01844"></a>01844
|
||
<a name="l01845"></a>01845 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> XBAR_reserverd_211[64];
|
||
<a name="l01846"></a>01846
|
||
<a name="l01847"></a>01847 <span class="keyword">union </span>{
|
||
<a name="l01848"></a>01848 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01849"></a>01849 <span class="keyword">struct </span>{
|
||
<a name="l01850"></a>01850 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:4; <span class="comment">/* Master 7 Priority - Not implemented */</span>
|
||
<a name="l01851"></a>01851 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:4; <span class="comment">/* Master 6 Priority - Not implemented */</span>
|
||
<a name="l01852"></a>01852 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:4; <span class="comment">/* Master 5 Priority - Not implemented */</span>
|
||
<a name="l01853"></a>01853 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* */</span>
|
||
<a name="l01854"></a>01854 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MSTR4:3; <span class="comment">/* Master 4 Priority - Core load/store & Nexus port */</span>
|
||
<a name="l01855"></a>01855 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:4; <span class="comment">/* Master 3 Priority - Not implemented */</span>
|
||
<a name="l01856"></a>01856 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* */</span>
|
||
<a name="l01857"></a>01857 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MSTR2:3; <span class="comment">/* Master 2 Priority - Unused implemented master port */</span>
|
||
<a name="l01858"></a>01858 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* */</span>
|
||
<a name="l01859"></a>01859 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MSTR1:3; <span class="comment">/* Master 1 Priority - eDMA */</span>
|
||
<a name="l01860"></a>01860 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* */</span>
|
||
<a name="l01861"></a>01861 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MSTR0:3; <span class="comment">/* Master 0 Priority - e200z335 core Instruction */</span>
|
||
<a name="l01862"></a>01862 } B;
|
||
<a name="l01863"></a>01863 } MPR3; <span class="comment">/* Master Priority Register for Slave port 3 @baseaddress + 0x300 */</span>
|
||
<a name="l01864"></a>01864
|
||
<a name="l01865"></a>01865 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> XBAR_reserverd_245[3];
|
||
<a name="l01866"></a>01866
|
||
<a name="l01867"></a>01867 <span class="keyword">union </span>{
|
||
<a name="l01868"></a>01868 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01869"></a>01869 <span class="keyword">struct </span>{
|
||
<a name="l01870"></a>01870 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RO:1; <span class="comment">/* Read Only */</span>
|
||
<a name="l01871"></a>01871 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> HLP:1; <span class="comment">/* Halt Low Priority (new in MPC563xM) */</span>
|
||
<a name="l01872"></a>01872 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:6; <span class="comment">/* Slave General Purpose Control Register Reserved */</span>
|
||
<a name="l01873"></a>01873 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* High Priority Enable (new in MPC563xM - not implemented) */</span>
|
||
<a name="l01874"></a>01874 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* High Priority Enable (new in MPC563xM - not implemented) */</span>
|
||
<a name="l01875"></a>01875 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* High Priority Enable (new in MPC563xM - not implemented) */</span>
|
||
<a name="l01876"></a>01876 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> HPE4:1; <span class="comment">/* High Priority Enable (new in MPC563xM) */</span>
|
||
<a name="l01877"></a>01877 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* High Priority Enable (new in MPC563xM - not implemented) */</span>
|
||
<a name="l01878"></a>01878 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> HPE2:1; <span class="comment">/* High Priority Enable (new in MPC563xM) */</span>
|
||
<a name="l01879"></a>01879 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> HPE1:1; <span class="comment">/* High Priority Enable (new in MPC563xM) */</span>
|
||
<a name="l01880"></a>01880 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> HPE0:1; <span class="comment">/* High Priority Enable (new in MPC563xM) */</span>
|
||
<a name="l01881"></a>01881 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:6; <span class="comment">/* */</span>
|
||
<a name="l01882"></a>01882 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ARB:2; <span class="comment">/* Arbitration Mode */</span>
|
||
<a name="l01883"></a>01883 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:2; <span class="comment">/* */</span>
|
||
<a name="l01884"></a>01884 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PCTL:2; <span class="comment">/* Parking Control */</span>
|
||
<a name="l01885"></a>01885 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* */</span>
|
||
<a name="l01886"></a>01886 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PARK:3; <span class="comment">/* PARK */</span>
|
||
<a name="l01887"></a>01887 } B;
|
||
<a name="l01888"></a>01888 } SGPCR3; <span class="comment">/* Slave General Purpose Control Register 3 @baseaddress + 0x310 */</span>
|
||
<a name="l01889"></a>01889
|
||
<a name="l01890"></a>01890 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> XBAR_reserverd_281[59];
|
||
<a name="l01891"></a>01891
|
||
<a name="l01892"></a>01892 <span class="comment">/* Slave General Purpose Control Register 4 @baseaddress + 0x410 - not implemented */</span>
|
||
<a name="l01893"></a>01893
|
||
<a name="l01894"></a>01894 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> XBAR_reserverd_351[64];
|
||
<a name="l01895"></a>01895
|
||
<a name="l01896"></a>01896 <span class="comment">/* Slave XBAR Port 5 Not implemented @baseaddress + 0x510 */</span>
|
||
<a name="l01897"></a>01897
|
||
<a name="l01898"></a>01898 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> XBAR_reserverd_421[64];
|
||
<a name="l01899"></a>01899
|
||
<a name="l01900"></a>01900 <span class="comment">/* Slave Port 6 not implemented @baseaddress + 0x610 */</span>
|
||
<a name="l01901"></a>01901
|
||
<a name="l01902"></a>01902 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> XBAR_reserverd_491[64];
|
||
<a name="l01903"></a>01903
|
||
<a name="l01904"></a>01904 <span class="keyword">union </span>{
|
||
<a name="l01905"></a>01905 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01906"></a>01906 <span class="keyword">struct </span>{
|
||
<a name="l01907"></a>01907 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:4; <span class="comment">/* Master 7 Priority - Not implemented */</span>
|
||
<a name="l01908"></a>01908 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:4; <span class="comment">/* Master 6 Priority - Not implemented */</span>
|
||
<a name="l01909"></a>01909 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:4; <span class="comment">/* Master 5 Priority - Not implemented */</span>
|
||
<a name="l01910"></a>01910 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* */</span>
|
||
<a name="l01911"></a>01911 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MSTR4:3; <span class="comment">/* Master 4 Priority - Core load/store & Nexus port */</span>
|
||
<a name="l01912"></a>01912 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:4; <span class="comment">/* Master 3 Priority - Not implemented */</span>
|
||
<a name="l01913"></a>01913 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* */</span>
|
||
<a name="l01914"></a>01914 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MSTR2:3; <span class="comment">/* Master 2 Priority - Unused implemented master port */</span>
|
||
<a name="l01915"></a>01915 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* */</span>
|
||
<a name="l01916"></a>01916 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MSTR1:3; <span class="comment">/* Master 1 Priority - eDMA */</span>
|
||
<a name="l01917"></a>01917 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* */</span>
|
||
<a name="l01918"></a>01918 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MSTR0:3; <span class="comment">/* Master 0 Priority - e200z335 core Instruction */</span>
|
||
<a name="l01919"></a>01919 } B;
|
||
<a name="l01920"></a>01920 } MPR7; <span class="comment">/* Master Priority Register for Slave port 7 @baseaddress + 0x700 */</span>
|
||
<a name="l01921"></a>01921
|
||
<a name="l01922"></a>01922 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> XBAR_reserverd_525[3];
|
||
<a name="l01923"></a>01923
|
||
<a name="l01924"></a>01924 <span class="keyword">union </span>{
|
||
<a name="l01925"></a>01925 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01926"></a>01926 <span class="keyword">struct </span>{
|
||
<a name="l01927"></a>01927 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RO:1; <span class="comment">/* Read Only */</span>
|
||
<a name="l01928"></a>01928 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> HLP:1; <span class="comment">/* Halt Low Priority (new in MPC563xM) */</span>
|
||
<a name="l01929"></a>01929 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:6; <span class="comment">/* Slave General Purpose Control Register Reserved */</span>
|
||
<a name="l01930"></a>01930 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* High Priority Enable (new in MPC563xM - not implemented) */</span>
|
||
<a name="l01931"></a>01931 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* High Priority Enable (new in MPC563xM - not implemented) */</span>
|
||
<a name="l01932"></a>01932 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* High Priority Enable (new in MPC563xM - not implemented) */</span>
|
||
<a name="l01933"></a>01933 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> HPE4:1; <span class="comment">/* High Priority Enable (new in MPC563xM) */</span>
|
||
<a name="l01934"></a>01934 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* High Priority Enable (new in MPC563xM - not implemented) */</span>
|
||
<a name="l01935"></a>01935 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> HPE2:1; <span class="comment">/* High Priority Enable (new in MPC563xM) */</span>
|
||
<a name="l01936"></a>01936 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> HPE1:1; <span class="comment">/* High Priority Enable (new in MPC563xM) */</span>
|
||
<a name="l01937"></a>01937 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> HPE0:1; <span class="comment">/* High Priority Enable (new in MPC563xM) */</span>
|
||
<a name="l01938"></a>01938 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:6; <span class="comment">/* */</span>
|
||
<a name="l01939"></a>01939 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ARB:2; <span class="comment">/* Arbitration Mode */</span>
|
||
<a name="l01940"></a>01940 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:2; <span class="comment">/* */</span>
|
||
<a name="l01941"></a>01941 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PCTL:2; <span class="comment">/* Parking Control */</span>
|
||
<a name="l01942"></a>01942 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* */</span>
|
||
<a name="l01943"></a>01943 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PARK:3; <span class="comment">/* PARK */</span>
|
||
<a name="l01944"></a>01944 } B;
|
||
<a name="l01945"></a>01945 } SGPCR7; <span class="comment">/* Slave General Purpose Control Register 7 @baseaddress + 0x710 */</span>
|
||
<a name="l01946"></a>01946
|
||
<a name="l01947"></a>01947 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> XBAR_reserverd_561[59];
|
||
<a name="l01948"></a>01948
|
||
<a name="l01949"></a>01949 <span class="keyword">union </span>{
|
||
<a name="l01950"></a>01950 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01951"></a>01951 <span class="keyword">struct </span>{
|
||
<a name="l01952"></a>01952 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:29; <span class="comment">/* */</span>
|
||
<a name="l01953"></a>01953 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> AULB:3; <span class="comment">/* Arbitrate on Undefined Length Bursts */</span>
|
||
<a name="l01954"></a>01954 } B;
|
||
<a name="l01955"></a>01955 } MGPCR0; <span class="comment">/* Master General Purpose Control Register 0 @baseaddress + 0x800 */</span>
|
||
<a name="l01956"></a>01956
|
||
<a name="l01957"></a>01957 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> XBAR_reserverd_564[63];
|
||
<a name="l01958"></a>01958
|
||
<a name="l01959"></a>01959 <span class="keyword">union </span>{
|
||
<a name="l01960"></a>01960 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01961"></a>01961 <span class="keyword">struct </span>{
|
||
<a name="l01962"></a>01962 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:29; <span class="comment">/* */</span>
|
||
<a name="l01963"></a>01963 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> AULB:3; <span class="comment">/* Arbitrate on Undefined Length Bursts */</span>
|
||
<a name="l01964"></a>01964 } B;
|
||
<a name="l01965"></a>01965 } MGPCR1; <span class="comment">/* Master General Purpose Control Register 1 @baseaddress + 0x900 */</span>
|
||
<a name="l01966"></a>01966
|
||
<a name="l01967"></a>01967 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> XBAR_reserverd_567[63];
|
||
<a name="l01968"></a>01968
|
||
<a name="l01969"></a>01969 <span class="keyword">union </span>{
|
||
<a name="l01970"></a>01970 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01971"></a>01971 <span class="keyword">struct </span>{
|
||
<a name="l01972"></a>01972 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:29; <span class="comment">/* */</span>
|
||
<a name="l01973"></a>01973 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> AULB:3; <span class="comment">/* Arbitrate on Undefined Length Bursts */</span>
|
||
<a name="l01974"></a>01974 } B;
|
||
<a name="l01975"></a>01975 } MGPCR2; <span class="comment">/* Master General Purpose Control Register 2 @baseaddress + 0xA00 */</span>
|
||
<a name="l01976"></a>01976
|
||
<a name="l01977"></a>01977 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> XBAR_reserverd_570[63];
|
||
<a name="l01978"></a>01978
|
||
<a name="l01979"></a>01979 <span class="comment">/* Master General Purpose Control Register 3 not implemented @baseaddress + 0xB00 */</span>
|
||
<a name="l01980"></a>01980
|
||
<a name="l01981"></a>01981 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> XBAR_reserverd_573[64];
|
||
<a name="l01982"></a>01982
|
||
<a name="l01983"></a>01983 <span class="keyword">union </span>{
|
||
<a name="l01984"></a>01984 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l01985"></a>01985 <span class="keyword">struct </span>{
|
||
<a name="l01986"></a>01986 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:29; <span class="comment">/* */</span>
|
||
<a name="l01987"></a>01987 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> AULB:3; <span class="comment">/* Arbitrate on Undefined Length Bursts */</span>
|
||
<a name="l01988"></a>01988 } B;
|
||
<a name="l01989"></a>01989 } MGPCR4; <span class="comment">/* Master General Purpose Control Register 4 @baseaddress + 0xC00 */</span>
|
||
<a name="l01990"></a>01990
|
||
<a name="l01991"></a>01991 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> XBAR_reserverd_576[64];
|
||
<a name="l01992"></a>01992
|
||
<a name="l01993"></a>01993 <span class="comment">/* Master General Purpose Control Register 5 not implemented @baseaddress + 0xD00 */</span>
|
||
<a name="l01994"></a>01994
|
||
<a name="l01995"></a>01995 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> XBAR_reserverd_579[64];
|
||
<a name="l01996"></a>01996
|
||
<a name="l01997"></a>01997 <span class="comment">/* Master General Purpose Control Register 6 not implemented @baseaddress + 0xE00 */</span>
|
||
<a name="l01998"></a>01998
|
||
<a name="l01999"></a>01999 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> XBAR_reserverd_582[64];
|
||
<a name="l02000"></a>02000
|
||
<a name="l02001"></a>02001 <span class="comment">/* Master General Purpose Control Register 7 not implemented @baseaddress + 0xF00 */</span>
|
||
<a name="l02002"></a>02002
|
||
<a name="l02003"></a>02003 }; <span class="comment">/* end of XBAR_tag */</span>
|
||
<a name="l02004"></a>02004 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l02005"></a>02005 <span class="comment">/* MODULE : ECSM */</span>
|
||
<a name="l02006"></a>02006 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l02007"></a>02007 <span class="keyword">struct </span>ECSM_tag {
|
||
<a name="l02008"></a>02008 <span class="comment">/* SWTCR, SWTSR and SWTIR don't exist in MPC563xM */</span>
|
||
<a name="l02009"></a>02009 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> ecsm_reserved1[16];
|
||
<a name="l02010"></a>02010
|
||
<a name="l02011"></a>02011 <a class="code" href="group___s_t_m8___c_o_r_e.html#gaba7bc1797add20fe3efdf37ced1182c5">uint8_t</a> ecsm_reserved3[3]; <span class="comment">/* base + 0x40 */</span>
|
||
<a name="l02012"></a>02012
|
||
<a name="l02013"></a>02013 <span class="keyword">union </span>{
|
||
<a name="l02014"></a>02014 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> R;
|
||
<a name="l02015"></a>02015 <span class="keyword">struct </span>{
|
||
<a name="l02016"></a>02016 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a>:6;
|
||
<a name="l02017"></a>02017 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> ERNCR:1; <span class="comment">/* <URM>EPRNCR</URM> */</span>
|
||
<a name="l02018"></a>02018 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> EFNCR:1; <span class="comment">/* <URM>EPFNCR</URM> */</span>
|
||
<a name="l02019"></a>02019 } B;
|
||
<a name="l02020"></a>02020 } ECR; <span class="comment">/* ECC Configuration Register */</span>
|
||
<a name="l02021"></a>02021
|
||
<a name="l02022"></a>02022 <a class="code" href="group___s_t_m8___c_o_r_e.html#gaba7bc1797add20fe3efdf37ced1182c5">uint8_t</a> ecsm_reserved4[3]; <span class="comment">/* base + 0x44 */</span>
|
||
<a name="l02023"></a>02023
|
||
<a name="l02024"></a>02024 <span class="keyword">union </span>{
|
||
<a name="l02025"></a>02025 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> R;
|
||
<a name="l02026"></a>02026 <span class="keyword">struct </span>{
|
||
<a name="l02027"></a>02027 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a>:6;
|
||
<a name="l02028"></a>02028 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> RNCE:1; <span class="comment">/* <URM>PRNCE</URM> */</span>
|
||
<a name="l02029"></a>02029 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> FNCE:1; <span class="comment">/* <URM>PFNCE</URM> */</span>
|
||
<a name="l02030"></a>02030 } B;
|
||
<a name="l02031"></a>02031 } ESR; <span class="comment">/* ECC Status Register */</span>
|
||
<a name="l02032"></a>02032
|
||
<a name="l02033"></a>02033 <span class="comment">/* EEGR don't exist in MPC563xM */</span>
|
||
<a name="l02034"></a>02034 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> ecsm_reserved4a[2];
|
||
<a name="l02035"></a>02035
|
||
<a name="l02036"></a>02036 <span class="keyword">union </span>{
|
||
<a name="l02037"></a>02037 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02038"></a>02038 <span class="keyword">struct </span>{
|
||
<a name="l02039"></a>02039 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> FEAR:32; <span class="comment">/* <URM>PFEAR</URM> */</span>
|
||
<a name="l02040"></a>02040 } B;
|
||
<a name="l02041"></a>02041 } FEAR; <span class="comment">/* Flash ECC Address Register <URM>PFEAR</URM> - 0x50 */</span>
|
||
<a name="l02042"></a>02042
|
||
<a name="l02043"></a>02043 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga1f1825b69244eb3ad2c7165ddc99c956">uint16_t</a> ecsm_reserved4b;
|
||
<a name="l02044"></a>02044
|
||
<a name="l02045"></a>02045 <span class="keyword">union </span>{
|
||
<a name="l02046"></a>02046 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> R;
|
||
<a name="l02047"></a>02047 <span class="keyword">struct </span>{
|
||
<a name="l02048"></a>02048 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a>:4;
|
||
<a name="l02049"></a>02049 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> FEMR:4; <span class="comment">/* <URM>PFEMR</URM> */</span>
|
||
<a name="l02050"></a>02050 } B;
|
||
<a name="l02051"></a>02051 } FEMR; <span class="comment">/* Flash ECC Master Register <URM>PFEMR</URM> */</span>
|
||
<a name="l02052"></a>02052
|
||
<a name="l02053"></a>02053 <span class="keyword">union </span>{
|
||
<a name="l02054"></a>02054 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> R;
|
||
<a name="l02055"></a>02055 <span class="keyword">struct </span>{
|
||
<a name="l02056"></a>02056 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> WRITE:1;
|
||
<a name="l02057"></a>02057 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> SIZE:3;
|
||
<a name="l02058"></a>02058 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> PROT0:1; <span class="comment">/* <URM>PROTECTION</URM> */</span>
|
||
<a name="l02059"></a>02059 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> PROT1:1; <span class="comment">/* <URM>PROTECTION</URM> */</span>
|
||
<a name="l02060"></a>02060 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> PROT2:1; <span class="comment">/* <URM>PROTECTION</URM> */</span>
|
||
<a name="l02061"></a>02061 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> PROT3:1; <span class="comment">/* <URM>PROTECTION</URM> */</span>
|
||
<a name="l02062"></a>02062 } B;
|
||
<a name="l02063"></a>02063 } FEAT; <span class="comment">/* Flash ECC Attributes Register <URM>PFEAT</URM> */</span>
|
||
<a name="l02064"></a>02064
|
||
<a name="l02065"></a>02065 <span class="keyword">union </span>{
|
||
<a name="l02066"></a>02066 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02067"></a>02067 <span class="keyword">struct </span>{
|
||
<a name="l02068"></a>02068 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> FEDH:32; <span class="comment">/* <URM>PFEDR</URM> */</span>
|
||
<a name="l02069"></a>02069 } B;
|
||
<a name="l02070"></a>02070 } FEDRH; <span class="comment">/* Flash ECC Data High Register <URM>PFEDRH</URM> */</span>
|
||
<a name="l02071"></a>02071
|
||
<a name="l02072"></a>02072 <span class="keyword">union </span>{
|
||
<a name="l02073"></a>02073 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02074"></a>02074 <span class="keyword">struct </span>{
|
||
<a name="l02075"></a>02075 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> FEDL:32; <span class="comment">/* <URM>PFEDR</URM> */</span>
|
||
<a name="l02076"></a>02076 } B;
|
||
<a name="l02077"></a>02077 } FEDRL; <span class="comment">/* Flash ECC Data Low Register <URM>PFEDRL</URM> */</span>
|
||
<a name="l02078"></a>02078
|
||
<a name="l02079"></a>02079 <span class="keyword">union </span>{
|
||
<a name="l02080"></a>02080 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02081"></a>02081 <span class="keyword">struct </span>{
|
||
<a name="l02082"></a>02082 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> REAR:32; <span class="comment">/* <URM>PREAR</URM> */</span>
|
||
<a name="l02083"></a>02083 } B;
|
||
<a name="l02084"></a>02084 } REAR; <span class="comment">/* RAM ECC Address <URM>PREAR</URM> */</span>
|
||
<a name="l02085"></a>02085
|
||
<a name="l02086"></a>02086 <a class="code" href="group___s_t_m8___c_o_r_e.html#gaba7bc1797add20fe3efdf37ced1182c5">uint8_t</a> ecsm_reserved5;
|
||
<a name="l02087"></a>02087
|
||
<a name="l02088"></a>02088 <span class="keyword">union </span>{
|
||
<a name="l02089"></a>02089 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> R;
|
||
<a name="l02090"></a>02090 <span class="keyword">struct </span>{
|
||
<a name="l02091"></a>02091 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> PRESR:8;
|
||
<a name="l02092"></a>02092 } B;
|
||
<a name="l02093"></a>02093 } PRESR; <span class="comment">/* RAM ECC Syndrome (new in MPC563xM) */</span>
|
||
<a name="l02094"></a>02094
|
||
<a name="l02095"></a>02095 <span class="keyword">union </span>{
|
||
<a name="l02096"></a>02096 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> R;
|
||
<a name="l02097"></a>02097 <span class="keyword">struct </span>{
|
||
<a name="l02098"></a>02098 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a>:4;
|
||
<a name="l02099"></a>02099 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> REMR:4; <span class="comment">/* <URM>PREMR</URM> */</span>
|
||
<a name="l02100"></a>02100 } B;
|
||
<a name="l02101"></a>02101 } REMR; <span class="comment">/* RAM ECC Master <URM>PREMR</URM> */</span>
|
||
<a name="l02102"></a>02102
|
||
<a name="l02103"></a>02103 <span class="keyword">union </span>{
|
||
<a name="l02104"></a>02104 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> R;
|
||
<a name="l02105"></a>02105 <span class="keyword">struct </span>{
|
||
<a name="l02106"></a>02106 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> WRITE:1;
|
||
<a name="l02107"></a>02107 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> SIZE:3;
|
||
<a name="l02108"></a>02108 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> PROT0:1; <span class="comment">/* <URM>PROTECTION</URM> */</span>
|
||
<a name="l02109"></a>02109 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> PROT1:1; <span class="comment">/* <URM>PROTECTION</URM> */</span>
|
||
<a name="l02110"></a>02110 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> PROT2:1; <span class="comment">/* <URM>PROTECTION</URM> */</span>
|
||
<a name="l02111"></a>02111 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> PROT3:1; <span class="comment">/* <URM>PROTECTION</URM> */</span>
|
||
<a name="l02112"></a>02112 } B;
|
||
<a name="l02113"></a>02113 } REAT; <span class="comment">/* RAM ECC Attributes Register <URM>PREAT</URM> */</span>
|
||
<a name="l02114"></a>02114
|
||
<a name="l02115"></a>02115 <span class="keyword">union </span>{
|
||
<a name="l02116"></a>02116 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02117"></a>02117 <span class="keyword">struct </span>{
|
||
<a name="l02118"></a>02118 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> REDH:32; <span class="comment">/* <URM>PREDR</URM> */</span>
|
||
<a name="l02119"></a>02119 } B;
|
||
<a name="l02120"></a>02120 } REDRH; <span class="comment">/* RAM ECC Data High Register <URM>PREDRH</URM> */</span>
|
||
<a name="l02121"></a>02121
|
||
<a name="l02122"></a>02122 <span class="keyword">union </span>{
|
||
<a name="l02123"></a>02123 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02124"></a>02124 <span class="keyword">struct </span>{
|
||
<a name="l02125"></a>02125 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> REDL:32; <span class="comment">/* <URM>PREDR</URM> */</span>
|
||
<a name="l02126"></a>02126 } B;
|
||
<a name="l02127"></a>02127 } REDRL; <span class="comment">/* RAMECC Data Low Register <URM>PREDRL</URM> */</span>
|
||
<a name="l02128"></a>02128
|
||
<a name="l02129"></a>02129 };
|
||
<a name="l02130"></a>02130 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l02131"></a>02131 <span class="comment">/* MODULE : EDMA */</span>
|
||
<a name="l02132"></a>02132 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l02133"></a>02133 <span class="keyword">struct </span>EDMA_tag {
|
||
<a name="l02134"></a>02134 <span class="keyword">union </span>{
|
||
<a name="l02135"></a>02135 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02136"></a>02136 <span class="keyword">struct </span>{
|
||
<a name="l02137"></a>02137 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:14; <span class="comment">/* Reserved */</span>
|
||
<a name="l02138"></a>02138 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CX:1; <span class="comment">/* Cancel Transfer (new in MPC563xM) */</span>
|
||
<a name="l02139"></a>02139 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ECX:1; <span class="comment">/* Error Cancel Transfer (new in MPC563xM) */</span>
|
||
<a name="l02140"></a>02140 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> GRP3PRI:2; <span class="comment">/* Channel Group 3 Priority (new in MPC563xM) */</span>
|
||
<a name="l02141"></a>02141 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> GRP2PRI:2; <span class="comment">/* Channel Group 2 Priority (new in MPC563xM) */</span>
|
||
<a name="l02142"></a>02142 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> GRP1PRI:2; <span class="comment">/* Channel Group 1 Priority */</span>
|
||
<a name="l02143"></a>02143 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> GRP0PRI:2; <span class="comment">/* Channel Group 0 Priority */</span>
|
||
<a name="l02144"></a>02144 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EMLM:1; <span class="comment">/* Enable Minor Loop Mapping (new in MPC563xM) */</span>
|
||
<a name="l02145"></a>02145 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CLM:1; <span class="comment">/* Continuous Link Mode (new in MPC563xM) */</span>
|
||
<a name="l02146"></a>02146 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> HALT:1; <span class="comment">/* Halt DMA Operations (new in MPC563xM) */</span>
|
||
<a name="l02147"></a>02147 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> HOE:1; <span class="comment">/* Halt On Error (new in MPC563xM) */</span>
|
||
<a name="l02148"></a>02148 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERGA:1; <span class="comment">/* Enable Round Robin Group Arbitration */</span>
|
||
<a name="l02149"></a>02149 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERCA:1; <span class="comment">/* Enable Round Robin Channel Arbitration */</span>
|
||
<a name="l02150"></a>02150 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EDBG:1; <span class="comment">/* Enable Debug */</span>
|
||
<a name="l02151"></a>02151 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EBW:1; <span class="comment">/* Enable Buffered Writes */</span>
|
||
<a name="l02152"></a>02152 } B;
|
||
<a name="l02153"></a>02153 } CR; <span class="comment">/* DMA Control Register <URM>DMACR</URM> @baseaddress + 0x0 */</span>
|
||
<a name="l02154"></a>02154
|
||
<a name="l02155"></a>02155 <span class="keyword">union </span>{
|
||
<a name="l02156"></a>02156 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02157"></a>02157 <span class="keyword">struct </span>{
|
||
<a name="l02158"></a>02158 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> VLD:1; <span class="comment">/* Logical OR of all DMAERRH */</span>
|
||
<a name="l02159"></a>02159
|
||
<a name="l02160"></a>02160 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:14; <span class="comment">/* Reserved */</span>
|
||
<a name="l02161"></a>02161 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ECX:1; <span class="comment">/* (new in MPC563xM) */</span>
|
||
<a name="l02162"></a>02162 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> GPE:1; <span class="comment">/* Group Priority Error */</span>
|
||
<a name="l02163"></a>02163 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CPE:1; <span class="comment">/* Channel Priority Error */</span>
|
||
<a name="l02164"></a>02164 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERRCHN:6; <span class="comment">/* ERRCHN[5:0] Error Channel Number or The channel number of the last recorded error */</span>
|
||
<a name="l02165"></a>02165 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SAE:1; <span class="comment">/* Source Address Error 0 */</span>
|
||
<a name="l02166"></a>02166 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SOE:1; <span class="comment">/* Source Offset Error */</span>
|
||
<a name="l02167"></a>02167 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DAE:1; <span class="comment">/* Destination Address Error */</span>
|
||
<a name="l02168"></a>02168 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DOE:1; <span class="comment">/* Destination Offset Error */</span>
|
||
<a name="l02169"></a>02169 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> NCE:1; <span class="comment">/* Nbytes/Citer Configuration Error */</span>
|
||
<a name="l02170"></a>02170 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SGE:1; <span class="comment">/* Scatter/Gather Configuration Error */</span>
|
||
<a name="l02171"></a>02171 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SBE:1; <span class="comment">/* Source Bus Error */</span>
|
||
<a name="l02172"></a>02172 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DBE:1; <span class="comment">/* Destination Bus Error */</span>
|
||
<a name="l02173"></a>02173
|
||
<a name="l02174"></a>02174 } B;
|
||
<a name="l02175"></a>02175 } ESR; <span class="comment">/* <URM>DMAES</URM> Error Status Register */</span>
|
||
<a name="l02176"></a>02176
|
||
<a name="l02177"></a>02177 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> edma_reserved_erqrh;
|
||
<a name="l02178"></a>02178
|
||
<a name="l02179"></a>02179 <span class="keyword">union </span>{
|
||
<a name="l02180"></a>02180 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02181"></a>02181 <span class="keyword">struct </span>{
|
||
<a name="l02182"></a>02182 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERQ31:1;
|
||
<a name="l02183"></a>02183 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERQ30:1;
|
||
<a name="l02184"></a>02184 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERQ29:1;
|
||
<a name="l02185"></a>02185 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERQ28:1;
|
||
<a name="l02186"></a>02186 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERQ27:1;
|
||
<a name="l02187"></a>02187 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERQ26:1;
|
||
<a name="l02188"></a>02188 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERQ25:1;
|
||
<a name="l02189"></a>02189 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERQ24:1;
|
||
<a name="l02190"></a>02190 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERQ23:1;
|
||
<a name="l02191"></a>02191 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERQ22:1;
|
||
<a name="l02192"></a>02192 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERQ21:1;
|
||
<a name="l02193"></a>02193 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERQ20:1;
|
||
<a name="l02194"></a>02194 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERQ19:1;
|
||
<a name="l02195"></a>02195 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERQ18:1;
|
||
<a name="l02196"></a>02196 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERQ17:1;
|
||
<a name="l02197"></a>02197 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERQ16:1;
|
||
<a name="l02198"></a>02198 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERQ15:1;
|
||
<a name="l02199"></a>02199 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERQ14:1;
|
||
<a name="l02200"></a>02200 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERQ13:1;
|
||
<a name="l02201"></a>02201 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERQ12:1;
|
||
<a name="l02202"></a>02202 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERQ11:1;
|
||
<a name="l02203"></a>02203 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERQ10:1;
|
||
<a name="l02204"></a>02204 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERQ09:1;
|
||
<a name="l02205"></a>02205 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERQ08:1;
|
||
<a name="l02206"></a>02206 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERQ07:1;
|
||
<a name="l02207"></a>02207 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERQ06:1;
|
||
<a name="l02208"></a>02208 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERQ05:1;
|
||
<a name="l02209"></a>02209 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERQ04:1;
|
||
<a name="l02210"></a>02210 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERQ03:1;
|
||
<a name="l02211"></a>02211 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERQ02:1;
|
||
<a name="l02212"></a>02212 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERQ01:1;
|
||
<a name="l02213"></a>02213 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERQ00:1;
|
||
<a name="l02214"></a>02214 } B;
|
||
<a name="l02215"></a>02215 } ERQRL; <span class="comment">/* <URM>DMAERQL</URM> ,DMA Enable Request Register Low */</span>
|
||
<a name="l02216"></a>02216
|
||
<a name="l02217"></a>02217 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> edma_reserved_eeirh;
|
||
<a name="l02218"></a>02218
|
||
<a name="l02219"></a>02219 <span class="keyword">union </span>{
|
||
<a name="l02220"></a>02220 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02221"></a>02221 <span class="keyword">struct </span>{
|
||
<a name="l02222"></a>02222 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EEI31:1;
|
||
<a name="l02223"></a>02223 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EEI30:1;
|
||
<a name="l02224"></a>02224 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EEI29:1;
|
||
<a name="l02225"></a>02225 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EEI28:1;
|
||
<a name="l02226"></a>02226 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EEI27:1;
|
||
<a name="l02227"></a>02227 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EEI26:1;
|
||
<a name="l02228"></a>02228 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EEI25:1;
|
||
<a name="l02229"></a>02229 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EEI24:1;
|
||
<a name="l02230"></a>02230 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EEI23:1;
|
||
<a name="l02231"></a>02231 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EEI22:1;
|
||
<a name="l02232"></a>02232 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EEI21:1;
|
||
<a name="l02233"></a>02233 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EEI20:1;
|
||
<a name="l02234"></a>02234 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EEI19:1;
|
||
<a name="l02235"></a>02235 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EEI18:1;
|
||
<a name="l02236"></a>02236 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EEI17:1;
|
||
<a name="l02237"></a>02237 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EEI16:1;
|
||
<a name="l02238"></a>02238 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EEI15:1;
|
||
<a name="l02239"></a>02239 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EEI14:1;
|
||
<a name="l02240"></a>02240 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EEI13:1;
|
||
<a name="l02241"></a>02241 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EEI12:1;
|
||
<a name="l02242"></a>02242 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EEI11:1;
|
||
<a name="l02243"></a>02243 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EEI10:1;
|
||
<a name="l02244"></a>02244 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EEI09:1;
|
||
<a name="l02245"></a>02245 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EEI08:1;
|
||
<a name="l02246"></a>02246 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EEI07:1;
|
||
<a name="l02247"></a>02247 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EEI06:1;
|
||
<a name="l02248"></a>02248 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EEI05:1;
|
||
<a name="l02249"></a>02249 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EEI04:1;
|
||
<a name="l02250"></a>02250 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EEI03:1;
|
||
<a name="l02251"></a>02251 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EEI02:1;
|
||
<a name="l02252"></a>02252 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EEI01:1;
|
||
<a name="l02253"></a>02253 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EEI00:1;
|
||
<a name="l02254"></a>02254 } B;
|
||
<a name="l02255"></a>02255 } EEIRL; <span class="comment">/* <URM>DMAEEIL</URM> , DMA Enable Error Interrupt Register Low */</span>
|
||
<a name="l02256"></a>02256
|
||
<a name="l02257"></a>02257 <span class="keyword">union </span>{
|
||
<a name="l02258"></a>02258 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> R;
|
||
<a name="l02259"></a>02259 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> B; <span class="comment">/* <URM>NOP:1 SERQ:7</URM> */</span>
|
||
<a name="l02260"></a>02260 } SERQR; <span class="comment">/* <URM>DMASERQ</URM> , DMA Set Enable Request Register */</span>
|
||
<a name="l02261"></a>02261
|
||
<a name="l02262"></a>02262 <span class="keyword">union </span>{
|
||
<a name="l02263"></a>02263 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> R;
|
||
<a name="l02264"></a>02264 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> B; <span class="comment">/* <URM>NOP:1 CERQ:7</URM> */</span>
|
||
<a name="l02265"></a>02265 } CERQR; <span class="comment">/* <URM>DMACERQ</URM> , DMA Clear Enable Request Register */</span>
|
||
<a name="l02266"></a>02266
|
||
<a name="l02267"></a>02267 <span class="keyword">union </span>{
|
||
<a name="l02268"></a>02268 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> R;
|
||
<a name="l02269"></a>02269 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> B; <span class="comment">/* <URM>NOP:1 SEEI:7</URM> */</span>
|
||
<a name="l02270"></a>02270 } SEEIR; <span class="comment">/* <URM>DMASEEI</URM> , DMA Set Enable Error Interrupt Register */</span>
|
||
<a name="l02271"></a>02271
|
||
<a name="l02272"></a>02272 <span class="keyword">union </span>{
|
||
<a name="l02273"></a>02273 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> R;
|
||
<a name="l02274"></a>02274 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> B; <span class="comment">/* <URM>NOP:1 CEEI:7</URM> */</span>
|
||
<a name="l02275"></a>02275 } CEEIR; <span class="comment">/* <URM>DMACEEI</URM> , DMA Clear Enable Error Interrupt Register */</span>
|
||
<a name="l02276"></a>02276
|
||
<a name="l02277"></a>02277 <span class="keyword">union </span>{
|
||
<a name="l02278"></a>02278 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> R;
|
||
<a name="l02279"></a>02279 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> B; <span class="comment">/* <URM>NOP:1 CINT:7</URM> */</span>
|
||
<a name="l02280"></a>02280 } CIRQR; <span class="comment">/* <URM>DMACINT</URM> , DMA Clear Interrupt Request Register */</span>
|
||
<a name="l02281"></a>02281
|
||
<a name="l02282"></a>02282 <span class="keyword">union </span>{
|
||
<a name="l02283"></a>02283 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> R;
|
||
<a name="l02284"></a>02284 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> B; <span class="comment">/* <URM>NOP:1 CERR:7</URM> */</span>
|
||
<a name="l02285"></a>02285 } CER; <span class="comment">/* <URM>DMACERR</URM> , DMA Clear error Register */</span>
|
||
<a name="l02286"></a>02286
|
||
<a name="l02287"></a>02287 <span class="keyword">union </span>{
|
||
<a name="l02288"></a>02288 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> R;
|
||
<a name="l02289"></a>02289 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> B; <span class="comment">/* <URM>NOP:1 SSRT:7</URM> */</span>
|
||
<a name="l02290"></a>02290 } SSBR; <span class="comment">/* <URM>DMASSRT</URM> , Set Start Bit Register */</span>
|
||
<a name="l02291"></a>02291
|
||
<a name="l02292"></a>02292 <span class="keyword">union </span>{
|
||
<a name="l02293"></a>02293 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> R;
|
||
<a name="l02294"></a>02294 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> B; <span class="comment">/* <URM>NOP:1 CDNE:7</URM> */</span>
|
||
<a name="l02295"></a>02295 } CDSBR; <span class="comment">/* <URM>DMACDNE</URM> , Clear Done Status Bit Register */</span>
|
||
<a name="l02296"></a>02296
|
||
<a name="l02297"></a>02297 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> edma_reserved_irqrh;
|
||
<a name="l02298"></a>02298
|
||
<a name="l02299"></a>02299 <span class="keyword">union </span>{
|
||
<a name="l02300"></a>02300 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02301"></a>02301 <span class="keyword">struct </span>{
|
||
<a name="l02302"></a>02302 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> INT31:1;
|
||
<a name="l02303"></a>02303 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> INT30:1;
|
||
<a name="l02304"></a>02304 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> INT29:1;
|
||
<a name="l02305"></a>02305 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> INT28:1;
|
||
<a name="l02306"></a>02306 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> INT27:1;
|
||
<a name="l02307"></a>02307 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> INT26:1;
|
||
<a name="l02308"></a>02308 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> INT25:1;
|
||
<a name="l02309"></a>02309 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> INT24:1;
|
||
<a name="l02310"></a>02310 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> INT23:1;
|
||
<a name="l02311"></a>02311 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> INT22:1;
|
||
<a name="l02312"></a>02312 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> INT21:1;
|
||
<a name="l02313"></a>02313 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> INT20:1;
|
||
<a name="l02314"></a>02314 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> INT19:1;
|
||
<a name="l02315"></a>02315 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> INT18:1;
|
||
<a name="l02316"></a>02316 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> INT17:1;
|
||
<a name="l02317"></a>02317 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> INT16:1;
|
||
<a name="l02318"></a>02318 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> INT15:1;
|
||
<a name="l02319"></a>02319 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> INT14:1;
|
||
<a name="l02320"></a>02320 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> INT13:1;
|
||
<a name="l02321"></a>02321 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> INT12:1;
|
||
<a name="l02322"></a>02322 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> INT11:1;
|
||
<a name="l02323"></a>02323 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> INT10:1;
|
||
<a name="l02324"></a>02324 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> INT09:1;
|
||
<a name="l02325"></a>02325 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> INT08:1;
|
||
<a name="l02326"></a>02326 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> INT07:1;
|
||
<a name="l02327"></a>02327 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> INT06:1;
|
||
<a name="l02328"></a>02328 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> INT05:1;
|
||
<a name="l02329"></a>02329 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> INT04:1;
|
||
<a name="l02330"></a>02330 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> INT03:1;
|
||
<a name="l02331"></a>02331 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> INT02:1;
|
||
<a name="l02332"></a>02332 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> INT01:1;
|
||
<a name="l02333"></a>02333 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> INT00:1;
|
||
<a name="l02334"></a>02334 } B;
|
||
<a name="l02335"></a>02335 } IRQRL; <span class="comment">/* <URM>DMAINTL</URM> , DMA Interrupt Request Low */</span>
|
||
<a name="l02336"></a>02336
|
||
<a name="l02337"></a>02337 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> edma_reserved_erh;
|
||
<a name="l02338"></a>02338
|
||
<a name="l02339"></a>02339 <span class="keyword">union </span>{
|
||
<a name="l02340"></a>02340 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02341"></a>02341 <span class="keyword">struct </span>{
|
||
<a name="l02342"></a>02342 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERR31:1;
|
||
<a name="l02343"></a>02343 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERR30:1;
|
||
<a name="l02344"></a>02344 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERR29:1;
|
||
<a name="l02345"></a>02345 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERR28:1;
|
||
<a name="l02346"></a>02346 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERR27:1;
|
||
<a name="l02347"></a>02347 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERR26:1;
|
||
<a name="l02348"></a>02348 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERR25:1;
|
||
<a name="l02349"></a>02349 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERR24:1;
|
||
<a name="l02350"></a>02350 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERR23:1;
|
||
<a name="l02351"></a>02351 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERR22:1;
|
||
<a name="l02352"></a>02352 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERR21:1;
|
||
<a name="l02353"></a>02353 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERR20:1;
|
||
<a name="l02354"></a>02354 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERR19:1;
|
||
<a name="l02355"></a>02355 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERR18:1;
|
||
<a name="l02356"></a>02356 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERR17:1;
|
||
<a name="l02357"></a>02357 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERR16:1;
|
||
<a name="l02358"></a>02358 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERR15:1;
|
||
<a name="l02359"></a>02359 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERR14:1;
|
||
<a name="l02360"></a>02360 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERR13:1;
|
||
<a name="l02361"></a>02361 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERR12:1;
|
||
<a name="l02362"></a>02362 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERR11:1;
|
||
<a name="l02363"></a>02363 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERR10:1;
|
||
<a name="l02364"></a>02364 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERR09:1;
|
||
<a name="l02365"></a>02365 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERR08:1;
|
||
<a name="l02366"></a>02366 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERR07:1;
|
||
<a name="l02367"></a>02367 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERR06:1;
|
||
<a name="l02368"></a>02368 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERR05:1;
|
||
<a name="l02369"></a>02369 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERR04:1;
|
||
<a name="l02370"></a>02370 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERR03:1;
|
||
<a name="l02371"></a>02371 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERR02:1;
|
||
<a name="l02372"></a>02372 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERR01:1;
|
||
<a name="l02373"></a>02373 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERR00:1;
|
||
<a name="l02374"></a>02374 } B;
|
||
<a name="l02375"></a>02375 } ERL; <span class="comment">/* <URM>DMAERRL</URM> , DMA Error Low */</span>
|
||
<a name="l02376"></a>02376
|
||
<a name="l02377"></a>02377 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> edma_reserverd_hrsh[1];
|
||
<a name="l02378"></a>02378
|
||
<a name="l02379"></a>02379 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> edma_reserverd_hrsl[1];
|
||
<a name="l02380"></a>02380
|
||
<a name="l02381"></a>02381 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> edma_reserverd_gpor[1];
|
||
<a name="l02382"></a>02382
|
||
<a name="l02383"></a>02383 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> EDMA_reserverd_223[49];
|
||
<a name="l02384"></a>02384
|
||
<a name="l02385"></a>02385 <span class="keyword">union </span>{
|
||
<a name="l02386"></a>02386 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> R;
|
||
<a name="l02387"></a>02387 <span class="keyword">struct </span>{
|
||
<a name="l02388"></a>02388 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> ECP:1;
|
||
<a name="l02389"></a>02389 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> DPA:1;
|
||
<a name="l02390"></a>02390 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> GRPPRI:2;
|
||
<a name="l02391"></a>02391 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> CHPRI:4;
|
||
<a name="l02392"></a>02392 } B;
|
||
<a name="l02393"></a>02393 } CPR[64]; <span class="comment">/* <URM>DCHPRI [32]</URM> , Channel n Priority */</span>
|
||
<a name="l02394"></a>02394
|
||
<a name="l02395"></a>02395 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> edma_reserved2[944];
|
||
<a name="l02396"></a>02396
|
||
<a name="l02397"></a>02397 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l02398"></a>02398 <span class="comment">/* DMA2 Transfer Control Descriptor */</span>
|
||
<a name="l02399"></a>02399 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l02400"></a>02400
|
||
<a name="l02401"></a>02401 <span class="keyword">struct </span>tcd_t { <span class="comment">/*for "standard" format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=0 && EDMA.EMLM=0 ) */</span>
|
||
<a name="l02402"></a>02402 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SADDR; <span class="comment">/* source address */</span>
|
||
<a name="l02403"></a>02403
|
||
<a name="l02404"></a>02404 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> SMOD:5; <span class="comment">/* source address modulo */</span>
|
||
<a name="l02405"></a>02405 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> SSIZE:3; <span class="comment">/* source transfer size */</span>
|
||
<a name="l02406"></a>02406 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> DMOD:5; <span class="comment">/* destination address modulo */</span>
|
||
<a name="l02407"></a>02407 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> DSIZE:3; <span class="comment">/* destination transfer size */</span>
|
||
<a name="l02408"></a>02408 <a class="code" href="group___p_p_c___c_o_r_e.html#ga9f6dcc179d3c49158006865ab81f84f5">vint16_t</a> SOFF; <span class="comment">/* signed source address offset */</span>
|
||
<a name="l02409"></a>02409 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> NBYTES; <span class="comment">/* inner (<28>minor<6F>) byte count */</span>
|
||
<a name="l02410"></a>02410 <a class="code" href="group___p_p_c___c_o_r_e.html#ga6f217e412133ffa5803e5d91d0043976">vint32_t</a> SLAST; <span class="comment">/* last destination address adjustment, or</span>
|
||
<a name="l02411"></a>02411 <span class="comment"></span>
|
||
<a name="l02412"></a>02412 <span class="comment"> scatter/gather address (if e_sg = 1) */</span>
|
||
<a name="l02413"></a>02413 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DADDR; <span class="comment">/* destination address */</span>
|
||
<a name="l02414"></a>02414 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> CITERE_LINK:1;
|
||
<a name="l02415"></a>02415 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> CITER:15;
|
||
<a name="l02416"></a>02416 <a class="code" href="group___p_p_c___c_o_r_e.html#ga9f6dcc179d3c49158006865ab81f84f5">vint16_t</a> DOFF; <span class="comment">/* signed destination address offset */</span>
|
||
<a name="l02417"></a>02417 <a class="code" href="group___p_p_c___c_o_r_e.html#ga6f217e412133ffa5803e5d91d0043976">vint32_t</a> DLAST_SGA;
|
||
<a name="l02418"></a>02418 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> BITERE_LINK:1; <span class="comment">/* beginning ("major") iteration count */</span>
|
||
<a name="l02419"></a>02419 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> BITER:15;
|
||
<a name="l02420"></a>02420 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> BWC:2; <span class="comment">/* bandwidth control */</span>
|
||
<a name="l02421"></a>02421 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> MAJORLINKCH:6; <span class="comment">/* enable channel-to-channel link */</span>
|
||
<a name="l02422"></a>02422 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> DONE:1; <span class="comment">/* channel done */</span>
|
||
<a name="l02423"></a>02423 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> ACTIVE:1; <span class="comment">/* channel active */</span>
|
||
<a name="l02424"></a>02424 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> MAJORE_LINK:1; <span class="comment">/* enable channel-to-channel link */</span>
|
||
<a name="l02425"></a>02425 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> E_SG:1; <span class="comment">/* enable scatter/gather descriptor */</span>
|
||
<a name="l02426"></a>02426 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> D_REQ:1; <span class="comment">/* disable ipd_req when done */</span>
|
||
<a name="l02427"></a>02427 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> INT_HALF:1; <span class="comment">/* interrupt on citer = (biter >> 1) */</span>
|
||
<a name="l02428"></a>02428 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> INT_MAJ:1; <span class="comment">/* interrupt on major loop completion */</span>
|
||
<a name="l02429"></a>02429 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> START:1; <span class="comment">/* explicit channel start */</span>
|
||
<a name="l02430"></a>02430 } TCD[64]; <span class="comment">/* <URM>TCD [32]</URM> , transfer_control_descriptor */</span>
|
||
<a name="l02431"></a>02431 };
|
||
<a name="l02432"></a>02432
|
||
<a name="l02433"></a>02433 <span class="keyword">struct </span>EDMA_TCD_alt1_tag { <span class="comment">/*for alternate format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=1 ) */</span>
|
||
<a name="l02434"></a>02434
|
||
<a name="l02435"></a>02435 <span class="keyword">struct </span>tcd_alt1_t {
|
||
<a name="l02436"></a>02436 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SADDR; <span class="comment">/* source address */</span>
|
||
<a name="l02437"></a>02437
|
||
<a name="l02438"></a>02438 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> SMOD:5; <span class="comment">/* source address modulo */</span>
|
||
<a name="l02439"></a>02439 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> SSIZE:3; <span class="comment">/* source transfer size */</span>
|
||
<a name="l02440"></a>02440 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> DMOD:5; <span class="comment">/* destination address modulo */</span>
|
||
<a name="l02441"></a>02441 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> DSIZE:3; <span class="comment">/* destination transfer size */</span>
|
||
<a name="l02442"></a>02442 <a class="code" href="group___p_p_c___c_o_r_e.html#ga9f6dcc179d3c49158006865ab81f84f5">vint16_t</a> SOFF; <span class="comment">/* signed source address offset */</span>
|
||
<a name="l02443"></a>02443 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> NBYTES; <span class="comment">/* inner (<28>minor<6F>) byte count */</span>
|
||
<a name="l02444"></a>02444 <a class="code" href="group___p_p_c___c_o_r_e.html#ga6f217e412133ffa5803e5d91d0043976">vint32_t</a> SLAST; <span class="comment">/* last destination address adjustment, or</span>
|
||
<a name="l02445"></a>02445 <span class="comment"></span>
|
||
<a name="l02446"></a>02446 <span class="comment"> scatter/gather address (if e_sg = 1) */</span>
|
||
<a name="l02447"></a>02447 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DADDR; <span class="comment">/* destination address */</span>
|
||
<a name="l02448"></a>02448 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> CITERE_LINK:1;
|
||
<a name="l02449"></a>02449 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> CITERLINKCH:6;
|
||
<a name="l02450"></a>02450 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> CITER:9;
|
||
<a name="l02451"></a>02451 <a class="code" href="group___p_p_c___c_o_r_e.html#ga9f6dcc179d3c49158006865ab81f84f5">vint16_t</a> DOFF; <span class="comment">/* signed destination address offset */</span>
|
||
<a name="l02452"></a>02452 <a class="code" href="group___p_p_c___c_o_r_e.html#ga6f217e412133ffa5803e5d91d0043976">vint32_t</a> DLAST_SGA;
|
||
<a name="l02453"></a>02453 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> BITERE_LINK:1; <span class="comment">/* beginning (<28>major<6F>) iteration count */</span>
|
||
<a name="l02454"></a>02454 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> BITERLINKCH:6;
|
||
<a name="l02455"></a>02455 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> BITER:9;
|
||
<a name="l02456"></a>02456 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> BWC:2; <span class="comment">/* bandwidth control */</span>
|
||
<a name="l02457"></a>02457 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> MAJORLINKCH:6; <span class="comment">/* enable channel-to-channel link */</span>
|
||
<a name="l02458"></a>02458 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> DONE:1; <span class="comment">/* channel done */</span>
|
||
<a name="l02459"></a>02459 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> ACTIVE:1; <span class="comment">/* channel active */</span>
|
||
<a name="l02460"></a>02460 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> MAJORE_LINK:1; <span class="comment">/* enable channel-to-channel link */</span>
|
||
<a name="l02461"></a>02461 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> E_SG:1; <span class="comment">/* enable scatter/gather descriptor */</span>
|
||
<a name="l02462"></a>02462 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> D_REQ:1; <span class="comment">/* disable ipd_req when done */</span>
|
||
<a name="l02463"></a>02463 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> INT_HALF:1; <span class="comment">/* interrupt on citer = (biter >> 1) */</span>
|
||
<a name="l02464"></a>02464 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> INT_MAJ:1; <span class="comment">/* interrupt on major loop completion */</span>
|
||
<a name="l02465"></a>02465 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> START:1; <span class="comment">/* explicit channel start */</span>
|
||
<a name="l02466"></a>02466 } TCD[64]; <span class="comment">/* <URM>TCD [32]</URM> , transfer_control_descriptor */</span>
|
||
<a name="l02467"></a>02467 };
|
||
<a name="l02468"></a>02468
|
||
<a name="l02469"></a>02469 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l02470"></a>02470 <span class="comment">/* MODULE : INTC */</span>
|
||
<a name="l02471"></a>02471 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l02472"></a>02472 <span class="keyword">struct </span>INTC_tag {
|
||
<a name="l02473"></a>02473 <span class="keyword">union </span>{
|
||
<a name="l02474"></a>02474 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02475"></a>02475 <span class="keyword">struct </span>{
|
||
<a name="l02476"></a>02476 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:18; <span class="comment">/* Reserved */</span>
|
||
<a name="l02477"></a>02477 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> VTES_PRC1:1; <span class="comment">/* Vector Table Entry Size for PRC1 (new in MPC563xM) */</span>
|
||
<a name="l02478"></a>02478 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:4; <span class="comment">/* Reserved */</span>
|
||
<a name="l02479"></a>02479 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> HVEN_PRC1:1; <span class="comment">/* Hardware Vector Enable for PRC1 (new in MPC563xM) */</span>
|
||
<a name="l02480"></a>02480 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:2; <span class="comment">/* Reserved */</span>
|
||
<a name="l02481"></a>02481 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> VTES:1; <span class="comment">/* Vector Table Entry Size for PRC0 <URM>VTES_PRC0</URM> */</span>
|
||
<a name="l02482"></a>02482 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:4; <span class="comment">/* Reserved */</span>
|
||
<a name="l02483"></a>02483 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> HVEN:1; <span class="comment">/* Hardware Vector Enable for PRC0 <URM>HVEN_PRC0</URM> */</span>
|
||
<a name="l02484"></a>02484 } B;
|
||
<a name="l02485"></a>02485 } MCR; <span class="comment">/* INTC Module Configuration Register (MCR) <URM>INTC_BCR</URM> @baseaddress + 0x00 */</span>
|
||
<a name="l02486"></a>02486 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> INTC_reserverd_10[1];
|
||
<a name="l02487"></a>02487
|
||
<a name="l02488"></a>02488 <span class="keyword">union </span>{
|
||
<a name="l02489"></a>02489 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02490"></a>02490 <span class="keyword">struct </span>{
|
||
<a name="l02491"></a>02491 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:28; <span class="comment">/* Reserved */</span>
|
||
<a name="l02492"></a>02492 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PRI:4; <span class="comment">/* Priority */</span>
|
||
<a name="l02493"></a>02493 } B;
|
||
<a name="l02494"></a>02494 } CPR; <span class="comment">/* INTC Current Priority Register for Processor 0 (CPR) <URM>INTC_CPR_PRC0</URM> @baseaddress + 0x08 */</span>
|
||
<a name="l02495"></a>02495
|
||
<a name="l02496"></a>02496 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> INTC_reserved_1; <span class="comment">/* CPR_PRC1 - INTC Current Priority Register for Processor 1 (CPR_PRC1) <URM>INTC_CPR_PRC1</URM> @baseaddress + 0x0c */</span>
|
||
<a name="l02497"></a>02497
|
||
<a name="l02498"></a>02498 <span class="keyword">union </span>{
|
||
<a name="l02499"></a>02499 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02500"></a>02500 <span class="keyword">struct </span>{
|
||
<a name="l02501"></a>02501 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> VTBA:21; <span class="comment">/* Vector Table Base Address <URM>VTBA_PRC0</URM> */</span>
|
||
<a name="l02502"></a>02502 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> INTVEC:9; <span class="comment">/* Interrupt Vector <URM>INTVEC_PRC0</URM> */</span>
|
||
<a name="l02503"></a>02503 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:2; <span class="comment">/* Reserved */</span>
|
||
<a name="l02504"></a>02504 } B;
|
||
<a name="l02505"></a>02505 } IACKR; <span class="comment">/* INTC Interrupt Acknowledge Register for Processor 0 (IACKR) <URM>INTC_IACKR_PRC0</URM> @baseaddress + 0x10 */</span>
|
||
<a name="l02506"></a>02506
|
||
<a name="l02507"></a>02507 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> INTC_reserverd_2; <span class="comment">/* IACKR_PRC1 - INTC Interrupt Acknowledge Register for Processor 1 (IACKR_PRC1) <URM>INTC_IACKR_PRC1</URM> @baseaddress + 0x14 */</span>
|
||
<a name="l02508"></a>02508
|
||
<a name="l02509"></a>02509 <span class="keyword">union </span>{
|
||
<a name="l02510"></a>02510 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02511"></a>02511 } EOIR; <span class="comment">/* INTC End of Interrupt Register for Processor 0 (EOIR) <URM>INTC_EOIR_PRC0</URM> @baseaddress + 0x18 */</span>
|
||
<a name="l02512"></a>02512
|
||
<a name="l02513"></a>02513 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> INTC_reserverd_3; <span class="comment">/* EOIR_PRC1 - INTC End of Interrupt Register for Processor 1 (EOIR_PRC1) <URM>INTC_EOIR_PRC1</URM> @baseaddress + 0x1C */</span>
|
||
<a name="l02514"></a>02514
|
||
<a name="l02515"></a>02515 <span class="keyword">union </span>{
|
||
<a name="l02516"></a>02516 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> R;
|
||
<a name="l02517"></a>02517 <span class="keyword">struct </span>{
|
||
<a name="l02518"></a>02518 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a>:6; <span class="comment">/* Reserved */</span>
|
||
<a name="l02519"></a>02519 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> SET:1; <span class="comment">/* Set Flag bits */</span>
|
||
<a name="l02520"></a>02520 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> CLR:1; <span class="comment">/* Clear Flag bits */</span>
|
||
<a name="l02521"></a>02521 } B;
|
||
<a name="l02522"></a>02522 } SSCIR[8]; <span class="comment">/* INTC Software Set/Clear Interrupt Registers (SSCIR) <URM>INTC_SSCIRn</URM> @baseaddress + 0x20 */</span>
|
||
<a name="l02523"></a>02523
|
||
<a name="l02524"></a>02524 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> INTC_reserverd_32[6];
|
||
<a name="l02525"></a>02525
|
||
<a name="l02526"></a>02526 <span class="keyword">union </span>{
|
||
<a name="l02527"></a>02527 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> R;
|
||
<a name="l02528"></a>02528 <span class="keyword">struct </span>{
|
||
<a name="l02529"></a>02529 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> PRC_SEL:2; <span class="comment">/* Processor Select (new in MPC563xM) */</span>
|
||
<a name="l02530"></a>02530 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a>:2; <span class="comment">/* Reserved */</span>
|
||
<a name="l02531"></a>02531 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> PRI:4; <span class="comment">/* Priority Select */</span>
|
||
<a name="l02532"></a>02532 } B;
|
||
<a name="l02533"></a>02533 } PSR[512]; <span class="comment">/* INTC Priority Select Registers (PSR) <URM>INTC_PSR</URM> @baseaddress + 0x40 */</span>
|
||
<a name="l02534"></a>02534
|
||
<a name="l02535"></a>02535 }; <span class="comment">/* end of INTC_tag */</span>
|
||
<a name="l02536"></a>02536 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l02537"></a>02537 <span class="comment">/* MODULE : EQADC */</span>
|
||
<a name="l02538"></a>02538 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l02539"></a>02539 <span class="keyword">struct </span>EQADC_tag {
|
||
<a name="l02540"></a>02540 <span class="keyword">union </span>{
|
||
<a name="l02541"></a>02541 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02542"></a>02542 <span class="keyword">struct </span>{
|
||
<a name="l02543"></a>02543 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:24;
|
||
<a name="l02544"></a>02544 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ICEA0:1;
|
||
<a name="l02545"></a>02545 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ICEA1:1;
|
||
<a name="l02546"></a>02546 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1;
|
||
<a name="l02547"></a>02547 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ESSIE:2;
|
||
<a name="l02548"></a>02548 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1;
|
||
<a name="l02549"></a>02549 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DBG:2;
|
||
<a name="l02550"></a>02550 } B;
|
||
<a name="l02551"></a>02551 } MCR; <span class="comment">/* Module Configuration Register <URM>EQADC_MCR</URM> */</span>
|
||
<a name="l02552"></a>02552
|
||
<a name="l02553"></a>02553 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> EQADC_reserved00;
|
||
<a name="l02554"></a>02554
|
||
<a name="l02555"></a>02555 <span class="keyword">union </span>{
|
||
<a name="l02556"></a>02556 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02557"></a>02557 <span class="keyword">struct </span>{
|
||
<a name="l02558"></a>02558 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:6;
|
||
<a name="l02559"></a>02559 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> NMF:26;
|
||
<a name="l02560"></a>02560 } B;
|
||
<a name="l02561"></a>02561 } NMSFR; <span class="comment">/* Null Message Send Format Register <URM>EQADC_NMSFR</URM> */</span>
|
||
<a name="l02562"></a>02562
|
||
<a name="l02563"></a>02563 <span class="keyword">union </span>{
|
||
<a name="l02564"></a>02564 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02565"></a>02565 <span class="keyword">struct </span>{
|
||
<a name="l02566"></a>02566 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:28;
|
||
<a name="l02567"></a>02567 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DFL:4;
|
||
<a name="l02568"></a>02568 } B;
|
||
<a name="l02569"></a>02569 } ETDFR; <span class="comment">/* External Trigger Digital Filter Register <URM>EQADC_ETDFR</URM> */</span>
|
||
<a name="l02570"></a>02570
|
||
<a name="l02571"></a>02571 <span class="keyword">union </span>{
|
||
<a name="l02572"></a>02572 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02573"></a>02573 <span class="keyword">struct </span>{
|
||
<a name="l02574"></a>02574 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CFPUSH:32; <span class="comment">/* <URM>CF_PUSH</URM> */</span>
|
||
<a name="l02575"></a>02575 } B;
|
||
<a name="l02576"></a>02576 } CFPR[6]; <span class="comment">/* CFIFO Push Registers <URM>EQADC_CFPR</URM> */</span>
|
||
<a name="l02577"></a>02577
|
||
<a name="l02578"></a>02578 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> eqadc_reserved1;
|
||
<a name="l02579"></a>02579
|
||
<a name="l02580"></a>02580 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> eqadc_reserved2;
|
||
<a name="l02581"></a>02581
|
||
<a name="l02582"></a>02582 <span class="keyword">union </span>{
|
||
<a name="l02583"></a>02583 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02584"></a>02584 <span class="keyword">struct </span>{
|
||
<a name="l02585"></a>02585 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:16;
|
||
<a name="l02586"></a>02586 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RFPOP:16; <span class="comment">/* <URM>RF_POP</URM> */</span>
|
||
<a name="l02587"></a>02587 } B;
|
||
<a name="l02588"></a>02588 } RFPR[6]; <span class="comment">/* Result FIFO Pop Registers <URM>EQADC_RFPR</URM> */</span>
|
||
<a name="l02589"></a>02589
|
||
<a name="l02590"></a>02590 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> eqadc_reserved3;
|
||
<a name="l02591"></a>02591
|
||
<a name="l02592"></a>02592 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> eqadc_reserved4;
|
||
<a name="l02593"></a>02593
|
||
<a name="l02594"></a>02594 <span class="keyword">union </span>{
|
||
<a name="l02595"></a>02595 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> R;
|
||
<a name="l02596"></a>02596 <span class="keyword">struct </span>{
|
||
<a name="l02597"></a>02597 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a>:3;
|
||
<a name="l02598"></a>02598 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> CFEE0:1;
|
||
<a name="l02599"></a>02599 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> STRME0:1;
|
||
<a name="l02600"></a>02600 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> SSE:1;
|
||
<a name="l02601"></a>02601 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> CFINV:1;
|
||
<a name="l02602"></a>02602 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a>:1;
|
||
<a name="l02603"></a>02603 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> MODE:4;
|
||
<a name="l02604"></a>02604 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> AMODE0:4; <span class="comment">/* CFIFO0 only */</span>
|
||
<a name="l02605"></a>02605 } B;
|
||
<a name="l02606"></a>02606 } CFCR[6]; <span class="comment">/* CFIFO Control Registers <URM>EQADC_CFCR</URM> */</span>
|
||
<a name="l02607"></a>02607
|
||
<a name="l02608"></a>02608 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> eqadc_reserved5;
|
||
<a name="l02609"></a>02609
|
||
<a name="l02610"></a>02610 <span class="keyword">union </span>{
|
||
<a name="l02611"></a>02611 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> R;
|
||
<a name="l02612"></a>02612 <span class="keyword">struct </span>{
|
||
<a name="l02613"></a>02613 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> NCIE:1;
|
||
<a name="l02614"></a>02614 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> TORIE:1;
|
||
<a name="l02615"></a>02615 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> PIE:1;
|
||
<a name="l02616"></a>02616 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> EOQIE:1;
|
||
<a name="l02617"></a>02617 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> CFUIE:1;
|
||
<a name="l02618"></a>02618 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a>:1;
|
||
<a name="l02619"></a>02619 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> CFFE:1;
|
||
<a name="l02620"></a>02620 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> CFFS:1;
|
||
<a name="l02621"></a>02621 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a>:4;
|
||
<a name="l02622"></a>02622 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> RFOIE:1;
|
||
<a name="l02623"></a>02623 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a>:1;
|
||
<a name="l02624"></a>02624 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> RFDE:1;
|
||
<a name="l02625"></a>02625 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> RFDS:1;
|
||
<a name="l02626"></a>02626 } B;
|
||
<a name="l02627"></a>02627 } IDCR[6]; <span class="comment">/* Interrupt and DMA Control Registers <URM>EQADC_IDCR</URM> */</span>
|
||
<a name="l02628"></a>02628
|
||
<a name="l02629"></a>02629 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> eqadc_reserved6;
|
||
<a name="l02630"></a>02630
|
||
<a name="l02631"></a>02631 <span class="keyword">union </span>{
|
||
<a name="l02632"></a>02632 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02633"></a>02633 <span class="keyword">struct </span>{
|
||
<a name="l02634"></a>02634 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> NCF:1;
|
||
<a name="l02635"></a>02635 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TORF:1;
|
||
<a name="l02636"></a>02636 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PF:1;
|
||
<a name="l02637"></a>02637 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EOQF:1;
|
||
<a name="l02638"></a>02638 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CFUF:1;
|
||
<a name="l02639"></a>02639 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SSS:1;
|
||
<a name="l02640"></a>02640 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CFFF:1;
|
||
<a name="l02641"></a>02641 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:5;
|
||
<a name="l02642"></a>02642 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RFOF:1;
|
||
<a name="l02643"></a>02643 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1;
|
||
<a name="l02644"></a>02644 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RFDF:1;
|
||
<a name="l02645"></a>02645 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1;
|
||
<a name="l02646"></a>02646 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CFCTR:4;
|
||
<a name="l02647"></a>02647 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TNXTPTR:4;
|
||
<a name="l02648"></a>02648 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RFCTR:4;
|
||
<a name="l02649"></a>02649 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> POPNXTPTR:4;
|
||
<a name="l02650"></a>02650 } B;
|
||
<a name="l02651"></a>02651 } FISR[6]; <span class="comment">/* FIFO and Interrupt Status Registers <URM>EQADC_FISR</URM> */</span>
|
||
<a name="l02652"></a>02652
|
||
<a name="l02653"></a>02653 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> eqadc_reserved7;
|
||
<a name="l02654"></a>02654
|
||
<a name="l02655"></a>02655 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> eqadc_reserved8;
|
||
<a name="l02656"></a>02656
|
||
<a name="l02657"></a>02657 <span class="keyword">union </span>{
|
||
<a name="l02658"></a>02658 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> R;
|
||
<a name="l02659"></a>02659 <span class="keyword">struct </span>{
|
||
<a name="l02660"></a>02660 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a>:5;
|
||
<a name="l02661"></a>02661 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> TCCF:11; <span class="comment">/* <URM>TC_CF</URM> */</span>
|
||
<a name="l02662"></a>02662 } B;
|
||
<a name="l02663"></a>02663 } CFTCR[6]; <span class="comment">/* CFIFO Transfer Counter Registers <URM>EQADC_CFTCR</URM> */</span>
|
||
<a name="l02664"></a>02664
|
||
<a name="l02665"></a>02665 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> eqadc_reserved9;
|
||
<a name="l02666"></a>02666
|
||
<a name="l02667"></a>02667 <span class="keyword">union </span>{
|
||
<a name="l02668"></a>02668 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02669"></a>02669 <span class="keyword">struct </span>{
|
||
<a name="l02670"></a>02670 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CFS0:2; <span class="comment">/* <URM>CFS0_TCB0</URM> */</span>
|
||
<a name="l02671"></a>02671 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CFS1:2; <span class="comment">/* <URM>CFS1_TCB0</URM> */</span>
|
||
<a name="l02672"></a>02672 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CFS2:2; <span class="comment">/* <URM>CFS2_TCB0</URM> */</span>
|
||
<a name="l02673"></a>02673 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CFS3:2; <span class="comment">/* <URM>CFS3_TCB0</URM> */</span>
|
||
<a name="l02674"></a>02674 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CFS4:2; <span class="comment">/* <URM>CFS4_TCB0</URM> */</span>
|
||
<a name="l02675"></a>02675 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CFS5:2; <span class="comment">/* <URM>CFS5_TCB0</URM> */</span>
|
||
<a name="l02676"></a>02676 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:5;
|
||
<a name="l02677"></a>02677 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LCFTCB0:4;
|
||
<a name="l02678"></a>02678 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TC_LCFTCB0:11;
|
||
<a name="l02679"></a>02679 } B;
|
||
<a name="l02680"></a>02680 } CFSSR0; <span class="comment">/* CFIFO Status Register 0 <URM>EQADC_CFSSR0</URM> */</span>
|
||
<a name="l02681"></a>02681
|
||
<a name="l02682"></a>02682 <span class="keyword">union </span>{
|
||
<a name="l02683"></a>02683 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02684"></a>02684 <span class="keyword">struct </span>{
|
||
<a name="l02685"></a>02685 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CFS0:2; <span class="comment">/* <URM>CFS0_TCB1</URM> */</span>
|
||
<a name="l02686"></a>02686 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CFS1:2; <span class="comment">/* <URM>CFS1_TCB1</URM> */</span>
|
||
<a name="l02687"></a>02687 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CFS2:2; <span class="comment">/* <URM>CFS2_TCB1</URM> */</span>
|
||
<a name="l02688"></a>02688 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CFS3:2; <span class="comment">/* <URM>CFS3_TCB1</URM> */</span>
|
||
<a name="l02689"></a>02689 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CFS4:2; <span class="comment">/* <URM>CFS4_TCB1</URM> */</span>
|
||
<a name="l02690"></a>02690 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CFS5:2; <span class="comment">/* <URM>CFS5_TCB1</URM> */</span>
|
||
<a name="l02691"></a>02691 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:5;
|
||
<a name="l02692"></a>02692 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LCFTCB1:4;
|
||
<a name="l02693"></a>02693 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TC_LCFTCB1:11;
|
||
<a name="l02694"></a>02694 } B;
|
||
<a name="l02695"></a>02695 } CFSSR1; <span class="comment">/* CFIFO Status Register 1 <URM>EQADC_CFSSR1</URM> */</span>
|
||
<a name="l02696"></a>02696
|
||
<a name="l02697"></a>02697 <span class="keyword">union </span>{
|
||
<a name="l02698"></a>02698 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02699"></a>02699 <span class="keyword">struct </span>{
|
||
<a name="l02700"></a>02700 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CFS0:2; <span class="comment">/* <URM>CFS0_TSSI</URM> */</span>
|
||
<a name="l02701"></a>02701 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CFS1:2; <span class="comment">/* <URM>CFS1_TSSI</URM> */</span>
|
||
<a name="l02702"></a>02702 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CFS2:2; <span class="comment">/* <URM>CFS2_TSSI</URM> */</span>
|
||
<a name="l02703"></a>02703 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CFS3:2; <span class="comment">/* <URM>CFS3_TSSI</URM> */</span>
|
||
<a name="l02704"></a>02704 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CFS4:2; <span class="comment">/* <URM>CFS4_TSSI</URM> */</span>
|
||
<a name="l02705"></a>02705 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CFS5:2; <span class="comment">/* <URM>CFS5_TSSI</URM> */</span>
|
||
<a name="l02706"></a>02706 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:4;
|
||
<a name="l02707"></a>02707 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ECBNI:1;
|
||
<a name="l02708"></a>02708 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LCFTSSI:4;
|
||
<a name="l02709"></a>02709 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TC_LCFTSSI:11;
|
||
<a name="l02710"></a>02710 } B;
|
||
<a name="l02711"></a>02711 } CFSSR2; <span class="comment">/* CFIFO Status Register 2 <URM>EQADC_CFSSR2</URM> */</span>
|
||
<a name="l02712"></a>02712
|
||
<a name="l02713"></a>02713 <span class="keyword">union </span>{
|
||
<a name="l02714"></a>02714 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02715"></a>02715 <span class="keyword">struct </span>{
|
||
<a name="l02716"></a>02716 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CFS0:2;
|
||
<a name="l02717"></a>02717 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CFS1:2;
|
||
<a name="l02718"></a>02718 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CFS2:2;
|
||
<a name="l02719"></a>02719 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CFS3:2;
|
||
<a name="l02720"></a>02720 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CFS4:2;
|
||
<a name="l02721"></a>02721 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CFS5:2;
|
||
<a name="l02722"></a>02722 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:20;
|
||
<a name="l02723"></a>02723 } B;
|
||
<a name="l02724"></a>02724 } CFSR; <span class="comment">/* <URM>EQADC_CFSR</URM> */</span>
|
||
<a name="l02725"></a>02725
|
||
<a name="l02726"></a>02726 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> eqadc_reserved11;
|
||
<a name="l02727"></a>02727
|
||
<a name="l02728"></a>02728 <span class="keyword">union </span>{
|
||
<a name="l02729"></a>02729 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02730"></a>02730 <span class="keyword">struct </span>{
|
||
<a name="l02731"></a>02731 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:21;
|
||
<a name="l02732"></a>02732 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MDT:3;
|
||
<a name="l02733"></a>02733 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:4;
|
||
<a name="l02734"></a>02734 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BR:4;
|
||
<a name="l02735"></a>02735 } B;
|
||
<a name="l02736"></a>02736 } SSICR; <span class="comment">/* SSI Control Register <URM>EQADC_SSICR</URM> */</span>
|
||
<a name="l02737"></a>02737
|
||
<a name="l02738"></a>02738 <span class="keyword">union </span>{
|
||
<a name="l02739"></a>02739 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02740"></a>02740 <span class="keyword">struct </span>{
|
||
<a name="l02741"></a>02741 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RDV:1;
|
||
<a name="l02742"></a>02742 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:5;
|
||
<a name="l02743"></a>02743 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RDATA:26;
|
||
<a name="l02744"></a>02744 } B;
|
||
<a name="l02745"></a>02745 } SSIRDR; <span class="comment">/* SSI Recieve Data Register <URM>EQADC_SSIRDR</URM> @ baseaddress + 0xB8 */</span>
|
||
<a name="l02746"></a>02746
|
||
<a name="l02747"></a>02747 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> eqadc_reserved11b[5];
|
||
<a name="l02748"></a>02748
|
||
<a name="l02749"></a>02749 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> eqadc_reserved15; <span class="comment">/* EQADC Red Line Client Configuration Register @ baseaddress + 0xD0 */</span>
|
||
<a name="l02750"></a>02750 <span class="comment">/* REDLCCR is not implemented in the MPC563xM */</span>
|
||
<a name="l02751"></a>02751
|
||
<a name="l02752"></a>02752 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> eqadc_reserved12[11];
|
||
<a name="l02753"></a>02753
|
||
<a name="l02754"></a>02754 <span class="keyword">struct </span>{
|
||
<a name="l02755"></a>02755 <span class="keyword">union </span>{
|
||
<a name="l02756"></a>02756 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02757"></a>02757
|
||
<a name="l02758"></a>02758 <span class="comment">/*<URM>B.CFIFOx_DATAw</URM> */</span>
|
||
<a name="l02759"></a>02759
|
||
<a name="l02760"></a>02760 } R[4]; <span class="comment">/*<URM>EQADC_CFxRw<URM> */</span>
|
||
<a name="l02761"></a>02761
|
||
<a name="l02762"></a>02762 <span class="keyword">union </span>{
|
||
<a name="l02763"></a>02763 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02764"></a>02764 <span class="comment">/*<URM>B.CFIFOx_EDATAw</URM> */</span>
|
||
<a name="l02765"></a>02765 } EDATA[4]; <span class="comment">/*<URM>EQADC_CFxERw</URM> (new in MPC563xM) */</span>
|
||
<a name="l02766"></a>02766
|
||
<a name="l02767"></a>02767 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> eqadc_reserved13[8];
|
||
<a name="l02768"></a>02768
|
||
<a name="l02769"></a>02769 } CF[6];
|
||
<a name="l02770"></a>02770
|
||
<a name="l02771"></a>02771 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> eqadc_reserved14[32];
|
||
<a name="l02772"></a>02772
|
||
<a name="l02773"></a>02773 <span class="keyword">struct </span>{
|
||
<a name="l02774"></a>02774 <span class="keyword">union </span>{
|
||
<a name="l02775"></a>02775 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02776"></a>02776 <span class="comment">/*<URM>RFIFOx_DATAw</URM> */</span>
|
||
<a name="l02777"></a>02777 } R[4]; <span class="comment">/*<URM>EQADC_RFxRw</URM> */</span>
|
||
<a name="l02778"></a>02778
|
||
<a name="l02779"></a>02779 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> eqadc_reserved15[12];
|
||
<a name="l02780"></a>02780
|
||
<a name="l02781"></a>02781 } RF[6];
|
||
<a name="l02782"></a>02782
|
||
<a name="l02783"></a>02783 };
|
||
<a name="l02784"></a>02784 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l02785"></a>02785 <span class="comment">/* MODULE : DSPI */</span>
|
||
<a name="l02786"></a>02786 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l02787"></a>02787 <span class="keyword">struct </span>DSPI_tag {
|
||
<a name="l02788"></a>02788 <span class="keyword">union </span>{
|
||
<a name="l02789"></a>02789 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02790"></a>02790 <span class="keyword">struct </span>{
|
||
<a name="l02791"></a>02791 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MSTR:1;
|
||
<a name="l02792"></a>02792 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CONT_SCKE:1;
|
||
<a name="l02793"></a>02793 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DCONF:2;
|
||
<a name="l02794"></a>02794 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> FRZ:1;
|
||
<a name="l02795"></a>02795 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MTFE:1;
|
||
<a name="l02796"></a>02796 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PCSSE:1;
|
||
<a name="l02797"></a>02797 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ROOE:1;
|
||
<a name="l02798"></a>02798 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PCSIS7:1; <span class="comment">/* new in MPC563xM */</span>
|
||
<a name="l02799"></a>02799 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PCSIS6:1; <span class="comment">/* new in MPC563xM */</span>
|
||
<a name="l02800"></a>02800 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PCSIS5:1;
|
||
<a name="l02801"></a>02801 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PCSIS4:1;
|
||
<a name="l02802"></a>02802 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PCSIS3:1;
|
||
<a name="l02803"></a>02803 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PCSIS2:1;
|
||
<a name="l02804"></a>02804 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PCSIS1:1;
|
||
<a name="l02805"></a>02805 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PCSIS0:1;
|
||
<a name="l02806"></a>02806 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DOZE:1;
|
||
<a name="l02807"></a>02807 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MDIS:1;
|
||
<a name="l02808"></a>02808 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DIS_TXF:1;
|
||
<a name="l02809"></a>02809 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DIS_RXF:1;
|
||
<a name="l02810"></a>02810 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CLR_TXF:1;
|
||
<a name="l02811"></a>02811 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CLR_RXF:1;
|
||
<a name="l02812"></a>02812 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SMPL_PT:2;
|
||
<a name="l02813"></a>02813 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:7;
|
||
<a name="l02814"></a>02814 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> HALT:1;
|
||
<a name="l02815"></a>02815 } B;
|
||
<a name="l02816"></a>02816 } MCR; <span class="comment">/* Module Configuration Register <URM>DSPI_MCR</URM> @baseaddress + 0x00 */</span>
|
||
<a name="l02817"></a>02817
|
||
<a name="l02818"></a>02818 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> dspi_reserved1;
|
||
<a name="l02819"></a>02819
|
||
<a name="l02820"></a>02820 <span class="keyword">union </span>{
|
||
<a name="l02821"></a>02821 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02822"></a>02822 <span class="keyword">struct </span>{
|
||
<a name="l02823"></a>02823 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TCNT:16; <span class="comment">/* <URM>SPI_TCNT</URM> */</span>
|
||
<a name="l02824"></a>02824 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:16;
|
||
<a name="l02825"></a>02825 } B;
|
||
<a name="l02826"></a>02826 } TCR; <span class="comment">/* DSPI Transfer Count Register <URM>DSPI_TCR</URM> @baseaddress + 0x08 */</span>
|
||
<a name="l02827"></a>02827
|
||
<a name="l02828"></a>02828 <span class="keyword">union </span>{
|
||
<a name="l02829"></a>02829 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02830"></a>02830 <span class="keyword">struct </span>{
|
||
<a name="l02831"></a>02831 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DBR:1;
|
||
<a name="l02832"></a>02832 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> FMSZ:4;
|
||
<a name="l02833"></a>02833 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CPOL:1;
|
||
<a name="l02834"></a>02834 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CPHA:1;
|
||
<a name="l02835"></a>02835 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LSBFE:1;
|
||
<a name="l02836"></a>02836 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PCSSCK:2;
|
||
<a name="l02837"></a>02837 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PASC:2;
|
||
<a name="l02838"></a>02838 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PDT:2;
|
||
<a name="l02839"></a>02839 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PBR:2;
|
||
<a name="l02840"></a>02840 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CSSCK:4;
|
||
<a name="l02841"></a>02841 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ASC:4;
|
||
<a name="l02842"></a>02842 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DT:4;
|
||
<a name="l02843"></a>02843 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BR:4;
|
||
<a name="l02844"></a>02844 } B;
|
||
<a name="l02845"></a>02845 } CTAR[8]; <span class="comment">/* Clock and Transfer Attributes Registers <URM>DSPI_CTARx</URM> @baseaddress + 0x0C - 0x28 */</span>
|
||
<a name="l02846"></a>02846
|
||
<a name="l02847"></a>02847 <span class="keyword">union </span>{
|
||
<a name="l02848"></a>02848 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02849"></a>02849 <span class="keyword">struct </span>{
|
||
<a name="l02850"></a>02850 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TCF:1;
|
||
<a name="l02851"></a>02851 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TXRXS:1;
|
||
<a name="l02852"></a>02852 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1;
|
||
<a name="l02853"></a>02853 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EOQF:1;
|
||
<a name="l02854"></a>02854 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TFUF:1;
|
||
<a name="l02855"></a>02855 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1;
|
||
<a name="l02856"></a>02856 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TFFF:1;
|
||
<a name="l02857"></a>02857 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:5;
|
||
<a name="l02858"></a>02858 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RFOF:1;
|
||
<a name="l02859"></a>02859 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1;
|
||
<a name="l02860"></a>02860 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RFDF:1;
|
||
<a name="l02861"></a>02861 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1;
|
||
<a name="l02862"></a>02862 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TXCTR:4;
|
||
<a name="l02863"></a>02863 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TXNXTPTR:4;
|
||
<a name="l02864"></a>02864 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RXCTR:4;
|
||
<a name="l02865"></a>02865 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> POPNXTPTR:4;
|
||
<a name="l02866"></a>02866 } B;
|
||
<a name="l02867"></a>02867 } SR; <span class="comment">/* Status Register <URM>DSPI_SR</URM> @baseaddress + 0x2C */</span>
|
||
<a name="l02868"></a>02868
|
||
<a name="l02869"></a>02869 <span class="keyword">union </span>{
|
||
<a name="l02870"></a>02870 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02871"></a>02871 <span class="keyword">struct </span>{
|
||
<a name="l02872"></a>02872 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TCFRE:1; <span class="comment">/*<URM>TCF_RE</URM> */</span>
|
||
<a name="l02873"></a>02873 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:2;
|
||
<a name="l02874"></a>02874 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EOQFRE:1; <span class="comment">/*<URM>EQQF_RE</URM> */</span>
|
||
<a name="l02875"></a>02875 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TFUFRE:1; <span class="comment">/*<URM>TFUF_RE</URM> */</span>
|
||
<a name="l02876"></a>02876 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1;
|
||
<a name="l02877"></a>02877 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TFFFRE:1; <span class="comment">/*<URM>TFFF_RE</URM> */</span>
|
||
<a name="l02878"></a>02878 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TFFFDIRS:1; <span class="comment">/*<URM>TFFF_DIRS</URM> */</span>
|
||
<a name="l02879"></a>02879 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:4;
|
||
<a name="l02880"></a>02880 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RFOFRE:1; <span class="comment">/*<URM>RFOF_RE</URM> */</span>
|
||
<a name="l02881"></a>02881 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1;
|
||
<a name="l02882"></a>02882 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RFDFRE:1; <span class="comment">/*<URM>RFDF_RE</URM> */</span>
|
||
<a name="l02883"></a>02883 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RFDFDIRS:1; <span class="comment">/*<URM>RFDF_DIRS</URM> */</span>
|
||
<a name="l02884"></a>02884 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:16;
|
||
<a name="l02885"></a>02885 } B;
|
||
<a name="l02886"></a>02886 } RSER; <span class="comment">/* DMA/Interrupt Request Select and Enable Register <URM>DSPI_RSER</URM> @baseaddress + 0x30 */</span>
|
||
<a name="l02887"></a>02887
|
||
<a name="l02888"></a>02888 <span class="keyword">union </span>{
|
||
<a name="l02889"></a>02889 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02890"></a>02890 <span class="keyword">struct </span>{
|
||
<a name="l02891"></a>02891 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CONT:1;
|
||
<a name="l02892"></a>02892 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CTAS:3;
|
||
<a name="l02893"></a>02893 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EOQ:1;
|
||
<a name="l02894"></a>02894 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CTCNT:1;
|
||
<a name="l02895"></a>02895 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:2;
|
||
<a name="l02896"></a>02896 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PCS7:1; <span class="comment">/* new in MPC563xM */</span>
|
||
<a name="l02897"></a>02897 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PCS6:1; <span class="comment">/* new in MPC563xM */</span>
|
||
<a name="l02898"></a>02898 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PCS5:1;
|
||
<a name="l02899"></a>02899 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PCS4:1;
|
||
<a name="l02900"></a>02900 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PCS3:1;
|
||
<a name="l02901"></a>02901 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PCS2:1;
|
||
<a name="l02902"></a>02902 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PCS1:1;
|
||
<a name="l02903"></a>02903 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PCS0:1;
|
||
<a name="l02904"></a>02904 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TXDATA:16;
|
||
<a name="l02905"></a>02905 } B;
|
||
<a name="l02906"></a>02906 } PUSHR; <span class="comment">/* PUSH TX FIFO Register <URM>DSPI_PUSHR</URM> @baseaddress + 0x34 */</span>
|
||
<a name="l02907"></a>02907
|
||
<a name="l02908"></a>02908 <span class="keyword">union </span>{
|
||
<a name="l02909"></a>02909 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02910"></a>02910 <span class="keyword">struct </span>{
|
||
<a name="l02911"></a>02911 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:16;
|
||
<a name="l02912"></a>02912 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RXDATA:16;
|
||
<a name="l02913"></a>02913 } B;
|
||
<a name="l02914"></a>02914 } POPR; <span class="comment">/* POP RX FIFO Register <URM>DSPI_POPR</URM> @baseaddress + 0x38 */</span>
|
||
<a name="l02915"></a>02915
|
||
<a name="l02916"></a>02916 <span class="keyword">union </span>{
|
||
<a name="l02917"></a>02917 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02918"></a>02918 <span class="keyword">struct </span>{
|
||
<a name="l02919"></a>02919 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TXCMD:16;
|
||
<a name="l02920"></a>02920 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TXDATA:16;
|
||
<a name="l02921"></a>02921 } B;
|
||
<a name="l02922"></a>02922 } TXFR[4]; <span class="comment">/* Transmit FIFO Registers <URM>DSPI_TXFRx</URM> @baseaddress + 0x3c - 0x78 */</span>
|
||
<a name="l02923"></a>02923
|
||
<a name="l02924"></a>02924 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DSPI_reserved_txf[12];
|
||
<a name="l02925"></a>02925
|
||
<a name="l02926"></a>02926 <span class="keyword">union </span>{
|
||
<a name="l02927"></a>02927 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02928"></a>02928 <span class="keyword">struct </span>{
|
||
<a name="l02929"></a>02929 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:16;
|
||
<a name="l02930"></a>02930 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RXDATA:16;
|
||
<a name="l02931"></a>02931 } B;
|
||
<a name="l02932"></a>02932 } RXFR[4]; <span class="comment">/* Transmit FIFO Registers <URM>DSPI_RXFRx</URM> @baseaddress + 0x7c - 0xB8 */</span>
|
||
<a name="l02933"></a>02933
|
||
<a name="l02934"></a>02934 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DSPI_reserved_rxf[12];
|
||
<a name="l02935"></a>02935
|
||
<a name="l02936"></a>02936 <span class="keyword">union </span>{
|
||
<a name="l02937"></a>02937 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02938"></a>02938 <span class="keyword">struct </span>{
|
||
<a name="l02939"></a>02939 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MTOE:1;
|
||
<a name="l02940"></a>02940 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1;
|
||
<a name="l02941"></a>02941 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MTOCNT:6;
|
||
<a name="l02942"></a>02942 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:3;
|
||
<a name="l02943"></a>02943 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TSBC:1;
|
||
<a name="l02944"></a>02944 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TXSS:1;
|
||
<a name="l02945"></a>02945 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TPOL:1;
|
||
<a name="l02946"></a>02946 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TRRE:1;
|
||
<a name="l02947"></a>02947 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CID:1;
|
||
<a name="l02948"></a>02948 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DCONT:1;
|
||
<a name="l02949"></a>02949 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DSICTAS:3;
|
||
<a name="l02950"></a>02950 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:4;
|
||
<a name="l02951"></a>02951 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DPCS7:1;
|
||
<a name="l02952"></a>02952 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DPCS6:1;
|
||
<a name="l02953"></a>02953 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DPCS5:1;
|
||
<a name="l02954"></a>02954 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DPCS4:1;
|
||
<a name="l02955"></a>02955 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DPCS3:1;
|
||
<a name="l02956"></a>02956 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DPCS2:1;
|
||
<a name="l02957"></a>02957 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DPCS1:1;
|
||
<a name="l02958"></a>02958 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DPCS0:1;
|
||
<a name="l02959"></a>02959 } B;
|
||
<a name="l02960"></a>02960 } DSICR; <span class="comment">/* DSI Configuration Register <URM>DSPI_DSICR</URM> @baseaddress + 0xBC */</span>
|
||
<a name="l02961"></a>02961
|
||
<a name="l02962"></a>02962 <span class="keyword">union </span>{
|
||
<a name="l02963"></a>02963 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02964"></a>02964 <span class="keyword">struct </span>{
|
||
<a name="l02965"></a>02965 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SER_DATA:32; <span class="comment">/* 32bit instead of 16 in MPC563xM */</span>
|
||
<a name="l02966"></a>02966 } B;
|
||
<a name="l02967"></a>02967 } SDR; <span class="comment">/* DSI Serialization Data Register <URM>DSPI_SDR</URM> @baseaddress + 0xC0 */</span>
|
||
<a name="l02968"></a>02968
|
||
<a name="l02969"></a>02969 <span class="keyword">union </span>{
|
||
<a name="l02970"></a>02970 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02971"></a>02971 <span class="keyword">struct </span>{
|
||
<a name="l02972"></a>02972 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ASER_DATA:32; <span class="comment">/* 32bit instead of 16 in MPC563xM */</span>
|
||
<a name="l02973"></a>02973 } B;
|
||
<a name="l02974"></a>02974 } ASDR; <span class="comment">/* DSI Alternate Serialization Data Register <URM>DSPI_ASDR</URM> @baseaddress + 0xC4 */</span>
|
||
<a name="l02975"></a>02975
|
||
<a name="l02976"></a>02976 <span class="keyword">union </span>{
|
||
<a name="l02977"></a>02977 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02978"></a>02978 <span class="keyword">struct </span>{
|
||
<a name="l02979"></a>02979 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> COMP_DATA:32; <span class="comment">/* 32bit instead of 16 in MPC563xM */</span>
|
||
<a name="l02980"></a>02980 } B;
|
||
<a name="l02981"></a>02981 } COMPR; <span class="comment">/* DSI Transmit Comparison Register <URM>DSPI_COMPR</URM> @baseaddress + 0xC8 */</span>
|
||
<a name="l02982"></a>02982
|
||
<a name="l02983"></a>02983 <span class="keyword">union </span>{
|
||
<a name="l02984"></a>02984 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02985"></a>02985 <span class="keyword">struct </span>{
|
||
<a name="l02986"></a>02986 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DESER_DATA:32; <span class="comment">/* 32bit instead of 16 in MPC563xM */</span>
|
||
<a name="l02987"></a>02987 } B;
|
||
<a name="l02988"></a>02988 } DDR; <span class="comment">/* DSI deserialization Data Register <URM>DSPI_DDR</URM> @baseaddress + 0xCC */</span>
|
||
<a name="l02989"></a>02989
|
||
<a name="l02990"></a>02990 <span class="keyword">union </span>{
|
||
<a name="l02991"></a>02991 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l02992"></a>02992 <span class="keyword">struct </span>{
|
||
<a name="l02993"></a>02993 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:3;
|
||
<a name="l02994"></a>02994 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TSBCNT:5;
|
||
<a name="l02995"></a>02995 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:16;
|
||
<a name="l02996"></a>02996 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DPCS1_7:1;
|
||
<a name="l02997"></a>02997 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DPCS1_6:1;
|
||
<a name="l02998"></a>02998 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DPCS1_5:1;
|
||
<a name="l02999"></a>02999 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DPCS1_4:1;
|
||
<a name="l03000"></a>03000 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DPCS1_3:1;
|
||
<a name="l03001"></a>03001 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DPCS1_2:1;
|
||
<a name="l03002"></a>03002 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DPCS1_1:1;
|
||
<a name="l03003"></a>03003 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DPCS1_0:1;
|
||
<a name="l03004"></a>03004 } B;
|
||
<a name="l03005"></a>03005 } DSICR1; <span class="comment">/* DSI Configuration Register 1 <URM>DSPI_DSICR1</URM> @baseaddress + 0xD0 */</span>
|
||
<a name="l03006"></a>03006
|
||
<a name="l03007"></a>03007 };
|
||
<a name="l03008"></a>03008 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l03009"></a>03009 <span class="comment">/* MODULE : eSCI */</span>
|
||
<a name="l03010"></a>03010 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l03011"></a>03011 <span class="keyword">struct </span>ESCI_tag {
|
||
<a name="l03012"></a>03012 <span class="keyword">union </span>{
|
||
<a name="l03013"></a>03013 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03014"></a>03014 <span class="keyword">struct </span>{
|
||
<a name="l03015"></a>03015 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:3;
|
||
<a name="l03016"></a>03016 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SBR:13;
|
||
<a name="l03017"></a>03017 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LOOPS:1;
|
||
<a name="l03018"></a>03018 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* Reserved in MPC563xM */</span>
|
||
<a name="l03019"></a>03019 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RSRC:1;
|
||
<a name="l03020"></a>03020 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> M:1;
|
||
<a name="l03021"></a>03021 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WAKE:1;
|
||
<a name="l03022"></a>03022 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ILT:1;
|
||
<a name="l03023"></a>03023 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PE:1;
|
||
<a name="l03024"></a>03024 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PT:1;
|
||
<a name="l03025"></a>03025 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TIE:1;
|
||
<a name="l03026"></a>03026 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TCIE:1;
|
||
<a name="l03027"></a>03027 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RIE:1;
|
||
<a name="l03028"></a>03028 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ILIE:1;
|
||
<a name="l03029"></a>03029 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TE:1;
|
||
<a name="l03030"></a>03030 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RE:1;
|
||
<a name="l03031"></a>03031 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RWU:1;
|
||
<a name="l03032"></a>03032 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SBK:1;
|
||
<a name="l03033"></a>03033 } B;
|
||
<a name="l03034"></a>03034 } CR1; <span class="comment">/* Control Register 1 <URM>SCIBDH, SCIBDL, SCICR1, SCICR2</URM> @baseaddress + 0x00 */</span>
|
||
<a name="l03035"></a>03035
|
||
<a name="l03036"></a>03036 <span class="keyword">union </span>{
|
||
<a name="l03037"></a>03037 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> R;
|
||
<a name="l03038"></a>03038 <span class="keyword">struct </span>{
|
||
<a name="l03039"></a>03039 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> MDIS:1;
|
||
<a name="l03040"></a>03040 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> FBR:1;
|
||
<a name="l03041"></a>03041 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> BSTP:1;
|
||
<a name="l03042"></a>03042 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> IEBERR:1; <span class="comment">/* <URM>BERIE</URM> */</span>
|
||
<a name="l03043"></a>03043 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> RXDMA:1;
|
||
<a name="l03044"></a>03044 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> TXDMA:1;
|
||
<a name="l03045"></a>03045 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> BRK13:1; <span class="comment">/* <URM>BRCL</URM> */</span>
|
||
<a name="l03046"></a>03046 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> TXDIR:1;
|
||
<a name="l03047"></a>03047 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> BESM13:1; <span class="comment">/* <URM>BESM</URM> */</span>
|
||
<a name="l03048"></a>03048 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> SBSTP:1; <span class="comment">/* <URM>BESTP</URM> */</span>
|
||
<a name="l03049"></a>03049 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> RXPOL:1;
|
||
<a name="l03050"></a>03050 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> PMSK:1;
|
||
<a name="l03051"></a>03051 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> ORIE:1;
|
||
<a name="l03052"></a>03052 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> NFIE:1;
|
||
<a name="l03053"></a>03053 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> FEIE:1;
|
||
<a name="l03054"></a>03054 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> PFIE:1;
|
||
<a name="l03055"></a>03055 } B;
|
||
<a name="l03056"></a>03056 } CR2; <span class="comment">/* Control Register 2 <URM>SCICR3, SCICR4</URM> @baseaddress + 0x04 */</span>
|
||
<a name="l03057"></a>03057
|
||
<a name="l03058"></a>03058 <span class="keyword">union </span>{
|
||
<a name="l03059"></a>03059 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> R;
|
||
<a name="l03060"></a>03060 <span class="keyword">struct </span>{
|
||
<a name="l03061"></a>03061 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> R8:1; <span class="comment">/* <URM>RN</URM> */</span>
|
||
<a name="l03062"></a>03062 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> T8:1; <span class="comment">/* <URM>TN</URM> */</span>
|
||
<a name="l03063"></a>03063 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> ERR:1;
|
||
<a name="l03064"></a>03064 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a>:1;
|
||
<a name="l03065"></a>03065 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> R:4;
|
||
<a name="l03066"></a>03066 <a class="code" href="group___p_p_c___c_o_r_e.html#ga7ee1720c821bd2a2b26c67afdc8b3549">vuint8_t</a> D;
|
||
<a name="l03067"></a>03067 } B;
|
||
<a name="l03068"></a>03068 } DR; <span class="comment">/* Data Register <URM>SCIDRH, SCIDRL</URM> @baseaddress + 0x06 */</span>
|
||
<a name="l03069"></a>03069
|
||
<a name="l03070"></a>03070 <span class="keyword">union </span>{
|
||
<a name="l03071"></a>03071 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03072"></a>03072 <span class="keyword">struct </span>{
|
||
<a name="l03073"></a>03073 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TDRE:1;
|
||
<a name="l03074"></a>03074 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TC:1;
|
||
<a name="l03075"></a>03075 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RDRF:1;
|
||
<a name="l03076"></a>03076 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IDLE:1;
|
||
<a name="l03077"></a>03077 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OR:1;
|
||
<a name="l03078"></a>03078 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> NF:1;
|
||
<a name="l03079"></a>03079 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> FE:1;
|
||
<a name="l03080"></a>03080 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PF:1;
|
||
<a name="l03081"></a>03081 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:3;
|
||
<a name="l03082"></a>03082 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BERR:1;
|
||
<a name="l03083"></a>03083 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:2;
|
||
<a name="l03084"></a>03084 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TACT:1;
|
||
<a name="l03085"></a>03085 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RAF:1; <span class="comment">/* <URM>RACT</URM> */</span>
|
||
<a name="l03086"></a>03086 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RXRDY:1;
|
||
<a name="l03087"></a>03087 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TXRDY:1;
|
||
<a name="l03088"></a>03088 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LWAKE:1;
|
||
<a name="l03089"></a>03089 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> STO:1;
|
||
<a name="l03090"></a>03090 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PBERR:1;
|
||
<a name="l03091"></a>03091 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CERR:1;
|
||
<a name="l03092"></a>03092 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CKERR:1;
|
||
<a name="l03093"></a>03093 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> FRC:1;
|
||
<a name="l03094"></a>03094 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:6;
|
||
<a name="l03095"></a>03095 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> UREQ:1;
|
||
<a name="l03096"></a>03096 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OVFL:1;
|
||
<a name="l03097"></a>03097 } B;
|
||
<a name="l03098"></a>03098 } SR; <span class="comment">/* Status Register <URM>SCISR1, SCIRSR2, LINSTAT1, LINSTAT2 </URM> @baseaddress + 0x08 */</span>
|
||
<a name="l03099"></a>03099
|
||
<a name="l03100"></a>03100 <span class="keyword">union </span>{
|
||
<a name="l03101"></a>03101 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03102"></a>03102 <span class="keyword">struct </span>{
|
||
<a name="l03103"></a>03103 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LRES:1;
|
||
<a name="l03104"></a>03104 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WU:1;
|
||
<a name="l03105"></a>03105 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WUD0:1;
|
||
<a name="l03106"></a>03106 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WUD1:1;
|
||
<a name="l03107"></a>03107 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:2; <span class="comment">/* reserved: LDBG and DSF not longer supported */</span>
|
||
<a name="l03108"></a>03108 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PRTY:1;
|
||
<a name="l03109"></a>03109 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LIN:1;
|
||
<a name="l03110"></a>03110 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RXIE:1;
|
||
<a name="l03111"></a>03111 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TXIE:1;
|
||
<a name="l03112"></a>03112 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WUIE:1;
|
||
<a name="l03113"></a>03113 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> STIE:1;
|
||
<a name="l03114"></a>03114 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PBIE:1;
|
||
<a name="l03115"></a>03115 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIE:1;
|
||
<a name="l03116"></a>03116 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CKIE:1;
|
||
<a name="l03117"></a>03117 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> FCIE:1;
|
||
<a name="l03118"></a>03118 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:6;
|
||
<a name="l03119"></a>03119 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> UQIE:1;
|
||
<a name="l03120"></a>03120 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OFIE:1;
|
||
<a name="l03121"></a>03121 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:8;
|
||
<a name="l03122"></a>03122 } B;
|
||
<a name="l03123"></a>03123 } LCR; <span class="comment">/* LIN Control Register <URM>LINCTRL1, LINCTRL2, LINCTRL3 </URM> @baseaddress + 0x0C */</span>
|
||
<a name="l03124"></a>03124
|
||
<a name="l03125"></a>03125 <span class="keyword">union </span>{
|
||
<a name="l03126"></a>03126 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03127"></a>03127 } LTR; <span class="comment">/* LIN Transmit Register <URM>LINTX</URM> @baseaddress + 0x10 */</span>
|
||
<a name="l03128"></a>03128
|
||
<a name="l03129"></a>03129 <span class="keyword">union </span>{
|
||
<a name="l03130"></a>03130 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03131"></a>03131 } LRR; <span class="comment">/* LIN Recieve Register <URM>LINRX</URM> @baseaddress + 0x14 */</span>
|
||
<a name="l03132"></a>03132
|
||
<a name="l03133"></a>03133 <span class="keyword">union </span>{
|
||
<a name="l03134"></a>03134 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03135"></a>03135 <span class="keyword">struct </span>{
|
||
<a name="l03136"></a>03136 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> P:16;
|
||
<a name="l03137"></a>03137 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:3;
|
||
<a name="l03138"></a>03138 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SYNM:1;
|
||
<a name="l03139"></a>03139 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EROE:1;
|
||
<a name="l03140"></a>03140 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERFE:1;
|
||
<a name="l03141"></a>03141 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERPE:1;
|
||
<a name="l03142"></a>03142 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> M2:1;
|
||
<a name="l03143"></a>03143 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:8;
|
||
<a name="l03144"></a>03144 } B;
|
||
<a name="l03145"></a>03145 } LPR; <span class="comment">/* LIN CRC Polynom Register <URM>LINCRCP1, LINCRCP2, SCICR5</URM> @baseaddress + 0x18 */</span>
|
||
<a name="l03146"></a>03146
|
||
<a name="l03147"></a>03147 };
|
||
<a name="l03148"></a>03148 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l03149"></a>03149 <span class="comment">/* MODULE : eSCI */</span>
|
||
<a name="l03150"></a>03150 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l03151"></a>03151 <span class="keyword">struct </span>ESCI_12_13_bit_tag {
|
||
<a name="l03152"></a>03152 <span class="keyword">union </span>{
|
||
<a name="l03153"></a>03153 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> R;
|
||
<a name="l03154"></a>03154 <span class="keyword">struct </span>{
|
||
<a name="l03155"></a>03155 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> R8:1;
|
||
<a name="l03156"></a>03156 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> T8:1;
|
||
<a name="l03157"></a>03157 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> ERR:1;
|
||
<a name="l03158"></a>03158 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a>:1;
|
||
<a name="l03159"></a>03159 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> D:12;
|
||
<a name="l03160"></a>03160 } B;
|
||
<a name="l03161"></a>03161 } DR; <span class="comment">/* Data Register */</span>
|
||
<a name="l03162"></a>03162 };
|
||
<a name="l03163"></a>03163 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l03164"></a>03164 <span class="comment">/* MODULE : FlexCAN */</span>
|
||
<a name="l03165"></a>03165 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l03166"></a>03166 <span class="keyword">struct </span>FLEXCAN_BUF_t {
|
||
<a name="l03167"></a>03167 <span class="keyword">union </span>{
|
||
<a name="l03168"></a>03168 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03169"></a>03169 <span class="keyword">struct </span>{
|
||
<a name="l03170"></a>03170 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:4;
|
||
<a name="l03171"></a>03171 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CODE:4;
|
||
<a name="l03172"></a>03172 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1;
|
||
<a name="l03173"></a>03173 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SRR:1;
|
||
<a name="l03174"></a>03174 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IDE:1;
|
||
<a name="l03175"></a>03175 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RTR:1;
|
||
<a name="l03176"></a>03176 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LENGTH:4;
|
||
<a name="l03177"></a>03177 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TIMESTAMP:16;
|
||
<a name="l03178"></a>03178 } B;
|
||
<a name="l03179"></a>03179 } CS;
|
||
<a name="l03180"></a>03180
|
||
<a name="l03181"></a>03181 <span class="keyword">union </span>{
|
||
<a name="l03182"></a>03182 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03183"></a>03183 <span class="keyword">struct </span>{
|
||
<a name="l03184"></a>03184 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PRIO:3;
|
||
<a name="l03185"></a>03185 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> STD_ID:11;
|
||
<a name="l03186"></a>03186 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EXT_ID:18;
|
||
<a name="l03187"></a>03187 } B;
|
||
<a name="l03188"></a>03188 } ID;
|
||
<a name="l03189"></a>03189
|
||
<a name="l03190"></a>03190 <span class="keyword">union </span>{
|
||
<a name="l03191"></a>03191 <span class="comment">/*vuint8_t B[8]; */</span><span class="comment">/* Data buffer in Bytes (8 bits) */</span><span class="comment">/* Not used in MPC563xM */</span>
|
||
<a name="l03192"></a>03192 <span class="comment">/*vuint16_t H[4]; */</span><span class="comment">/* Data buffer in Half-words (16 bits) */</span><span class="comment">/* Not used in MPC563xM */</span>
|
||
<a name="l03193"></a>03193 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> W[2]; <span class="comment">/* Data buffer in words (32 bits) */</span>
|
||
<a name="l03194"></a>03194 <span class="comment">/*vuint32_t R[2]; */</span><span class="comment">/* Data buffer in words (32 bits) */</span><span class="comment">/* Not used in MPC563xM */</span>
|
||
<a name="l03195"></a>03195 } DATA;
|
||
<a name="l03196"></a>03196
|
||
<a name="l03197"></a>03197 }; <span class="comment">/* end of FLEXCAN_BUF_t */</span>
|
||
<a name="l03198"></a>03198
|
||
<a name="l03199"></a>03199 <span class="keyword">struct </span>FLEXCAN_RXFIFO_t {
|
||
<a name="l03200"></a>03200 <span class="keyword">union </span>{
|
||
<a name="l03201"></a>03201 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03202"></a>03202 <span class="keyword">struct </span>{
|
||
<a name="l03203"></a>03203 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:9;
|
||
<a name="l03204"></a>03204 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SRR:1;
|
||
<a name="l03205"></a>03205 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IDE:1;
|
||
<a name="l03206"></a>03206 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RTR:1;
|
||
<a name="l03207"></a>03207 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LENGTH:4;
|
||
<a name="l03208"></a>03208 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TIMESTAMP:16;
|
||
<a name="l03209"></a>03209 } B;
|
||
<a name="l03210"></a>03210 } CS;
|
||
<a name="l03211"></a>03211
|
||
<a name="l03212"></a>03212 <span class="keyword">union </span>{
|
||
<a name="l03213"></a>03213 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03214"></a>03214 <span class="keyword">struct </span>{
|
||
<a name="l03215"></a>03215 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:3;
|
||
<a name="l03216"></a>03216 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> STD_ID:11;
|
||
<a name="l03217"></a>03217 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EXT_ID:18;
|
||
<a name="l03218"></a>03218 } B;
|
||
<a name="l03219"></a>03219 } ID;
|
||
<a name="l03220"></a>03220
|
||
<a name="l03221"></a>03221 <span class="keyword">union </span>{
|
||
<a name="l03222"></a>03222 <span class="comment">/*vuint8_t B[8]; */</span><span class="comment">/* Data buffer in Bytes (8 bits) */</span><span class="comment">/* Not used in MPC563xM */</span>
|
||
<a name="l03223"></a>03223 <span class="comment">/*vuint16_t H[4]; */</span><span class="comment">/* Data buffer in Half-words (16 bits) */</span><span class="comment">/* Not used in MPC563xM */</span>
|
||
<a name="l03224"></a>03224 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> W[2]; <span class="comment">/* Data buffer in words (32 bits) */</span>
|
||
<a name="l03225"></a>03225 <span class="comment">/*vuint32_t R[2]; */</span><span class="comment">/* Data buffer in words (32 bits) */</span><span class="comment">/* Not used in MPC563xM */</span>
|
||
<a name="l03226"></a>03226 } DATA;
|
||
<a name="l03227"></a>03227
|
||
<a name="l03228"></a>03228 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> FLEXCAN_RXFIFO_reserved[20]; <span class="comment">/* {0x00E0-0x0090}/0x4 = 0x14 */</span>
|
||
<a name="l03229"></a>03229
|
||
<a name="l03230"></a>03230 <span class="keyword">union </span>{
|
||
<a name="l03231"></a>03231 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03232"></a>03232 } IDTABLE[8];
|
||
<a name="l03233"></a>03233
|
||
<a name="l03234"></a>03234 }; <span class="comment">/* end of FLEXCAN_RXFIFO_t */</span>
|
||
<a name="l03235"></a>03235
|
||
<a name="l03236"></a>03236 <span class="keyword">struct </span>FLEXCAN2_tag {
|
||
<a name="l03237"></a>03237 <span class="keyword">union </span>{
|
||
<a name="l03238"></a>03238 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03239"></a>03239 <span class="keyword">struct </span>{
|
||
<a name="l03240"></a>03240 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MDIS:1;
|
||
<a name="l03241"></a>03241 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> FRZ:1;
|
||
<a name="l03242"></a>03242 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> FEN:1; <span class="comment">/* new in MPC563xM */</span>
|
||
<a name="l03243"></a>03243 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> HALT:1;
|
||
<a name="l03244"></a>03244 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> NOTRDY:1; <span class="comment">/* <URM>NOT_RDY</URM> */</span>
|
||
<a name="l03245"></a>03245 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WAK_MSK:1; <span class="comment">/* new in MPC563xM */</span>
|
||
<a name="l03246"></a>03246 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SOFTRST:1; <span class="comment">/* <URM>SOFT_RST</URM> */</span>
|
||
<a name="l03247"></a>03247 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> FRZACK:1; <span class="comment">/* <URM>FRZ_ACK</URM> */</span>
|
||
<a name="l03248"></a>03248 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SUPV:1; <span class="comment">/* new in MPC563xM */</span>
|
||
<a name="l03249"></a>03249 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SLF_WAK:1; <span class="comment">/* new in MPC563xM */</span>
|
||
<a name="l03250"></a>03250
|
||
<a name="l03251"></a>03251 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WRNEN:1; <span class="comment">/* <URM>WRN_EN</URM> */</span>
|
||
<a name="l03252"></a>03252
|
||
<a name="l03253"></a>03253 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MDISACK:1; <span class="comment">/* <URM>LPM_ACK</URM> */</span>
|
||
<a name="l03254"></a>03254 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WAK_SRC:1; <span class="comment">/* new in MPC563xM */</span>
|
||
<a name="l03255"></a>03255 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DOZE:1; <span class="comment">/* new in MPC563xM */</span>
|
||
<a name="l03256"></a>03256
|
||
<a name="l03257"></a>03257 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SRXDIS:1; <span class="comment">/* <URM>SRX_DIS</URM> */</span>
|
||
<a name="l03258"></a>03258 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MBFEN:1; <span class="comment">/* <URM>BCC</URM> */</span>
|
||
<a name="l03259"></a>03259 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:2;
|
||
<a name="l03260"></a>03260
|
||
<a name="l03261"></a>03261 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LPRIO_EN:1; <span class="comment">/* new in MPC563xM */</span>
|
||
<a name="l03262"></a>03262 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> AEN:1; <span class="comment">/* new in MPC563xM */</span>
|
||
<a name="l03263"></a>03263 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:2;
|
||
<a name="l03264"></a>03264 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IDAM:2; <span class="comment">/* new in MPC563xM */</span>
|
||
<a name="l03265"></a>03265 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:2;
|
||
<a name="l03266"></a>03266
|
||
<a name="l03267"></a>03267 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MAXMB:6;
|
||
<a name="l03268"></a>03268 } B;
|
||
<a name="l03269"></a>03269 } MCR; <span class="comment">/* Module Configuration Register */</span>
|
||
<a name="l03270"></a>03270
|
||
<a name="l03271"></a>03271 <span class="keyword">union </span>{
|
||
<a name="l03272"></a>03272 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03273"></a>03273 <span class="keyword">struct </span>{
|
||
<a name="l03274"></a>03274 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PRESDIV:8;
|
||
<a name="l03275"></a>03275 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RJW:2;
|
||
<a name="l03276"></a>03276 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PSEG1:3;
|
||
<a name="l03277"></a>03277 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PSEG2:3;
|
||
<a name="l03278"></a>03278 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BOFFMSK:1; <span class="comment">/* <URM>BOFF_MSK</URM> */</span>
|
||
<a name="l03279"></a>03279 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERRMSK:1; <span class="comment">/* <URM>ERR_MSK</URM> */</span>
|
||
<a name="l03280"></a>03280 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CLKSRC:1; <span class="comment">/* <URM>CLK_SRC</URM> */</span>
|
||
<a name="l03281"></a>03281 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LPB:1;
|
||
<a name="l03282"></a>03282 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TWRNMSK:1; <span class="comment">/* <URM>TWRN_MSK</URM> */</span>
|
||
<a name="l03283"></a>03283 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RWRNMSK:1; <span class="comment">/* <URM>RWRN_MSK</URM> */</span>
|
||
<a name="l03284"></a>03284 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:2;
|
||
<a name="l03285"></a>03285 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SMP:1;
|
||
<a name="l03286"></a>03286 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BOFFREC:1; <span class="comment">/* <URM>BOFF_REC</URM> */</span>
|
||
<a name="l03287"></a>03287 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TSYN:1;
|
||
<a name="l03288"></a>03288 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LBUF:1;
|
||
<a name="l03289"></a>03289 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LOM:1;
|
||
<a name="l03290"></a>03290 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PROPSEG:3;
|
||
<a name="l03291"></a>03291 } B; <span class="comment">/* Control Register */</span>
|
||
<a name="l03292"></a>03292 } CR; <span class="comment">/* <URM>CTRL</URM> */</span>
|
||
<a name="l03293"></a>03293
|
||
<a name="l03294"></a>03294 <span class="keyword">union </span>{
|
||
<a name="l03295"></a>03295 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03296"></a>03296 } TIMER; <span class="comment">/* Free Running Timer */</span>
|
||
<a name="l03297"></a>03297
|
||
<a name="l03298"></a>03298 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga2ba621978a511250f7250fb10e05ffbe">int32_t</a> FLEXCAN_reserved00;
|
||
<a name="l03299"></a>03299
|
||
<a name="l03300"></a>03300 <span class="keyword">union </span>{
|
||
<a name="l03301"></a>03301 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03302"></a>03302 <span class="keyword">struct </span>{
|
||
<a name="l03303"></a>03303 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:3;
|
||
<a name="l03304"></a>03304 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MI:29;
|
||
<a name="l03305"></a>03305 } B;
|
||
<a name="l03306"></a>03306 } RXGMASK; <span class="comment">/* RX Global Mask */</span>
|
||
<a name="l03307"></a>03307
|
||
<a name="l03308"></a>03308 <span class="keyword">union </span>{
|
||
<a name="l03309"></a>03309 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03310"></a>03310 <span class="keyword">struct </span>{
|
||
<a name="l03311"></a>03311 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:3;
|
||
<a name="l03312"></a>03312 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MI:29;
|
||
<a name="l03313"></a>03313 } B;
|
||
<a name="l03314"></a>03314 } RX14MASK; <span class="comment">/* RX 14 Mask */</span>
|
||
<a name="l03315"></a>03315
|
||
<a name="l03316"></a>03316 <span class="keyword">union </span>{
|
||
<a name="l03317"></a>03317 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03318"></a>03318 <span class="keyword">struct </span>{
|
||
<a name="l03319"></a>03319 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:3;
|
||
<a name="l03320"></a>03320 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MI:29;
|
||
<a name="l03321"></a>03321 } B;
|
||
<a name="l03322"></a>03322 } RX15MASK; <span class="comment">/* RX 15 Mask */</span>
|
||
<a name="l03323"></a>03323
|
||
<a name="l03324"></a>03324 <span class="keyword">union </span>{
|
||
<a name="l03325"></a>03325 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03326"></a>03326 <span class="keyword">struct </span>{
|
||
<a name="l03327"></a>03327 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:16;
|
||
<a name="l03328"></a>03328 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RXECNT:8;
|
||
<a name="l03329"></a>03329 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TXECNT:8;
|
||
<a name="l03330"></a>03330 } B;
|
||
<a name="l03331"></a>03331 } ECR; <span class="comment">/* Error Counter Register */</span>
|
||
<a name="l03332"></a>03332
|
||
<a name="l03333"></a>03333 <span class="keyword">union </span>{
|
||
<a name="l03334"></a>03334 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03335"></a>03335 <span class="keyword">struct </span>{
|
||
<a name="l03336"></a>03336 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:14;
|
||
<a name="l03337"></a>03337 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TWRNINT:1; <span class="comment">/* <URM>TWRN_INT</URM> */</span>
|
||
<a name="l03338"></a>03338 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RWRNINT:1; <span class="comment">/* <URM>RWRN_INT</URM> */</span>
|
||
<a name="l03339"></a>03339 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BIT1ERR:1; <span class="comment">/* <URM>BIT1_ERR</URM> */</span>
|
||
<a name="l03340"></a>03340 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BIT0ERR:1; <span class="comment">/* <URM>BIT0_ERR</URM> */</span>
|
||
<a name="l03341"></a>03341 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ACKERR:1; <span class="comment">/* <URM>ACK_ERR</URM> */</span>
|
||
<a name="l03342"></a>03342 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CRCERR:1; <span class="comment">/* <URM>CRC_ERR</URM> */</span>
|
||
<a name="l03343"></a>03343 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> FRMERR:1; <span class="comment">/* <URM>FRM_ERR</URM> */</span>
|
||
<a name="l03344"></a>03344 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> STFERR:1; <span class="comment">/* <URM>STF_ERR</URM> */</span>
|
||
<a name="l03345"></a>03345 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TXWRN:1; <span class="comment">/* <URM>TX_WRN</URM> */</span>
|
||
<a name="l03346"></a>03346 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RXWRN:1; <span class="comment">/* <URM>RX_WRN</URM> */</span>
|
||
<a name="l03347"></a>03347 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IDLE:1;
|
||
<a name="l03348"></a>03348 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TXRX:1;
|
||
<a name="l03349"></a>03349 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> FLTCONF:2; <span class="comment">/* <URM>FLT_CONF</URM> */</span>
|
||
<a name="l03350"></a>03350 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1;
|
||
<a name="l03351"></a>03351 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BOFFINT:1; <span class="comment">/* <URM>BOFF_INT</URM> */</span>
|
||
<a name="l03352"></a>03352 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERRINT:1; <span class="comment">/* <URM>ERR_INT</URM> */</span>
|
||
<a name="l03353"></a>03353 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WAK_INT:1; <span class="comment">/* new in MPC563xM */</span>
|
||
<a name="l03354"></a>03354 } B;
|
||
<a name="l03355"></a>03355 } ESR; <span class="comment">/* Error and Status Register */</span>
|
||
<a name="l03356"></a>03356
|
||
<a name="l03357"></a>03357 <span class="keyword">union </span>{
|
||
<a name="l03358"></a>03358 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03359"></a>03359 <span class="keyword">struct </span>{
|
||
<a name="l03360"></a>03360 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF63M:1;
|
||
<a name="l03361"></a>03361 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF62M:1;
|
||
<a name="l03362"></a>03362 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF61M:1;
|
||
<a name="l03363"></a>03363 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF60M:1;
|
||
<a name="l03364"></a>03364 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF59M:1;
|
||
<a name="l03365"></a>03365 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF58M:1;
|
||
<a name="l03366"></a>03366 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF57M:1;
|
||
<a name="l03367"></a>03367 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF56M:1;
|
||
<a name="l03368"></a>03368 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF55M:1;
|
||
<a name="l03369"></a>03369 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF54M:1;
|
||
<a name="l03370"></a>03370 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF53M:1;
|
||
<a name="l03371"></a>03371 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF52M:1;
|
||
<a name="l03372"></a>03372 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF51M:1;
|
||
<a name="l03373"></a>03373 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF50M:1;
|
||
<a name="l03374"></a>03374 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF49M:1;
|
||
<a name="l03375"></a>03375 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF48M:1;
|
||
<a name="l03376"></a>03376 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF47M:1;
|
||
<a name="l03377"></a>03377 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF46M:1;
|
||
<a name="l03378"></a>03378 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF45M:1;
|
||
<a name="l03379"></a>03379 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF44M:1;
|
||
<a name="l03380"></a>03380 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF43M:1;
|
||
<a name="l03381"></a>03381 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF42M:1;
|
||
<a name="l03382"></a>03382 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF41M:1;
|
||
<a name="l03383"></a>03383 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF40M:1;
|
||
<a name="l03384"></a>03384 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF39M:1;
|
||
<a name="l03385"></a>03385 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF38M:1;
|
||
<a name="l03386"></a>03386 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF37M:1;
|
||
<a name="l03387"></a>03387 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF36M:1;
|
||
<a name="l03388"></a>03388 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF35M:1;
|
||
<a name="l03389"></a>03389 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF34M:1;
|
||
<a name="l03390"></a>03390 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF33M:1;
|
||
<a name="l03391"></a>03391 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF32M:1;
|
||
<a name="l03392"></a>03392 } B; <span class="comment">/* Interruput Masks Register */</span>
|
||
<a name="l03393"></a>03393 } IMRH; <span class="comment">/* <URM>IMASK2</URM> */</span>
|
||
<a name="l03394"></a>03394
|
||
<a name="l03395"></a>03395 <span class="keyword">union </span>{
|
||
<a name="l03396"></a>03396 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03397"></a>03397 <span class="keyword">struct </span>{
|
||
<a name="l03398"></a>03398 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF31M:1;
|
||
<a name="l03399"></a>03399 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF30M:1;
|
||
<a name="l03400"></a>03400 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF29M:1;
|
||
<a name="l03401"></a>03401 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF28M:1;
|
||
<a name="l03402"></a>03402 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF27M:1;
|
||
<a name="l03403"></a>03403 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF26M:1;
|
||
<a name="l03404"></a>03404 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF25M:1;
|
||
<a name="l03405"></a>03405 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF24M:1;
|
||
<a name="l03406"></a>03406 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF23M:1;
|
||
<a name="l03407"></a>03407 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF22M:1;
|
||
<a name="l03408"></a>03408 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF21M:1;
|
||
<a name="l03409"></a>03409 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF20M:1;
|
||
<a name="l03410"></a>03410 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF19M:1;
|
||
<a name="l03411"></a>03411 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF18M:1;
|
||
<a name="l03412"></a>03412 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF17M:1;
|
||
<a name="l03413"></a>03413 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF16M:1;
|
||
<a name="l03414"></a>03414 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF15M:1;
|
||
<a name="l03415"></a>03415 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF14M:1;
|
||
<a name="l03416"></a>03416 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF13M:1;
|
||
<a name="l03417"></a>03417 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF12M:1;
|
||
<a name="l03418"></a>03418 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF11M:1;
|
||
<a name="l03419"></a>03419 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF10M:1;
|
||
<a name="l03420"></a>03420 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF09M:1;
|
||
<a name="l03421"></a>03421 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF08M:1;
|
||
<a name="l03422"></a>03422 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF07M:1;
|
||
<a name="l03423"></a>03423 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF06M:1;
|
||
<a name="l03424"></a>03424 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF05M:1;
|
||
<a name="l03425"></a>03425 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF04M:1;
|
||
<a name="l03426"></a>03426 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF03M:1;
|
||
<a name="l03427"></a>03427 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF02M:1;
|
||
<a name="l03428"></a>03428 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF01M:1;
|
||
<a name="l03429"></a>03429 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF00M:1;
|
||
<a name="l03430"></a>03430 } B; <span class="comment">/* Interruput Masks Register */</span>
|
||
<a name="l03431"></a>03431 } IMRL; <span class="comment">/* <URM>IMASK1</URM> */</span>
|
||
<a name="l03432"></a>03432
|
||
<a name="l03433"></a>03433 <span class="keyword">union </span>{
|
||
<a name="l03434"></a>03434 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03435"></a>03435 <span class="keyword">struct </span>{
|
||
<a name="l03436"></a>03436 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF63I:1;
|
||
<a name="l03437"></a>03437 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF62I:1;
|
||
<a name="l03438"></a>03438 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF61I:1;
|
||
<a name="l03439"></a>03439 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF60I:1;
|
||
<a name="l03440"></a>03440 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF59I:1;
|
||
<a name="l03441"></a>03441 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF58I:1;
|
||
<a name="l03442"></a>03442 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF57I:1;
|
||
<a name="l03443"></a>03443 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF56I:1;
|
||
<a name="l03444"></a>03444 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF55I:1;
|
||
<a name="l03445"></a>03445 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF54I:1;
|
||
<a name="l03446"></a>03446 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF53I:1;
|
||
<a name="l03447"></a>03447 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF52I:1;
|
||
<a name="l03448"></a>03448 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF51I:1;
|
||
<a name="l03449"></a>03449 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF50I:1;
|
||
<a name="l03450"></a>03450 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF49I:1;
|
||
<a name="l03451"></a>03451 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF48I:1;
|
||
<a name="l03452"></a>03452 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF47I:1;
|
||
<a name="l03453"></a>03453 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF46I:1;
|
||
<a name="l03454"></a>03454 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF45I:1;
|
||
<a name="l03455"></a>03455 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF44I:1;
|
||
<a name="l03456"></a>03456 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF43I:1;
|
||
<a name="l03457"></a>03457 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF42I:1;
|
||
<a name="l03458"></a>03458 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF41I:1;
|
||
<a name="l03459"></a>03459 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF40I:1;
|
||
<a name="l03460"></a>03460 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF39I:1;
|
||
<a name="l03461"></a>03461 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF38I:1;
|
||
<a name="l03462"></a>03462 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF37I:1;
|
||
<a name="l03463"></a>03463 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF36I:1;
|
||
<a name="l03464"></a>03464 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF35I:1;
|
||
<a name="l03465"></a>03465 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF34I:1;
|
||
<a name="l03466"></a>03466 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF33I:1;
|
||
<a name="l03467"></a>03467 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF32I:1;
|
||
<a name="l03468"></a>03468 } B; <span class="comment">/* Interruput Flag Register */</span>
|
||
<a name="l03469"></a>03469 } IFRH; <span class="comment">/* <URM>IFLAG2</URM> */</span>
|
||
<a name="l03470"></a>03470
|
||
<a name="l03471"></a>03471 <span class="keyword">union </span>{
|
||
<a name="l03472"></a>03472 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03473"></a>03473 <span class="keyword">struct </span>{
|
||
<a name="l03474"></a>03474 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF31I:1;
|
||
<a name="l03475"></a>03475 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF30I:1;
|
||
<a name="l03476"></a>03476 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF29I:1;
|
||
<a name="l03477"></a>03477 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF28I:1;
|
||
<a name="l03478"></a>03478 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF27I:1;
|
||
<a name="l03479"></a>03479 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF26I:1;
|
||
<a name="l03480"></a>03480 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF25I:1;
|
||
<a name="l03481"></a>03481 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF24I:1;
|
||
<a name="l03482"></a>03482 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF23I:1;
|
||
<a name="l03483"></a>03483 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF22I:1;
|
||
<a name="l03484"></a>03484 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF21I:1;
|
||
<a name="l03485"></a>03485 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF20I:1;
|
||
<a name="l03486"></a>03486 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF19I:1;
|
||
<a name="l03487"></a>03487 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF18I:1;
|
||
<a name="l03488"></a>03488 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF17I:1;
|
||
<a name="l03489"></a>03489 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF16I:1;
|
||
<a name="l03490"></a>03490 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF15I:1;
|
||
<a name="l03491"></a>03491 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF14I:1;
|
||
<a name="l03492"></a>03492 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF13I:1;
|
||
<a name="l03493"></a>03493 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF12I:1;
|
||
<a name="l03494"></a>03494 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF11I:1;
|
||
<a name="l03495"></a>03495 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF10I:1;
|
||
<a name="l03496"></a>03496 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF09I:1;
|
||
<a name="l03497"></a>03497 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF08I:1;
|
||
<a name="l03498"></a>03498 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF07I:1;
|
||
<a name="l03499"></a>03499 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF06I:1;
|
||
<a name="l03500"></a>03500 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF05I:1;
|
||
<a name="l03501"></a>03501 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF04I:1;
|
||
<a name="l03502"></a>03502 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF03I:1;
|
||
<a name="l03503"></a>03503 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF02I:1;
|
||
<a name="l03504"></a>03504 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF01I:1;
|
||
<a name="l03505"></a>03505 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BUF00I:1;
|
||
<a name="l03506"></a>03506 } B; <span class="comment">/* Interruput Flag Register */</span>
|
||
<a name="l03507"></a>03507 } IFRL; <span class="comment">/* <URM>IFLAG1</URM> */</span>
|
||
<a name="l03508"></a>03508
|
||
<a name="l03509"></a>03509 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> flexcan2_reserved2[19];
|
||
<a name="l03510"></a>03510
|
||
<a name="l03511"></a>03511 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l03512"></a>03512 <span class="comment">/* Use either Standard Buffer Structure OR RX FIFO and Buffer Structure */</span>
|
||
<a name="l03513"></a>03513 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l03514"></a>03514 <span class="comment">/* Standard Buffer Structure */</span>
|
||
<a name="l03515"></a>03515 <span class="keyword">struct </span>FLEXCAN_BUF_t BUF[64];
|
||
<a name="l03516"></a>03516
|
||
<a name="l03517"></a>03517 <span class="comment">/* RX FIFO and Buffer Structure */</span><span class="comment">/* New options in MPC563xM */</span>
|
||
<a name="l03518"></a>03518 <span class="comment">/*struct FLEXCAN_RXFIFO_t RXFIFO; */</span>
|
||
<a name="l03519"></a>03519 <span class="comment">/*struct FLEXCAN_BUF_t BUF[56]; */</span>
|
||
<a name="l03520"></a>03520 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l03521"></a>03521
|
||
<a name="l03522"></a>03522 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> FLEXCAN_reserved3[256]; <span class="comment">/* {0x0880-0x0480}/0x4 = 0x100 */</span><span class="comment">/* (New in MPC563xM) Address Base + 0x0034 */</span>
|
||
<a name="l03523"></a>03523
|
||
<a name="l03524"></a>03524 <span class="keyword">union </span>{
|
||
<a name="l03525"></a>03525 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03526"></a>03526 <span class="keyword">struct </span>{
|
||
<a name="l03527"></a>03527 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MI:32;
|
||
<a name="l03528"></a>03528 } B; <span class="comment">/* RX Individual Mask Registers */</span>
|
||
<a name="l03529"></a>03529 } RXIMR[64]; <span class="comment">/* (New in MPC563xM) Address Base + 0x0880 */</span>
|
||
<a name="l03530"></a>03530
|
||
<a name="l03531"></a>03531 }; <span class="comment">/* end of FLEXCAN_tag */</span>
|
||
<a name="l03532"></a>03532 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l03533"></a>03533 <span class="comment">/* MODULE : Decimation Filter (DECFIL) */</span>
|
||
<a name="l03534"></a>03534 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l03535"></a>03535 <span class="keyword">struct </span>DECFIL_tag {
|
||
<a name="l03536"></a>03536 <span class="keyword">union </span>{
|
||
<a name="l03537"></a>03537 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03538"></a>03538 <span class="keyword">struct </span>{
|
||
<a name="l03539"></a>03539 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MDIS:1;
|
||
<a name="l03540"></a>03540 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> FREN:1;
|
||
<a name="l03541"></a>03541 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1;
|
||
<a name="l03542"></a>03542 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> FRZ:1;
|
||
<a name="l03543"></a>03543 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SRES:1;
|
||
<a name="l03544"></a>03544 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:2; <span class="comment">/* CASCD not supported in MPC563xM */</span>
|
||
<a name="l03545"></a>03545 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IDEN:1;
|
||
<a name="l03546"></a>03546 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ODEN:1;
|
||
<a name="l03547"></a>03547 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ERREN:1;
|
||
<a name="l03548"></a>03548 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1;
|
||
<a name="l03549"></a>03549 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> FTYPE:2;
|
||
<a name="l03550"></a>03550 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1;
|
||
<a name="l03551"></a>03551 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SCAL:2;
|
||
<a name="l03552"></a>03552 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1;
|
||
<a name="l03553"></a>03553 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SAT:1;
|
||
<a name="l03554"></a>03554 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ISEL:1;
|
||
<a name="l03555"></a>03555 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* MIXM does not appear to be implemented on the MPC563xM */</span>
|
||
<a name="l03556"></a>03556 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DEC_RATE:4;
|
||
<a name="l03557"></a>03557 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1; <span class="comment">/* SDIE not supported in MPC563xM */</span>
|
||
<a name="l03558"></a>03558 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DSEL:1;
|
||
<a name="l03559"></a>03559 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IBIE:1;
|
||
<a name="l03560"></a>03560 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OBIE:1;
|
||
<a name="l03561"></a>03561 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> EDME:1;
|
||
<a name="l03562"></a>03562 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TORE:1;
|
||
<a name="l03563"></a>03563 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TMODE:2; <span class="comment">/* the LSB of TMODE is always 0 on the MPC563xM */</span>
|
||
<a name="l03564"></a>03564 } B;
|
||
<a name="l03565"></a>03565 } MCR; <span class="comment">/* Configuration Register <URM>DECFILTER_MCR</URM> @baseaddress + 0x00 */</span>
|
||
<a name="l03566"></a>03566
|
||
<a name="l03567"></a>03567 <span class="keyword">union </span>{
|
||
<a name="l03568"></a>03568 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03569"></a>03569 <span class="keyword">struct </span>{
|
||
<a name="l03570"></a>03570 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BSY:1;
|
||
<a name="l03571"></a>03571 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1;
|
||
<a name="l03572"></a>03572 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DEC_COUNTER:4;
|
||
<a name="l03573"></a>03573 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IDFC:1;
|
||
<a name="l03574"></a>03574 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ODFC:1;
|
||
<a name="l03575"></a>03575 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SDFC:1; <span class="comment">/* SDFC not supported in MPC563xM */</span>
|
||
<a name="l03576"></a>03576 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IBIC:1;
|
||
<a name="l03577"></a>03577 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OBIC:1;
|
||
<a name="l03578"></a>03578 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SVRC:1; <span class="comment">/* SVRC not supported in MPC563xM */</span>
|
||
<a name="l03579"></a>03579 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DIVRC:1;
|
||
<a name="l03580"></a>03580 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OVFC:1;
|
||
<a name="l03581"></a>03581 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OVRC:1;
|
||
<a name="l03582"></a>03582 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IVRC:1;
|
||
<a name="l03583"></a>03583 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:6;
|
||
<a name="l03584"></a>03584 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IDF:1;
|
||
<a name="l03585"></a>03585 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ODF:1;
|
||
<a name="l03586"></a>03586 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SDF:1; <span class="comment">/* SDF not supported in MPC563xM */</span>
|
||
<a name="l03587"></a>03587 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IBIF:1;
|
||
<a name="l03588"></a>03588 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OBIF:1;
|
||
<a name="l03589"></a>03589 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SVR:1; <span class="comment">/* SVR not supported in MPC563xM */</span>
|
||
<a name="l03590"></a>03590 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> DIVR:1;
|
||
<a name="l03591"></a>03591 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OVF:1;
|
||
<a name="l03592"></a>03592 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OVR:1;
|
||
<a name="l03593"></a>03593 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> IVR:1;
|
||
<a name="l03594"></a>03594 } B;
|
||
<a name="l03595"></a>03595 } MSR; <span class="comment">/* Status Register <URM>DECFILTER_MSR</URM> @baseaddress + 0x04 */</span>
|
||
<a name="l03596"></a>03596
|
||
<a name="l03597"></a>03597 <span class="comment">/* Module Extended Config.Register - not siupported on the MPC563xM <URM>DECFILTER_MXCR</URM> @baseaddress + 0x08 */</span>
|
||
<a name="l03598"></a>03598
|
||
<a name="l03599"></a>03599 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> decfil_reserved1[2];
|
||
<a name="l03600"></a>03600
|
||
<a name="l03601"></a>03601 <span class="keyword">union </span>{
|
||
<a name="l03602"></a>03602 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03603"></a>03603 <span class="keyword">struct </span>{
|
||
<a name="l03604"></a>03604 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:4;
|
||
<a name="l03605"></a>03605 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> INTAG:4;
|
||
<a name="l03606"></a>03606 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:6;
|
||
<a name="l03607"></a>03607 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> PREFILL:1;
|
||
<a name="l03608"></a>03608 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> FLUSH:1;
|
||
<a name="l03609"></a>03609 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> INPBUF:16;
|
||
<a name="l03610"></a>03610 } B;
|
||
<a name="l03611"></a>03611 } IB; <span class="comment">/* Interface Input Buffer <URM>DECFILTER_IB</URM> @baseaddress + 0x10 */</span>
|
||
<a name="l03612"></a>03612
|
||
<a name="l03613"></a>03613 <span class="keyword">union </span>{
|
||
<a name="l03614"></a>03614 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03615"></a>03615 <span class="keyword">struct </span>{
|
||
<a name="l03616"></a>03616 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:12;
|
||
<a name="l03617"></a>03617 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OUTTAG:4;
|
||
<a name="l03618"></a>03618 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> OUTBUF:16;
|
||
<a name="l03619"></a>03619 } B;
|
||
<a name="l03620"></a>03620 } OB; <span class="comment">/* Interface Output Buffer <URM>DECFILTER_OB</URM> @baseaddress + 0x14 */</span>
|
||
<a name="l03621"></a>03621
|
||
<a name="l03622"></a>03622 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> decfil_reserved2[2];
|
||
<a name="l03623"></a>03623
|
||
<a name="l03624"></a>03624 <span class="keyword">union </span>{
|
||
<a name="l03625"></a>03625 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03626"></a>03626 <span class="keyword">struct </span>{
|
||
<a name="l03627"></a>03627 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:8;
|
||
<a name="l03628"></a>03628 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> COEF:24;
|
||
<a name="l03629"></a>03629 } B;
|
||
<a name="l03630"></a>03630 } COEF[9]; <span class="comment">/* Filter Coefficient Registers <URM>DECFILTER_COEFx</URM> @baseaddress + 0x20 - 0x40 */</span>
|
||
<a name="l03631"></a>03631
|
||
<a name="l03632"></a>03632 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> decfil_reserved3[13];
|
||
<a name="l03633"></a>03633
|
||
<a name="l03634"></a>03634 <span class="keyword">union </span>{
|
||
<a name="l03635"></a>03635 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03636"></a>03636 <span class="keyword">struct </span>{
|
||
<a name="l03637"></a>03637 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:8;
|
||
<a name="l03638"></a>03638 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TAP:24;
|
||
<a name="l03639"></a>03639 } B;
|
||
<a name="l03640"></a>03640 } TAP[8]; <span class="comment">/* Filter TAP Registers <URM>DECFILTER_TAPx</URM> @baseaddress + 0x78 - 0x94 */</span>
|
||
<a name="l03641"></a>03641
|
||
<a name="l03642"></a>03642 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> decfil_reserved4[14];
|
||
<a name="l03643"></a>03643
|
||
<a name="l03644"></a>03644 <span class="comment">/* 0x0D0 */</span>
|
||
<a name="l03645"></a>03645 <span class="keyword">union </span>{
|
||
<a name="l03646"></a>03646 <a class="code" href="group___p_p_c___c_o_r_e.html#ga90521f687dbd4c8eec49c259b253527a">vuint16_t</a> R;
|
||
<a name="l03647"></a>03647 <span class="keyword">struct </span>{
|
||
<a name="l03648"></a>03648 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:16;
|
||
<a name="l03649"></a>03649 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SAMP_DATA:16;
|
||
<a name="l03650"></a>03650 } B;
|
||
<a name="l03651"></a>03651 } EDID; <span class="comment">/* Filter EDID Registers <URM>DECFILTER_EDID</URM> @baseaddress + 0xD0 */</span>
|
||
<a name="l03652"></a>03652
|
||
<a name="l03653"></a>03653 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> decfil_reserved5[3];
|
||
<a name="l03654"></a>03654
|
||
<a name="l03655"></a>03655 <span class="comment">/* 0x0E0 */</span>
|
||
<a name="l03656"></a>03656 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> decfil_reserved6;
|
||
<a name="l03657"></a>03657 <span class="comment">/* Filter FINTVAL Registers - Not supported on MPC563xM <URM>DECFILTER_FINTVAL</URM> @baseaddress + 0xE0 */</span>
|
||
<a name="l03658"></a>03658
|
||
<a name="l03659"></a>03659 <span class="comment">/* 0x0E4 */</span>
|
||
<a name="l03660"></a>03660 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> decfil_reserved7;
|
||
<a name="l03661"></a>03661 <span class="comment">/* Filter FINTCNT Registers - Not supported on MPC563xM <URM>DECFILTER_FINTCNT</URM> @baseaddress + 0xE4 */</span>
|
||
<a name="l03662"></a>03662
|
||
<a name="l03663"></a>03663 <span class="comment">/* 0x0E8 */</span>
|
||
<a name="l03664"></a>03664 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> decfil_reserved8;
|
||
<a name="l03665"></a>03665 <span class="comment">/* Filter CINTVAL Registers - Not supported on MPC563xM <URM>DECFILTER_CINTVAL</URM> @baseaddress + 0xE8 */</span>
|
||
<a name="l03666"></a>03666
|
||
<a name="l03667"></a>03667 <span class="comment">/* 0x0EC */</span>
|
||
<a name="l03668"></a>03668 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> decfil_reserved9;
|
||
<a name="l03669"></a>03669 <span class="comment">/* Filter CINTCNT Registers - Not supported on MPC563xM <URM>DECFILTER_CINTCNT</URM> @baseaddress + 0xEC */</span>
|
||
<a name="l03670"></a>03670
|
||
<a name="l03671"></a>03671 };
|
||
<a name="l03672"></a>03672 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l03673"></a>03673 <span class="comment">/* MODULE : Periodic Interval Timer (PIT) */</span>
|
||
<a name="l03674"></a>03674 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l03675"></a>03675 <span class="keyword">struct </span>PIT_tag {
|
||
<a name="l03676"></a>03676
|
||
<a name="l03677"></a>03677 <span class="keyword">union </span>{
|
||
<a name="l03678"></a>03678 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03679"></a>03679 <span class="keyword">struct </span>{
|
||
<a name="l03680"></a>03680 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:29;
|
||
<a name="l03681"></a>03681 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MDIS_RTI:1;
|
||
<a name="l03682"></a>03682 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MDIS:1;
|
||
<a name="l03683"></a>03683 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> FRZ:1;
|
||
<a name="l03684"></a>03684 } B;
|
||
<a name="l03685"></a>03685 } PITMCR; <span class="comment">/* PIT Module Control Register */</span>
|
||
<a name="l03686"></a>03686
|
||
<a name="l03687"></a>03687 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> pit_reserved1[59];
|
||
<a name="l03688"></a>03688
|
||
<a name="l03689"></a>03689 <span class="keyword">struct </span>{
|
||
<a name="l03690"></a>03690 <span class="keyword">union </span>{
|
||
<a name="l03691"></a>03691 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R; <span class="comment">/* <URM>TSVn</URM> */</span>
|
||
<a name="l03692"></a>03692 } LDVAL; <span class="comment">/* Timer Load Value Register */</span>
|
||
<a name="l03693"></a>03693
|
||
<a name="l03694"></a>03694 <span class="keyword">union </span>{
|
||
<a name="l03695"></a>03695 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R; <span class="comment">/* <URM>TVLn</URM> */</span>
|
||
<a name="l03696"></a>03696 } CVAL; <span class="comment">/* Current Timer Value Register */</span>
|
||
<a name="l03697"></a>03697
|
||
<a name="l03698"></a>03698 <span class="keyword">union </span>{
|
||
<a name="l03699"></a>03699 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03700"></a>03700 <span class="keyword">struct </span>{
|
||
<a name="l03701"></a>03701 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:30;
|
||
<a name="l03702"></a>03702 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TIE:1;
|
||
<a name="l03703"></a>03703 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TEN:1;
|
||
<a name="l03704"></a>03704 } B;
|
||
<a name="l03705"></a>03705 } TCTRL; <span class="comment">/* Timer Control Register */</span>
|
||
<a name="l03706"></a>03706
|
||
<a name="l03707"></a>03707 <span class="keyword">union </span>{
|
||
<a name="l03708"></a>03708 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03709"></a>03709 <span class="keyword">struct </span>{
|
||
<a name="l03710"></a>03710 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:31;
|
||
<a name="l03711"></a>03711 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TIF:1;
|
||
<a name="l03712"></a>03712 } B;
|
||
<a name="l03713"></a>03713 } TFLG; <span class="comment">/* Timer Flag Register */</span>
|
||
<a name="l03714"></a>03714 } RTI; <span class="comment">/* RTI Channel */</span>
|
||
<a name="l03715"></a>03715
|
||
<a name="l03716"></a>03716 <span class="keyword">struct </span>{
|
||
<a name="l03717"></a>03717 <span class="keyword">union </span>{
|
||
<a name="l03718"></a>03718 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03719"></a>03719 } LDVAL; <span class="comment">/* Timer Load Value Register */</span>
|
||
<a name="l03720"></a>03720
|
||
<a name="l03721"></a>03721 <span class="keyword">union </span>{
|
||
<a name="l03722"></a>03722 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03723"></a>03723 } CVAL; <span class="comment">/* Current Timer Value Register */</span>
|
||
<a name="l03724"></a>03724
|
||
<a name="l03725"></a>03725 <span class="keyword">union </span>{
|
||
<a name="l03726"></a>03726 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03727"></a>03727 <span class="keyword">struct </span>{
|
||
<a name="l03728"></a>03728 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:30;
|
||
<a name="l03729"></a>03729 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TIE:1;
|
||
<a name="l03730"></a>03730 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TEN:1;
|
||
<a name="l03731"></a>03731 } B;
|
||
<a name="l03732"></a>03732 } TCTRL; <span class="comment">/* Timer Control Register */</span>
|
||
<a name="l03733"></a>03733
|
||
<a name="l03734"></a>03734 <span class="keyword">union </span>{
|
||
<a name="l03735"></a>03735 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03736"></a>03736 <span class="keyword">struct </span>{
|
||
<a name="l03737"></a>03737 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:31;
|
||
<a name="l03738"></a>03738 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TIF:1;
|
||
<a name="l03739"></a>03739 } B;
|
||
<a name="l03740"></a>03740 } TFLG; <span class="comment">/* Timer Flag Register */</span>
|
||
<a name="l03741"></a>03741 } TIMER[4]; <span class="comment">/* Timer Channels */</span>
|
||
<a name="l03742"></a>03742
|
||
<a name="l03743"></a>03743 };
|
||
<a name="l03744"></a>03744 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l03745"></a>03745 <span class="comment">/* MODULE : System Timer Module (STM) */</span>
|
||
<a name="l03746"></a>03746 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l03747"></a>03747 <span class="keyword">struct </span>STM_tag {
|
||
<a name="l03748"></a>03748 <span class="keyword">union </span>{
|
||
<a name="l03749"></a>03749 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03750"></a>03750 <span class="keyword">struct </span>{
|
||
<a name="l03751"></a>03751 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:16;
|
||
<a name="l03752"></a>03752 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CPS:8;
|
||
<a name="l03753"></a>03753 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:6;
|
||
<a name="l03754"></a>03754 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> FRZ:1;
|
||
<a name="l03755"></a>03755 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TEN:1;
|
||
<a name="l03756"></a>03756 } B;
|
||
<a name="l03757"></a>03757 } CR; <span class="comment">/* STM Control Register <URM>STM_CR</URM> (new in MPC563xM) Offset 0x0000 */</span>
|
||
<a name="l03758"></a>03758
|
||
<a name="l03759"></a>03759 <span class="keyword">union </span>{
|
||
<a name="l03760"></a>03760 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03761"></a>03761 } CNT; <span class="comment">/* STM Count Register <URM>STM_CNT</URM> (new in MPC563xM) Offset Offset 0x0004 */</span>
|
||
<a name="l03762"></a>03762
|
||
<a name="l03763"></a>03763 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> stm_reserved1[2]; <span class="comment">/* Reserved (new in MPC563xM) Offset Offset 0x0008 */</span>
|
||
<a name="l03764"></a>03764
|
||
<a name="l03765"></a>03765 <span class="keyword">union </span>{
|
||
<a name="l03766"></a>03766 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03767"></a>03767 <span class="keyword">struct </span>{
|
||
<a name="l03768"></a>03768 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:31;
|
||
<a name="l03769"></a>03769 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CEN:1;
|
||
<a name="l03770"></a>03770 } B;
|
||
<a name="l03771"></a>03771 } CCR0; <span class="comment">/* STM Channel Control Register <URM>STM_CCR0</URM> (new in MPC563xM) Offset 0x0010 */</span>
|
||
<a name="l03772"></a>03772
|
||
<a name="l03773"></a>03773 <span class="keyword">union </span>{
|
||
<a name="l03774"></a>03774 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03775"></a>03775 <span class="keyword">struct </span>{
|
||
<a name="l03776"></a>03776 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:31;
|
||
<a name="l03777"></a>03777 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIF:1;
|
||
<a name="l03778"></a>03778 } B;
|
||
<a name="l03779"></a>03779 } CIR0; <span class="comment">/* STM Channel Interrupt Register <URM>STM_CIR0</URM> (new in MPC563xM) Offset 0x0014 */</span>
|
||
<a name="l03780"></a>03780
|
||
<a name="l03781"></a>03781 <span class="keyword">union </span>{
|
||
<a name="l03782"></a>03782 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03783"></a>03783 } CMP0; <span class="comment">/* STM Channel Compare Register <URM>STM_CMP0</URM> (new in MPC563xM) Offset Offset 0x0018 */</span>
|
||
<a name="l03784"></a>03784
|
||
<a name="l03785"></a>03785 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> stm_reserved2; <span class="comment">/* Reserved (new in MPC563xM) Offset Offset 0x001C */</span>
|
||
<a name="l03786"></a>03786
|
||
<a name="l03787"></a>03787 <span class="keyword">union </span>{
|
||
<a name="l03788"></a>03788 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03789"></a>03789 <span class="keyword">struct </span>{
|
||
<a name="l03790"></a>03790 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:31;
|
||
<a name="l03791"></a>03791 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CEN:1;
|
||
<a name="l03792"></a>03792 } B;
|
||
<a name="l03793"></a>03793 } CCR1; <span class="comment">/* STM Channel Control Register <URM>STM_CCR1</URM> (new in MPC563xM) Offset 0x0020 */</span>
|
||
<a name="l03794"></a>03794
|
||
<a name="l03795"></a>03795 <span class="keyword">union </span>{
|
||
<a name="l03796"></a>03796 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03797"></a>03797 <span class="keyword">struct </span>{
|
||
<a name="l03798"></a>03798 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:31;
|
||
<a name="l03799"></a>03799 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIF:1;
|
||
<a name="l03800"></a>03800 } B;
|
||
<a name="l03801"></a>03801 } CIR1; <span class="comment">/* STM Channel Interrupt Register <URM>STM_CIR1</URM> (new in MPC563xM) Offset 0x0024 */</span>
|
||
<a name="l03802"></a>03802
|
||
<a name="l03803"></a>03803 <span class="keyword">union </span>{
|
||
<a name="l03804"></a>03804 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03805"></a>03805 } CMP1; <span class="comment">/* STM Channel Compare Register <URM>STM_CMP1</URM> (new in MPC563xM) Offset Offset 0x0028 */</span>
|
||
<a name="l03806"></a>03806
|
||
<a name="l03807"></a>03807 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> stm_reserved3; <span class="comment">/* Reserved (new in MPC563xM) Offset Offset 0x002C */</span>
|
||
<a name="l03808"></a>03808
|
||
<a name="l03809"></a>03809 <span class="keyword">union </span>{
|
||
<a name="l03810"></a>03810 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03811"></a>03811 <span class="keyword">struct </span>{
|
||
<a name="l03812"></a>03812 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:31;
|
||
<a name="l03813"></a>03813 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CEN:1;
|
||
<a name="l03814"></a>03814 } B;
|
||
<a name="l03815"></a>03815 } CCR2; <span class="comment">/* STM Channel Control Register <URM>STM_CCR2</URM> (new in MPC563xM) Offset 0x0030 */</span>
|
||
<a name="l03816"></a>03816
|
||
<a name="l03817"></a>03817 <span class="keyword">union </span>{
|
||
<a name="l03818"></a>03818 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03819"></a>03819 <span class="keyword">struct </span>{
|
||
<a name="l03820"></a>03820 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:31;
|
||
<a name="l03821"></a>03821 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIF:1;
|
||
<a name="l03822"></a>03822 } B;
|
||
<a name="l03823"></a>03823 } CIR2; <span class="comment">/* STM Channel Interrupt Register <URM>STM_CIR2</URM> (new in MPC563xM) Offset 0x0034 */</span>
|
||
<a name="l03824"></a>03824
|
||
<a name="l03825"></a>03825 <span class="keyword">union </span>{
|
||
<a name="l03826"></a>03826 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03827"></a>03827 } CMP2; <span class="comment">/* STM Channel Compare Register <URM>STM_CMP2</URM> (new in MPC563xM) Offset Offset 0x0038 */</span>
|
||
<a name="l03828"></a>03828
|
||
<a name="l03829"></a>03829 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> stm_reserved4; <span class="comment">/* Reserved (new in MPC563xM) Offset Offset 0x003C */</span>
|
||
<a name="l03830"></a>03830
|
||
<a name="l03831"></a>03831 <span class="keyword">union </span>{
|
||
<a name="l03832"></a>03832 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03833"></a>03833 <span class="keyword">struct </span>{
|
||
<a name="l03834"></a>03834 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:31;
|
||
<a name="l03835"></a>03835 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CEN:1;
|
||
<a name="l03836"></a>03836 } B;
|
||
<a name="l03837"></a>03837 } CCR3; <span class="comment">/* STM Channel Control Register <URM>STM_CCR3</URM> (new in MPC563xM) Offset 0x0040 */</span>
|
||
<a name="l03838"></a>03838
|
||
<a name="l03839"></a>03839 <span class="keyword">union </span>{
|
||
<a name="l03840"></a>03840 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03841"></a>03841 <span class="keyword">struct </span>{
|
||
<a name="l03842"></a>03842 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:31;
|
||
<a name="l03843"></a>03843 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CIF:1;
|
||
<a name="l03844"></a>03844 } B;
|
||
<a name="l03845"></a>03845 } CIR3; <span class="comment">/* STM Channel Interrupt Register <URM>STM_CIR3</URM> (new in MPC563xM) Offset 0x0044 */</span>
|
||
<a name="l03846"></a>03846
|
||
<a name="l03847"></a>03847 <span class="keyword">union </span>{
|
||
<a name="l03848"></a>03848 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03849"></a>03849 } CMP3; <span class="comment">/* STM Channel Compare Register <URM>STM_CMP3</URM> (new in MPC563xM) Offset Offset 0x0048 */</span>
|
||
<a name="l03850"></a>03850
|
||
<a name="l03851"></a>03851 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> stm_reserved5; <span class="comment">/* Reserved (new in MPC563xM) Offset Offset 0x004C */</span>
|
||
<a name="l03852"></a>03852 };
|
||
<a name="l03853"></a>03853
|
||
<a name="l03854"></a>03854 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l03855"></a>03855 <span class="comment">/* MODULE : SWT */</span>
|
||
<a name="l03856"></a>03856 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l03857"></a>03857
|
||
<a name="l03858"></a>03858 <span class="keyword">struct </span>SWT_tag {
|
||
<a name="l03859"></a>03859 <span class="keyword">union </span>{
|
||
<a name="l03860"></a>03860 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03861"></a>03861 <span class="keyword">struct </span>{
|
||
<a name="l03862"></a>03862 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MAP0:1;
|
||
<a name="l03863"></a>03863 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MAP1:1;
|
||
<a name="l03864"></a>03864 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MAP2:1;
|
||
<a name="l03865"></a>03865 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MAP3:1;
|
||
<a name="l03866"></a>03866 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MAP4:1;
|
||
<a name="l03867"></a>03867 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MAP5:1;
|
||
<a name="l03868"></a>03868 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MAP6:1;
|
||
<a name="l03869"></a>03869 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> MAP7:1;
|
||
<a name="l03870"></a>03870 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:14;
|
||
<a name="l03871"></a>03871 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> KEY:1;
|
||
<a name="l03872"></a>03872 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> RIA:1;
|
||
<a name="l03873"></a>03873 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WND:1;
|
||
<a name="l03874"></a>03874 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> ITR:1;
|
||
<a name="l03875"></a>03875 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> HLK:1;
|
||
<a name="l03876"></a>03876 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SLK:1;
|
||
<a name="l03877"></a>03877 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CSL:1;
|
||
<a name="l03878"></a>03878 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> STP:1;
|
||
<a name="l03879"></a>03879 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> FRZ:1;
|
||
<a name="l03880"></a>03880 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WEN:1;
|
||
<a name="l03881"></a>03881 } B;
|
||
<a name="l03882"></a>03882 } MCR; <span class="comment">/*<URM>SWT_CR</URM> */</span><span class="comment">/* Module Configuration Register */</span>
|
||
<a name="l03883"></a>03883
|
||
<a name="l03884"></a>03884 <span class="keyword">union </span>{
|
||
<a name="l03885"></a>03885 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03886"></a>03886 <span class="keyword">struct </span>{
|
||
<a name="l03887"></a>03887 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:31;
|
||
<a name="l03888"></a>03888 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TIF:1;
|
||
<a name="l03889"></a>03889 } B;
|
||
<a name="l03890"></a>03890 } IR; <span class="comment">/* Interrupt register <URM>SWT_IR</URM> */</span>
|
||
<a name="l03891"></a>03891
|
||
<a name="l03892"></a>03892 <span class="keyword">union </span>{
|
||
<a name="l03893"></a>03893 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03894"></a>03894 <span class="keyword">struct </span>{
|
||
<a name="l03895"></a>03895 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WTO:32;
|
||
<a name="l03896"></a>03896 } B;
|
||
<a name="l03897"></a>03897 } TO; <span class="comment">/* Timeout register <URM>SWT_TO</URM> */</span>
|
||
<a name="l03898"></a>03898
|
||
<a name="l03899"></a>03899 <span class="keyword">union </span>{
|
||
<a name="l03900"></a>03900 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03901"></a>03901 <span class="keyword">struct </span>{
|
||
<a name="l03902"></a>03902 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WST:32;
|
||
<a name="l03903"></a>03903
|
||
<a name="l03904"></a>03904 } B;
|
||
<a name="l03905"></a>03905 } WN; <span class="comment">/* Window register <URM>SWT_WN</URM> */</span>
|
||
<a name="l03906"></a>03906
|
||
<a name="l03907"></a>03907 <span class="keyword">union </span>{
|
||
<a name="l03908"></a>03908 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03909"></a>03909 <span class="keyword">struct </span>{
|
||
<a name="l03910"></a>03910 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:16;
|
||
<a name="l03911"></a>03911 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> WSC:16;
|
||
<a name="l03912"></a>03912 } B;
|
||
<a name="l03913"></a>03913 } SR; <span class="comment">/* Service register <URM>SWT_SR</URM> */</span>
|
||
<a name="l03914"></a>03914
|
||
<a name="l03915"></a>03915 <span class="keyword">union </span>{
|
||
<a name="l03916"></a>03916 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03917"></a>03917 <span class="keyword">struct </span>{
|
||
<a name="l03918"></a>03918 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> CNT:32;
|
||
<a name="l03919"></a>03919 } B;
|
||
<a name="l03920"></a>03920 } CO; <span class="comment">/* Counter output register <URM>SWT_CO</URM> */</span>
|
||
<a name="l03921"></a>03921
|
||
<a name="l03922"></a>03922 <span class="keyword">union </span>{
|
||
<a name="l03923"></a>03923 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03924"></a>03924 <span class="keyword">struct </span>{
|
||
<a name="l03925"></a>03925 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:16;
|
||
<a name="l03926"></a>03926 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> SK:16;
|
||
<a name="l03927"></a>03927 } B;
|
||
<a name="l03928"></a>03928 } SK; <span class="comment">/* Service key register <URM>SWT_SK</URM> */</span>
|
||
<a name="l03929"></a>03929 };
|
||
<a name="l03930"></a>03930 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l03931"></a>03931 <span class="comment">/* MODULE : Power Management Controller (PMC) */</span>
|
||
<a name="l03932"></a>03932 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l03933"></a>03933 <span class="keyword">struct </span>PMC_tag {
|
||
<a name="l03934"></a>03934 <span class="keyword">union </span>{
|
||
<a name="l03935"></a>03935 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03936"></a>03936 <span class="keyword">struct </span>{
|
||
<a name="l03937"></a>03937 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LVRER:1; <span class="comment">/* <URM> LVIRR </URM> */</span>
|
||
<a name="l03938"></a>03938 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LVREH:1; <span class="comment">/* <URM> LVIHR </URM> */</span>
|
||
<a name="l03939"></a>03939 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LVRE50:1; <span class="comment">/* <URM> LVI5R </URM> */</span>
|
||
<a name="l03940"></a>03940 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LVRE33:1; <span class="comment">/* <URM> LVI3R </URM> */</span>
|
||
<a name="l03941"></a>03941 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LVREC:1; <span class="comment">/* <URM> LVI1R </URM> */</span>
|
||
<a name="l03942"></a>03942 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:3;
|
||
<a name="l03943"></a>03943 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LVIER:1; <span class="comment">/* <URM> LVIRE </URM> */</span>
|
||
<a name="l03944"></a>03944 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LVIEH:1; <span class="comment">/* <URM> LVIHE </URM> */</span>
|
||
<a name="l03945"></a>03945 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LVIE50:1; <span class="comment">/* <URM> LVI5E </URM> */</span>
|
||
<a name="l03946"></a>03946 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LVIE33:1; <span class="comment">/* <URM> LVI3E </URM> */</span>
|
||
<a name="l03947"></a>03947 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LVIC:1; <span class="comment">/* <URM> LVI1E </URM> */</span>
|
||
<a name="l03948"></a>03948 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:2;
|
||
<a name="l03949"></a>03949 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TLK:1;
|
||
<a name="l03950"></a>03950 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:16;
|
||
<a name="l03951"></a>03951 } B;
|
||
<a name="l03952"></a>03952 } MCR; <span class="comment">/* Module Configuration register <URM> CFGR </URM> */</span>
|
||
<a name="l03953"></a>03953
|
||
<a name="l03954"></a>03954 <span class="keyword">union </span>{
|
||
<a name="l03955"></a>03955 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03956"></a>03956 <span class="keyword">struct </span>{
|
||
<a name="l03957"></a>03957 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:12;
|
||
<a name="l03958"></a>03958 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LVDREGTRIM:4; <span class="comment">/* <URM> LVI50TRIM </URM> */</span>
|
||
<a name="l03959"></a>03959 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> VDD33TRIM:4; <span class="comment">/* <URM> BV33TRIM </URM> */</span>
|
||
<a name="l03960"></a>03960 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LVD33TRIM:4; <span class="comment">/* <URM> LVI33TRIM </URM> */</span>
|
||
<a name="l03961"></a>03961 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> VDDCTRIM:4; <span class="comment">/* <URM> V12TRIM </URM> */</span>
|
||
<a name="l03962"></a>03962 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LVDCTRIM:4; <span class="comment">/* <URM> LVI33TRIM </URM> */</span>
|
||
<a name="l03963"></a>03963 } B;
|
||
<a name="l03964"></a>03964 } TRIMR; <span class="comment">/* Trimming register */</span>
|
||
<a name="l03965"></a>03965
|
||
<a name="l03966"></a>03966 <span class="keyword">union </span>{
|
||
<a name="l03967"></a>03967 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l03968"></a>03968 <span class="keyword">struct </span>{
|
||
<a name="l03969"></a>03969 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:5;
|
||
<a name="l03970"></a>03970 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LVFVSTBY:1;
|
||
<a name="l03971"></a>03971 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BGRDY:1; <span class="comment">/* <URM> BGS1 </URM> */</span>
|
||
<a name="l03972"></a>03972 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> BGTS:1; <span class="comment">/* <URM> BGS2 </URM> */</span>
|
||
<a name="l03973"></a>03973 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:5;
|
||
<a name="l03974"></a>03974 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LVFCSTBY:1;
|
||
<a name="l03975"></a>03975 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:1;
|
||
<a name="l03976"></a>03976 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> V33DIS:1; <span class="comment">/* 3.3V Regulator Disable <URM> V33S </URM> */</span>
|
||
<a name="l03977"></a>03977 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LVFCR:1; <span class="comment">/* Clear LVFR <URM> LVIRC </URM> */</span>
|
||
<a name="l03978"></a>03978 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LVFCH:1; <span class="comment">/* Clear LVFH <URM> LVIHC </URM> */</span>
|
||
<a name="l03979"></a>03979 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LVFC50:1; <span class="comment">/* Clear LVF5 <URM> LVI5 </URM> */</span>
|
||
<a name="l03980"></a>03980 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LVFC33:1; <span class="comment">/* Clear LVF3 <URM> LVI3 </URM> */</span>
|
||
<a name="l03981"></a>03981 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LVFCC:1; <span class="comment">/* Clear LVFC <URM> LVI1 </URM> */</span>
|
||
<a name="l03982"></a>03982 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:3;
|
||
<a name="l03983"></a>03983 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LVFR:1; <span class="comment">/* Low Voltage Flag Reset Supply <URM> LVIRF </URM> */</span>
|
||
<a name="l03984"></a>03984 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LVFH:1; <span class="comment">/* Low Voltage Flag VDDEH Supply <URM> LVIHF </URM> */</span>
|
||
<a name="l03985"></a>03985 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LVF50:1; <span class="comment">/* Low Voltage Flag 5V Supply <URM> LVI5F </URM> */</span>
|
||
<a name="l03986"></a>03986 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LVF33:1; <span class="comment">/* Low Voltage Flag 3.3V Supply <URM> LVI3F </URM> */</span>
|
||
<a name="l03987"></a>03987 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> LVFC:1; <span class="comment">/* Low Voltage Flag Core (1.2V) <URM> LVI1F </URM> */</span>
|
||
<a name="l03988"></a>03988 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:3;
|
||
<a name="l03989"></a>03989
|
||
<a name="l03990"></a>03990 } B;
|
||
<a name="l03991"></a>03991 } SR; <span class="comment">/* status register */</span>
|
||
<a name="l03992"></a>03992 };
|
||
<a name="l03993"></a>03993 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l03994"></a>03994 <span class="comment">/* MODULE : TSENS (Temperature Sensor) */</span>
|
||
<a name="l03995"></a>03995 <span class="comment">/****************************************************************************/</span>
|
||
<a name="l03996"></a>03996
|
||
<a name="l03997"></a>03997 <span class="keyword">struct </span>TSENS_tag {
|
||
<a name="l03998"></a>03998
|
||
<a name="l03999"></a>03999 <span class="keyword">union </span>{
|
||
<a name="l04000"></a>04000 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l04001"></a>04001 <span class="keyword">struct </span>{
|
||
<a name="l04002"></a>04002 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TSCV2:16;
|
||
<a name="l04003"></a>04003 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TSCV1:16;
|
||
<a name="l04004"></a>04004 } B;
|
||
<a name="l04005"></a>04005 } TCCR0; <span class="comment">/* Temperature Sensor Calibration B @baseaddress + 0x00 */</span>
|
||
<a name="l04006"></a>04006
|
||
<a name="l04007"></a>04007 <span class="keyword">union </span>{
|
||
<a name="l04008"></a>04008 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> R;
|
||
<a name="l04009"></a>04009 <span class="keyword">struct </span>{
|
||
<a name="l04010"></a>04010 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a>:16;
|
||
<a name="l04011"></a>04011 <a class="code" href="group___p_p_c___c_o_r_e.html#gaa6eb327e1a47e374f46253e6eed88bf5">vuint32_t</a> TSCV3:16;
|
||
<a name="l04012"></a>04012 } B;
|
||
<a name="l04013"></a>04013 } TCCR1; <span class="comment">/* Temperature Sensor Calibration A @baseaddress + 0x04 */</span>
|
||
<a name="l04014"></a>04014
|
||
<a name="l04015"></a>04015 <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> TSENS_reserved0008[16382]; <span class="comment">/* 0x0008-0xFFFF */</span>
|
||
<a name="l04016"></a>04016
|
||
<a name="l04017"></a>04017 };
|
||
<a name="l04018"></a>04018
|
||
<a name="l04019"></a>04019 <span class="comment">/* Define memories */</span>
|
||
<a name="l04020"></a>04020 <span class="comment">/* Comments need to be moved for different memory sizes */</span>
|
||
<a name="l04021"></a>04021
|
||
<a name="l04022"></a>04022 <span class="preprocessor">#define SRAM_START 0x40000000</span>
|
||
<a name="l04023"></a>04023 <span class="preprocessor"></span> <span class="comment">/*#define SRAM_SIZE 0xC000 48K SRAM */</span>
|
||
<a name="l04024"></a>04024 <span class="comment">/*#define SRAM_SIZE 0x10000 64K SRAM */</span>
|
||
<a name="l04025"></a>04025 <span class="preprocessor">#define SRAM_SIZE 0x17800 </span><span class="comment">/* 94K SRAM */</span>
|
||
<a name="l04026"></a>04026 <span class="comment">/*#define SRAM_END 0x4000BFFF 48K SRAM */</span>
|
||
<a name="l04027"></a>04027 <span class="comment">/*#define SRAM_END 0x4000FFFF 64K SRAM */</span>
|
||
<a name="l04028"></a>04028 <span class="preprocessor">#define SRAM_END 0x400177FF </span><span class="comment">/* 94K SRAM */</span>
|
||
<a name="l04029"></a>04029
|
||
<a name="l04030"></a>04030 <span class="preprocessor">#define FLASH_START 0x0</span>
|
||
<a name="l04031"></a>04031 <span class="preprocessor"></span> <span class="comment">/*#define FLASH_SIZE 0x100000 1M Flash */</span>
|
||
<a name="l04032"></a>04032 <span class="preprocessor">#define FLASH_SIZE 0x180000 </span><span class="comment">/* 1.5M Flash */</span>
|
||
<a name="l04033"></a>04033 <span class="comment">/*#define FLASH_END 0xFFFFF 1M Flash */</span>
|
||
<a name="l04034"></a>04034 <span class="preprocessor">#define FLASH_END 0x17FFFF </span><span class="comment">/* 1.5M Flash */</span>
|
||
<a name="l04035"></a>04035
|
||
<a name="l04036"></a>04036 <span class="comment">/* Shadow Flash start and end address */</span>
|
||
<a name="l04037"></a>04037 <span class="preprocessor">#define FLASH_SHADOW_START 0x00FFC000 </span>
|
||
<a name="l04038"></a>04038 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_SHADOW_SIZE 0x4000</span>
|
||
<a name="l04039"></a>04039 <span class="preprocessor"></span><span class="preprocessor">#define FLASH_SHADOW_END 0x00FFFFFF</span>
|
||
<a name="l04040"></a>04040 <span class="preprocessor"></span>
|
||
<a name="l04041"></a>04041 <span class="comment">/* Define instances of modules */</span>
|
||
<a name="l04042"></a>04042 <span class="preprocessor">#define FMPLL (*( volatile struct FMPLL_tag *) 0xC3F80000)</span>
|
||
<a name="l04043"></a>04043 <span class="preprocessor"></span><span class="preprocessor">#define EBI (*( volatile struct EBI_tag *) 0xC3F84000)</span>
|
||
<a name="l04044"></a>04044 <span class="preprocessor"></span><span class="preprocessor">#define CFLASH0 (*( volatile struct FLASH_tag *) 0xC3F88000)</span>
|
||
<a name="l04045"></a>04045 <span class="preprocessor"></span><span class="preprocessor">#define CFLASH1 (*( volatile struct FLASH_tag *) 0xC3FB0000)</span>
|
||
<a name="l04046"></a>04046 <span class="preprocessor"></span><span class="preprocessor">#define CFLASH2 (*( volatile struct FLASH_tag *) 0xC3FB4000)</span>
|
||
<a name="l04047"></a>04047 <span class="preprocessor"></span><span class="preprocessor">#define SIU (*( volatile struct SIU_tag *) 0xC3F90000)</span>
|
||
<a name="l04048"></a>04048 <span class="preprocessor"></span>
|
||
<a name="l04049"></a>04049 <span class="preprocessor">#define EMIOS (*( volatile struct EMIOS_tag *) 0xC3FA0000)</span>
|
||
<a name="l04050"></a>04050 <span class="preprocessor"></span><span class="preprocessor">#define PMC (*( volatile struct PMC_tag *) 0xC3FBC000)</span>
|
||
<a name="l04051"></a>04051 <span class="preprocessor"></span><span class="preprocessor">#define ETPU (*( volatile struct ETPU_tag *) 0xC3FC0000)</span>
|
||
<a name="l04052"></a>04052 <span class="preprocessor"></span><span class="preprocessor">#define ETPU_DATA_RAM (*( uint32_t *) 0xC3FC8000)</span>
|
||
<a name="l04053"></a>04053 <span class="preprocessor"></span><span class="preprocessor">#define ETPU_DATA_RAM_EXT (*( uint32_t *) 0xC3FCC000)</span>
|
||
<a name="l04054"></a>04054 <span class="preprocessor"></span><span class="preprocessor">#define ETPU_DATA_RAM_END 0xC3FC8BFC</span>
|
||
<a name="l04055"></a>04055 <span class="preprocessor"></span><span class="preprocessor">#define CODE_RAM (*( uint32_t *) 0xC3FD0000)</span>
|
||
<a name="l04056"></a>04056 <span class="preprocessor"></span><span class="preprocessor">#define ETPU_CODE_RAM (*( uint32_t *) 0xC3FD0000)</span>
|
||
<a name="l04057"></a>04057 <span class="preprocessor"></span><span class="preprocessor">#define PIT (*( volatile struct PIT_tag *) 0xC3FF0000)</span>
|
||
<a name="l04058"></a>04058 <span class="preprocessor"></span>
|
||
<a name="l04059"></a>04059 <span class="preprocessor">#define XBAR (*( volatile struct XBAR_tag *) 0xFFF04000)</span>
|
||
<a name="l04060"></a>04060 <span class="preprocessor"></span><span class="preprocessor">#define SWT (*( volatile struct SWT_tag *) 0xFFF38000)</span>
|
||
<a name="l04061"></a>04061 <span class="preprocessor"></span><span class="preprocessor">#define STM (*( volatile struct STM_tag *) 0xFFF3C000)</span>
|
||
<a name="l04062"></a>04062 <span class="preprocessor"></span><span class="preprocessor">#define ECSM (*( volatile struct ECSM_tag *) 0xFFF40000)</span>
|
||
<a name="l04063"></a>04063 <span class="preprocessor"></span><span class="preprocessor">#define EDMA (*( volatile struct EDMA_tag *) 0xFFF44000)</span>
|
||
<a name="l04064"></a>04064 <span class="preprocessor"></span><span class="preprocessor">#define INTC (*( volatile struct INTC_tag *) 0xFFF48000)</span>
|
||
<a name="l04065"></a>04065 <span class="preprocessor"></span>
|
||
<a name="l04066"></a>04066 <span class="preprocessor">#define EQADC (*( volatile struct EQADC_tag *) 0xFFF80000)</span>
|
||
<a name="l04067"></a>04067 <span class="preprocessor"></span><span class="preprocessor">#define DECFIL (*( volatile struct DECFIL_tag *) 0xFFF88000)</span>
|
||
<a name="l04068"></a>04068 <span class="preprocessor"></span>
|
||
<a name="l04069"></a>04069 <span class="preprocessor">#define DSPI_B (*( volatile struct DSPI_tag *) 0xFFF94000)</span>
|
||
<a name="l04070"></a>04070 <span class="preprocessor"></span><span class="preprocessor">#define DSPI_C (*( volatile struct DSPI_tag *) 0xFFF98000)</span>
|
||
<a name="l04071"></a>04071 <span class="preprocessor"></span>
|
||
<a name="l04072"></a>04072 <span class="preprocessor">#define ESCI_A (*( volatile struct ESCI_tag *) 0xFFFB0000)</span>
|
||
<a name="l04073"></a>04073 <span class="preprocessor"></span><span class="preprocessor">#define ESCI_A_12_13 (*( volatile struct ESCI_12_13_bit_tag *) 0xFFFB0006)</span>
|
||
<a name="l04074"></a>04074 <span class="preprocessor"></span><span class="preprocessor">#define ESCI_B (*( volatile struct ESCI_tag *) 0xFFFB4000)</span>
|
||
<a name="l04075"></a>04075 <span class="preprocessor"></span><span class="preprocessor">#define ESCI_B_12_13 (*( volatile struct ESCI_12_13_bit_tag *) 0xFFFB4006)</span>
|
||
<a name="l04076"></a>04076 <span class="preprocessor"></span>
|
||
<a name="l04077"></a>04077 <span class="preprocessor">#define CAN_A (*( volatile struct FLEXCAN2_tag *) 0xFFFC0000)</span>
|
||
<a name="l04078"></a>04078 <span class="preprocessor"></span><span class="preprocessor">#define CAN_C (*( volatile struct FLEXCAN2_tag *) 0xFFFC8000)</span>
|
||
<a name="l04079"></a>04079 <span class="preprocessor"></span>
|
||
<a name="l04080"></a>04080 <span class="preprocessor">#define TSENS (*( volatile struct TSENS_tag *) 0xFFFEC000)</span>
|
||
<a name="l04081"></a>04081 <span class="preprocessor"></span>
|
||
<a name="l04082"></a>04082 <span class="preprocessor">#ifdef __MWERKS__</span>
|
||
<a name="l04083"></a>04083 <span class="preprocessor"></span><span class="preprocessor">#pragma pop</span>
|
||
<a name="l04084"></a>04084 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/* </span>
|
||
<a name="l04085"></a>04085 <span class="comment"> */</span>
|
||
<a name="l04086"></a>04086
|
||
<a name="l04087"></a>04087 <span class="preprocessor">#ifdef __cplusplus</span>
|
||
<a name="l04088"></a>04088 <span class="preprocessor"></span>}
|
||
<a name="l04089"></a>04089 <span class="preprocessor">#endif </span><span class="comment">/* </span>
|
||
<a name="l04090"></a>04090 <span class="comment"> */</span>
|
||
<a name="l04091"></a>04091
|
||
<a name="l04092"></a>04092 <span class="preprocessor">#endif </span><span class="comment">/* ifdef _MPC563M_H */</span>
|
||
<a name="l04093"></a>04093 <span class="comment">/*********************************************************************</span>
|
||
<a name="l04094"></a>04094 <span class="comment"> *</span>
|
||
<a name="l04095"></a>04095 <span class="comment"> * Copyright:</span>
|
||
<a name="l04096"></a>04096 <span class="comment"> * Freescale Semiconductor, INC. All Rights Reserved.</span>
|
||
<a name="l04097"></a>04097 <span class="comment"> * You are hereby granted a copyright license to use, modify, and</span>
|
||
<a name="l04098"></a>04098 <span class="comment"> * distribute the SOFTWARE so long as this entire notice is</span>
|
||
<a name="l04099"></a>04099 <span class="comment"> * retained without alteration in any modified and/or redistributed</span>
|
||
<a name="l04100"></a>04100 <span class="comment"> * versions, and that such modified versions are clearly identified</span>
|
||
<a name="l04101"></a>04101 <span class="comment"> * as such. No licenses are granted by implication, estoppel or</span>
|
||
<a name="l04102"></a>04102 <span class="comment"> * otherwise under any patents or trademarks of Freescale</span>
|
||
<a name="l04103"></a>04103 <span class="comment"> * Semiconductor, Inc. This software is provided on an "AS IS"</span>
|
||
<a name="l04104"></a>04104 <span class="comment"> * basis and without warranty.</span>
|
||
<a name="l04105"></a>04105 <span class="comment"> *</span>
|
||
<a name="l04106"></a>04106 <span class="comment"> * To the maximum extent permitted by applicable law, Freescale</span>
|
||
<a name="l04107"></a>04107 <span class="comment"> * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,</span>
|
||
<a name="l04108"></a>04108 <span class="comment"> * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A</span>
|
||
<a name="l04109"></a>04109 <span class="comment"> * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH</span>
|
||
<a name="l04110"></a>04110 <span class="comment"> * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)</span>
|
||
<a name="l04111"></a>04111 <span class="comment"> * AND ANY ACCOMPANYING WRITTEN MATERIALS.</span>
|
||
<a name="l04112"></a>04112 <span class="comment"> *</span>
|
||
<a name="l04113"></a>04113 <span class="comment"> * To the maximum extent permitted by applicable law, IN NO EVENT</span>
|
||
<a name="l04114"></a>04114 <span class="comment"> * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER</span>
|
||
<a name="l04115"></a>04115 <span class="comment"> * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,</span>
|
||
<a name="l04116"></a>04116 <span class="comment"> * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER</span>
|
||
<a name="l04117"></a>04117 <span class="comment"> * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.</span>
|
||
<a name="l04118"></a>04118 <span class="comment"> *</span>
|
||
<a name="l04119"></a>04119 <span class="comment"> * Freescale Semiconductor assumes no responsibility for the</span>
|
||
<a name="l04120"></a>04120 <span class="comment"> * maintenance and support of this software</span>
|
||
<a name="l04121"></a>04121 <span class="comment"> *</span>
|
||
<a name="l04122"></a>04122 <span class="comment"> ********************************************************************/</span>
|
||
<a name="l04123"></a>04123
|
||
</pre></div></div>
|
||
<hr size="1"><address style="text-align: right;"><small>
|
||
Generated on Sun Jul 11 13:13:01 2010 for ChibiOS/RT by <a href="http://www.doxygen.org/index.html"><img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.6.3</small></address>
|
||
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|
||
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