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170 lines
4.3 KiB
ArmAsm
170 lines
4.3 KiB
ArmAsm
/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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---
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A special exception to the GPL can be applied should you wish to distribute
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a combined work that includes ChibiOS/RT, without being obliged to provide
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the source code for any proprietary components. See the file exception.txt
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for full details of how and when the exception can be applied.
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*/
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/**
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* @file ARMCMx/crt0.s
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* @brief Generic ARM Cortex-Mx startup file for ChibiOS/RT.
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*
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* @addtogroup ARMCMx_CORE
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* @{
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*/
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#include "cmparams.h"
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#if !defined(__DOXYGEN__)
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.set CONTROL_MODE_PRIVILEGED, 0
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.set CONTROL_MODE_UNPRIVILEGED, 1
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.set CONTROL_USE_MSP, 0
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.set CONTROL_USE_PSP, 2
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.text
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.balign 2
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.syntax unified
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.thumb
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/*
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* Reset handler.
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*/
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.thumb_func
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.global ResetHandler
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.weak ResetHandler
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ResetHandler:
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/*
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* Interrupts are globally masked initially.
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*/
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cpsid i
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/*
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* Stack pointers initialization.
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*/
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ldr r0, =__ram_end__
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ldr r1, =__main_stack_size__
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subs r0, r0, r1
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/*
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* Note that r0 is the main stack low boundary address and process
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* stack initial top address.
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*/
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msr PSP, r0
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/*
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* Early initialization phase, it is empty by default.
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*/
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bl hwinit0
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/*
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* Data initialization.
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* NOTE: It assumes that the DATA size is a multiple of 4.
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*/
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ldr r1, =_textdata
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ldr r2, =_data
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ldr r3, =_edata
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dloop:
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cmp r2, r3
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#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M1)
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bge enddloop
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ldr r0, [r1]
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str r0, [r2]
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adds r1, r1, #4
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adds r2, r2, #4
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b dloop
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enddloop:
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#else
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ittt lo
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ldrlo r0, [r1], #4
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strlo r0, [r2], #4
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blo dloop
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#endif
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/*
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* BSS initialization.
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* NOTE: It assumes that the BSS size is a multiple of 4.
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*/
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movs r0, #0
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ldr r1, =_bss_start
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ldr r2, =_bss_end
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bloop:
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cmp r1, r2
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#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M1)
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bge endbloop
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str r0, [r1]
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adds r1, r1, #4
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b bloop
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endbloop:
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#else
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itt lo
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strlo r0, [r1], #4
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blo bloop
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#endif
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/*
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* Switches to the Process Stack and uses a barrier just to be safe.
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*/
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movs r0, #CONTROL_MODE_PRIVILEGED | CONTROL_USE_PSP
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msr CONTROL, r0
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isb
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/*
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* Late initialization phase, it is empty by default.
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*/
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bl hwinit1
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movs r0, #0
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mov r1, r0
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bl main
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b MainExitHandler
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/*
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* Default main exit code, just a loop.
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* It is a weak symbol, the application code can redefine the behavior.
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*/
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.thumb_func
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.global MainExitHandler
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.weak MainExitHandler
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MainExitHandler:
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.loop: b .loop
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/*
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* Default early initialization code. It is declared weak in order to be
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* replaced by the real initialization code.
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* Early initialization is performed just after reset before BSS and DATA
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* segments initialization.
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*/
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.thumb_func
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.global hwinit0
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.weak hwinit0
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hwinit0:
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bx lr
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/*
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* Default late initialization code. It is declared weak in order to be
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* replaced by the real initialization code.
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* Late initialization is performed after BSS and DATA segments initialization
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* and before invoking the main() function.
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*/
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.thumb_func
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.global hwinit1
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.weak hwinit1
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hwinit1:
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bx lr
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#endif
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/** @} */
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