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https://salsa.debian.org/gnuk-team/gnuk/gnuk.git
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200 lines
6.2 KiB
C
200 lines
6.2 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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---
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A special exception to the GPL can be applied should you wish to distribute
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a combined work that includes ChibiOS/RT, without being obliged to provide
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the source code for any proprietary components. See the file exception.txt
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for full details of how and when the exception can be applied.
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*/
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/**
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* @file ARMCMx/nvic.h
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* @brief Cortex-Mx NVIC support macros and structures.
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*
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* @addtogroup ARMCMx_NVIC
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* @{
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*/
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#ifndef _NVIC_H_
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#define _NVIC_H_
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/*
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* System vector constants for @p NVICSetSystemHandlerPriority().
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*/
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#define HANDLER_MEM_MANAGE 0 /**< MEM MANAGE vector id. */
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#define HANDLER_BUS_FAULT 1 /**< BUS FAULT vector id. */
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#define HANDLER_USAGE_FAULT 2 /**< USAGE FAULT vector id. */
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#define HANDLER_RESERVED_3 3
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#define HANDLER_RESERVED_4 4
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#define HANDLER_RESERVED_5 5
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#define HANDLER_RESERVED_6 6
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#define HANDLER_SVCALL 7 /**< SVCALL vector id. */
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#define HANDLER_DEBUG_MONITOR 8 /**< DEBUG MONITOR vector id. */
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#define HANDLER_RESERVED_9 9
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#define HANDLER_PENDSV 10 /**< PENDSV vector id. */
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#define HANDLER_SYSTICK 11 /**< SYS TCK vector id. */
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typedef volatile uint8_t IOREG8; /**< 8 bits I/O register type. */
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typedef volatile uint32_t IOREG32; /**< 32 bits I/O register type. */
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/**
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* @brief NVIC ITCR register.
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*/
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#define NVIC_ITCR (*((IOREG32 *)0xE000E004))
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/**
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* @brief NVIC STIR register.
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*/
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#define NVIC_STIR (*((IOREG32 *)0xE000EF00))
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/**
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* @brief Structure representing the SYSTICK I/O space.
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*/
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typedef struct {
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IOREG32 CSR;
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IOREG32 RVR;
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IOREG32 CVR;
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IOREG32 CBVR;
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} CM3_ST;
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/**
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* @brief SYSTICK peripheral base address.
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*/
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#define STBase ((CM3_ST *)0xE000E010)
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#define ST_CSR (STBase->CSR)
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#define ST_RVR (STBase->RVR)
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#define ST_CVR (STBase->CVR)
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#define ST_CBVR (STBase->CBVR)
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#define CSR_ENABLE_MASK (0x1 << 0)
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#define ENABLE_OFF_BITS (0 << 0)
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#define ENABLE_ON_BITS (1 << 0)
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#define CSR_TICKINT_MASK (0x1 << 1)
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#define TICKINT_DISABLED_BITS (0 << 1)
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#define TICKINT_ENABLED_BITS (1 << 1)
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#define CSR_CLKSOURCE_MASK (0x1 << 2)
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#define CLKSOURCE_EXT_BITS (0 << 2)
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#define CLKSOURCE_CORE_BITS (1 << 2)
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#define CSR_COUNTFLAG_MASK (0x1 << 16)
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#define RVR_RELOAD_MASK (0xFFFFFF << 0)
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#define CVR_CURRENT_MASK (0xFFFFFF << 0)
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#define CBVR_TENMS_MASK (0xFFFFFF << 0)
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#define CBVR_SKEW_MASK (0x1 << 30)
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#define CBVR_NOREF_MASK (0x1 << 31)
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/**
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* @brief Structure representing the NVIC I/O space.
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*/
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typedef struct {
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IOREG32 ISER[8];
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IOREG32 unused1[24];
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IOREG32 ICER[8];
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IOREG32 unused2[24];
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IOREG32 ISPR[8];
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IOREG32 unused3[24];
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IOREG32 ICPR[8];
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IOREG32 unused4[24];
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IOREG32 IABR[8];
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IOREG32 unused5[56];
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IOREG32 IPR[60];
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} CM3_NVIC;
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/**
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* @brief NVIC peripheral base address.
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*/
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#define NVICBase ((CM3_NVIC *)0xE000E100)
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#define NVIC_ISER(n) (NVICBase->ISER[n])
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#define NVIC_ICER(n) (NVICBase->ICER[n])
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#define NVIC_ISPR(n) (NVICBase->ISPR[n])
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#define NVIC_ICPR(n) (NVICBase->ICPR[n])
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#define NVIC_IABR(n) (NVICBase->IABR[n])
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#define NVIC_IPR(n) (NVICBase->IPR[n])
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/**
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* @brief Structure representing the System Control Block I/O space.
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*/
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typedef struct {
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IOREG32 CPUID;
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IOREG32 ICSR;
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IOREG32 VTOR;
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IOREG32 AIRCR;
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IOREG32 SCR;
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IOREG32 CCR;
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IOREG32 SHPR[3];
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IOREG32 SHCSR;
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IOREG32 CFSR;
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IOREG32 HFSR;
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IOREG32 DFSR;
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IOREG32 MMFAR;
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IOREG32 BFAR;
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IOREG32 AFSR;
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} CM3_SCB;
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/**
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* @brief SCB peripheral base address.
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*/
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#define SCBBase ((CM3_SCB *)0xE000ED00)
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#define SCB_CPUID (SCBBase->CPUID)
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#define SCB_ICSR (SCBBase->ICSR)
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#define SCB_VTOR (SCBBase->VTOR)
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#define SCB_AIRCR (SCBBase->AIRCR)
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#define SCB_SCR (SCBBase->SCR)
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#define SCB_CCR (SCBBase->CCR)
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#define SCB_SHPR(n) (SCBBase->SHPR[n])
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#define SCB_SHCSR (SCBBase->SHCSR)
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#define SCB_CFSR (SCBBase->CFSR)
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#define SCB_HFSR (SCBBase->HFSR)
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#define SCB_DFSR (SCBBase->DFSR)
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#define SCB_MMFAR (SCBBase->MMFAR)
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#define SCB_BFAR (SCBBase->BFAR)
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#define SCB_AFSR (SCBBase->AFSR)
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#define ICSR_VECTACTIVE_MASK (0x1FF << 0)
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#define ICSR_RETTOBASE (0x1 << 11)
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#define ICSR_VECTPENDING_MASK (0x1FF << 12)
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#define ICSR_ISRPENDING (0x1 << 22)
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#define ICSR_ISRPREEMPT (0x1 << 23)
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#define ICSR_PENDSTCLR (0x1 << 25)
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#define ICSR_PENDSTSET (0x1 << 26)
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#define ICSR_PENDSVCLR (0x1 << 27)
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#define ICSR_PENDSVSET (0x1 << 28)
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#define ICSR_NMIPENDSET (0x1 << 31)
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#define AIRCR_VECTKEY 0x05FA0000
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#define AIRCR_PRIGROUP_MASK (0x7 << 8)
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#define AIRCR_PRIGROUP(n) ((n) << 8)
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#ifdef __cplusplus
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extern "C" {
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#endif
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void NVICEnableVector(uint32_t n, uint32_t prio);
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void NVICDisableVector(uint32_t n);
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void NVICSetSystemHandlerPriority(uint32_t handler, uint32_t prio);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _NVIC_H_ */
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/** @} */
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