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<td><big><big>ChibiOS/RT</big></big><br><br>Architecture - Reference Manual - Guides</td>
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<a href="#define-members">Defines</a> </div>
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<h1>hal_lld_f103.h File Reference</h1> </div>
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<p>STM32F103 HAL subsystem low level driver header.
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<a href="#_details">More...</a></p>
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<p><a href="hal__lld__f103_8h_source.html">Go to the source code of this file.</a></p>
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<table class="memberdecls">
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<tr><td colspan="2"><h2><a name="define-members"></a>
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Defines</h2></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga65c12bc7160ab579eaeee40ec2915110">STM32_HSICLK</a> 8000000</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga90421650b988332462db9a08815efb6f">STM32_LSICLK</a> 40000</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga6a49bf4388f3acf15661252b3bb7547b">STM32_SW_HSI</a> (0 << 0)</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gab5b581bd1ff4fd48fc8c5f093ca776ca">STM32_SW_HSE</a> (1 << 0)</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga8bc74f08245bf796555d33a86afd9fc4">STM32_SW_PLL</a> (2 << 0)</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gabf2bcd341b2140b7a82ff24b92f6af68">STM32_HPRE_DIV1</a> (0 << 4)</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga6dfcd5149eb88f1681b4defc77f4d8b2">STM32_HPRE_DIV2</a> (8 << 4)</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gaeb5f7cce4d1b6646f7e48d2784aade1c">STM32_HPRE_DIV4</a> (9 << 4)</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gaaa6b23363a848239b048cde5b565e2d5">STM32_HPRE_DIV8</a> (10 << 4)</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gaab6772439c76981e1c1d23bf97ec3910">STM32_HPRE_DIV16</a> (11 << 4)</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga152f3c2eabcc96019194c85bb2f7f2af">STM32_HPRE_DIV64</a> (12 << 4)</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga6ea1e82317d266fa344d6787f485e991">STM32_HPRE_DIV128</a> (13 << 4)</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga7099ae3ddeb74537f4a34f1e36730dbe">STM32_HPRE_DIV256</a> (14 << 4)</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gaac6d223ccd51614bd3c8f354b16e4671">STM32_HPRE_DIV512</a> (15 << 4)</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga3c9ece8fc206039d5723f8016adb789d">STM32_PPRE1_DIV1</a> (0 << 8)</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gae205bae3cec6b45723d687bc2b7a4e38">STM32_PPRE1_DIV2</a> (4 << 8)</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga18b34bc52ebebd209fffb01002b2bc98">STM32_PPRE1_DIV4</a> (5 << 8)</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gab7b100956dae0246dd9faa0a54010b17">STM32_PPRE1_DIV8</a> (6 << 8)</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga750b0ba24dbebb1fac1a3b2330666350">STM32_PPRE1_DIV16</a> (7 << 8)</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga9883bc736b03534d09789f13a6026c31">STM32_PPRE2_DIV1</a> (0 << 11)</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga55e0199e60c0551b8fae6b8eb49d6364">STM32_PPRE2_DIV2</a> (4 << 11)</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gaa85c01042fcee21da997473f4f42ba78">STM32_PPRE2_DIV4</a> (5 << 11)</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga0db040c759cc09cee6261301a952d862">STM32_PPRE2_DIV8</a> (6 << 11)</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gaf986782e091335aeaf0235635d20353d">STM32_PPRE2_DIV16</a> (7 << 11)</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gaedf6c315cac4eed84eefb906f11909d5">STM32_ADCPRE_DIV2</a> (0 << 14)</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gac85f817c97ee65cef48408aae15a4275">STM32_ADCPRE_DIV4</a> (1 << 14)</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gad628210302793a5ffdd7a92515c2d3a1">STM32_ADCPRE_DIV6</a> (2 << 14)</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gacc4296ec001b1f54da48a503c68af27a">STM32_ADCPRE_DIV8</a> (3 << 14)</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gac8438d5c9b3c6bfd0346e1026b8055fc">STM32_PLLSRC_HSI</a> (0 << 16)</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga64328eed4cc2c355aab176e0beb31b63">STM32_PLLSRC_HSE</a> (1 << 16)</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga70455e18b40c7dc6fd0a2a2dc32df2b2">STM32_PLLXTPRE_DIV1</a> (0 << 17)</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga1e7e686a70079862ff8e7e14d9d85124">STM32_PLLXTPRE_DIV2</a> (1 << 17)</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga89cb88c836f543f0133cb923d24b8ac2">STM32_MCO_NOCLOCK</a> (0 << 24)</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga88dd4d9fea9a7de30ff26dfc73b2dca7">STM32_MCO_SYSCLK</a> (4 << 24)</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gaa208624a69b4a031b7ce4b9bf41a0dac">STM32_MCO_HSI</a> (5 << 24)</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga881bbb9fb274aaa98a69c6fcc64a92ab">STM32_MCO_HSE</a> (6 << 24)</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga1c0494e40e6a7a032b259209fb69a802">STM32_MCO_PLLDIV2</a> (7 << 24)</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gad4c8a013e3354da6d132cdb91a481c3c">WWDG_IRQHandler</a> Vector40</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga045476dfaec8c84f5e16b06b937c0c18">PVD_IRQHandler</a> Vector44</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga3668bf2c1d66bea024e3ff1cc7f9952c">TAMPER_IRQHandler</a> Vector48</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gaeadad366a84e3b496a18ef919a28342b">RTC_IRQHandler</a> Vector4C</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga3cca2eaebb146655fb72e09adee7839d">FLASH_IRQHandler</a> Vector50</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga5a6d083fa78461da86a717b28973e009">RCC_IRQHandler</a> Vector54</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gac468127e2887086eeafd0fc5044c8c1f">EXTI0_IRQHandler</a> Vector58</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga0580c4052329cca57bede85ffff29de5">EXTI1_IRQHandler</a> Vector5C</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gae39f987c5ace4c480d23ea000ed53f6e">EXTI2_IRQHandler</a> Vector60</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga6227b0b9333e766db47c3e86d57b8a4f">EXTI3_IRQHandler</a> Vector64</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gab7dcb33a5cf9254fd25f8619c6c92ab8">EXTI4_IRQHandler</a> Vector68</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga3f7debe9fc2548ab6640825967110101">DMA1_Ch1_IRQHandler</a> Vector6C</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga37d95c99d84753e4efe4909bbaae4fa1">DMA1_Ch2_IRQHandler</a> Vector70</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gaa3a67d36319fc3c153999ebbb0e0cd49">DMA1_Ch3_IRQHandler</a> Vector74</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga76bb91040587d17a396ccb31395aa0e5">DMA1_Ch4_IRQHandler</a> Vector78</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gadbe5dfd4aed18b04f864d5fbed32f438">DMA1_Ch5_IRQHandler</a> Vector7C</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga39b427886b2c2d2c7ce3be9537c1f6a2">DMA1_Ch6_IRQHandler</a> Vector80</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gaecfa962ef95ba5a06ad60ac57e8a54ec">DMA1_Ch7_IRQHandler</a> Vector84</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gabc7315be5ac997b8f347fe1e22f58adf">ADC1_2_IRQHandler</a> Vector88</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga4fdbecfed2cdeadfec6210f7ec510fbc">CAN1_TX_IRQHandler</a> Vector8C</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gab62271824915d04d5350da852b32cd5e">USB_HP_IRQHandler</a> Vector8C</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga40873fbdcb268642576f45babaad5c2e">CAN1_RX0_IRQHandler</a> Vector90</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gab5032057a517201938fc126d12690f4e">USB_LP_IRQHandler</a> Vector90</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga8550c9680a59f697a018b283878b0648">CAN1_RX1_IRQHandler</a> Vector94</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gab6a0b35d117d66c63172d56a59ce2e20">CAN1_SCE_IRQHandler</a> Vector98</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gab2efac0867c3c975ea4ea586013b10ce">EXTI9_5_IRQHandler</a> Vector9C</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga2f33687cec484ac054656b3a9daca2c1">TIM1_BRK_IRQHandler</a> VectorA0</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga578b4afc3dd6695f66e1b7a116c33d41">TIM1_UP_IRQHandler</a> VectorA4</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga029af7575a43b2c3c6b50c62571ed21c">TIM1_TRG_COM_IRQHandler</a> VectorA8</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga3f167d3dabac4824347885babe86926f">TIM1_CC_IRQHandler</a> VectorAC</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga499bdce3f1172d391e9565e9f9d07a76">TIM2_IRQHandler</a> VectorB0</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga8e5c20e41d6d555efd718fc29037cc26">TIM3_IRQHandler</a> VectorB4</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga582fbd8d35d9280347b55cd12f65c213">TIM4_IRQHandler</a> VectorB8</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga83e61d3d4eb31c12a4369f6b1d9fa742">I2C1_EV_IRQHandler</a> VectorBC</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gad8e382b9ce2bb267c7414c7185637654">I2C1_ER_IRQHandler</a> VectorC0</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga0b8dacb7ac76cfc954fd0db2d5e53025">I2C2_EV_IRQHandler</a> VectorC4</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga1a98d05b127fa293a1210397bda82007">I2C2_ER_IRQHandler</a> VectorC8</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gadc38983c3ec1357840b21472ff1a2147">SPI1_IRQHandler</a> VectorCC</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gaaace6fa425ba2038de9ce01755070057">SPI2_IRQHandler</a> VectorD0</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga23182c2feafd217668e6b37c126512a1">USART1_IRQHandler</a> VectorD4</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga484cf268e20400bfa2cf159fd86b98be">USART2_IRQHandler</a> VectorD8</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga8a246e61ab1022b289c251e48f7094aa">USART3_IRQHandler</a> VectorDC</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga94d705608b3377724d368a6ce381c735">EXTI15_10_IRQHandler</a> VectorE0</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga649ba5a31ccb8936b7bb9be165160be4">RTCAlarm_IRQHandler</a> VectorE4</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga6b2574837ab61eb470ef0ed1974c2b06">USBWakeUp_IRQHandler</a> VectorE8</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gac635c00a20e7eabe13729819a1da315c">TIM8_BRK_IRQHandler</a> VectorEC</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga382f5f6851ef86ec4307b5ec06980e12">TIM8_UP_IRQHandler</a> VectorF0</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gacf84e2e666ecbfd5efef8805e8870f8e">TIM8_TRG_COM_IRQHandler</a> VectorF4</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gaa757dea287f3017dd4829db7357aaf4c">TIM8_CC_IRQHandler</a> VectorF8</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gaeaaf5d1330ebfa99dc1baf2ebaadccaf">ADC3_IRQHandler</a> VectorFC</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga5b49d338a67aae8ff880596f373a1d58">FSMC_IRQHandler</a> Vector100</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga44b56def4842b9f9ba6ce93e4dfe6361">SDIO_IRQHandler</a> Vector104</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gab9fe80492ed4e0fa1fd6faf58bd58e4b">TIM5_IRQHandler</a> Vector108</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gad9e1203f13593d969234331ceb55d7d2">SPI3_IRQHandler</a> Vector10C</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gac4b19b89f21dd7c2510cf3ad18f30550">UART4_IRQHandler</a> Vector110</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga3b377c7a7064b3dad2e2ef423f786786">UART5_IRQHandler</a> Vector114</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gae30e35a563a952a284f3f54d7f164ccd">TIM6_IRQHandler</a> Vector118</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gaf58f7701209700015c8090b7904e5e3e">TIM7_IRQHandler</a> Vector11C</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga59e42b422ce23eb466d067abbd0098ea">DMA2_Ch1_IRQHandler</a> Vector120</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gae86b2cc4ca778cf1922b28e0fa0957d8">DMA2_Ch2_IRQHandler</a> Vector124</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gad3cdd76c6987693a2aeeb7ceb0c470dc">DMA2_Ch3_IRQHandler</a> Vector128</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gaf4dbbedea451647a29ff2d31903b5388">DMA2_Ch4_5_IRQHandler</a> Vector12C</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga29204b81c265dd6e124fbcf12a2c8d6f">STM32_SW</a> STM32_SW_PLL</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">Main clock source selection. <a href="group___s_t_m32_f103___h_a_l.html#ga29204b81c265dd6e124fbcf12a2c8d6f"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga811cfbd049f0ab00976def9593849d32">STM32_PLLSRC</a> STM32_PLLSRC_HSE</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">Clock source for the PLL. <a href="group___s_t_m32_f103___h_a_l.html#ga811cfbd049f0ab00976def9593849d32"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gad7443fb89c1569f264a218209fbe8ddd">STM32_PLLXTPRE</a> STM32_PLLXTPRE_DIV1</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">Crystal PLL pre-divider. <a href="group___s_t_m32_f103___h_a_l.html#gad7443fb89c1569f264a218209fbe8ddd"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga0015fc8f73017358a7025ba57a265a11">STM32_PLLMUL_VALUE</a> 9</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">PLL multiplier value. <a href="group___s_t_m32_f103___h_a_l.html#ga0015fc8f73017358a7025ba57a265a11"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga035ea0d8259c0f89306c6a7d344705f2">STM32_HPRE</a> STM32_HPRE_DIV1</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">AHB prescaler value. <a href="group___s_t_m32_f103___h_a_l.html#ga035ea0d8259c0f89306c6a7d344705f2"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga5f9c3734d5d06c9ccd5214af5c78c4f8">STM32_PPRE1</a> STM32_PPRE1_DIV2</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">APB1 prescaler value. <a href="group___s_t_m32_f103___h_a_l.html#ga5f9c3734d5d06c9ccd5214af5c78c4f8"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga3670f3886d02bb3010016bbf0db0db83">STM32_PPRE2</a> STM32_PPRE2_DIV2</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">APB2 prescaler value. <a href="group___s_t_m32_f103___h_a_l.html#ga3670f3886d02bb3010016bbf0db0db83"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga671b452f988ee9b64e128fad72f656e6">STM32_ADCPRE</a> STM32_ADCPRE_DIV4</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">ADC prescaler value. <a href="group___s_t_m32_f103___h_a_l.html#ga671b452f988ee9b64e128fad72f656e6"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga5b24026a48ef156dcb642b6e55a68e02">STM32_MCO</a> STM32_MCO_NOCLOCK</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">MCO pin setting. <a href="group___s_t_m32_f103___h_a_l.html#ga5b24026a48ef156dcb642b6e55a68e02"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga9889ca83d58a738f5758b4c300433f2a">STM32_PLLMUL</a> ((STM32_PLLMUL_VALUE - 2) << 18)</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">PLLMUL field. <a href="group___s_t_m32_f103___h_a_l.html#ga9889ca83d58a738f5758b4c300433f2a"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga0b32be6543b6d55b0505288f268ddbe1">STM32_PLLCLKIN</a> (STM32_HSECLK / 1)</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">PLL input clock frequency. <a href="group___s_t_m32_f103___h_a_l.html#ga0b32be6543b6d55b0505288f268ddbe1"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga551b4e93d2b76245c4b912ebfc54f9f3">STM32_PLLCLKOUT</a> (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">PLL output clock frequency. <a href="group___s_t_m32_f103___h_a_l.html#ga551b4e93d2b76245c4b912ebfc54f9f3"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga81594f71c9bc1c1fde4e5207e5133777">STM32_SYSCLK</a> STM32_PLLCLKOUT</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">System clock source. <a href="group___s_t_m32_f103___h_a_l.html#ga81594f71c9bc1c1fde4e5207e5133777"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga918128f20df10ac68bd73605007bccf1">STM32_HCLK</a> (STM32_SYSCLK / 1)</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">AHB frequency. <a href="group___s_t_m32_f103___h_a_l.html#ga918128f20df10ac68bd73605007bccf1"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga79d8b0164de9c4437da78024b0ed94cb">STM32_PCLK1</a> (STM32_HCLK / 1)</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">APB1 frequency. <a href="group___s_t_m32_f103___h_a_l.html#ga79d8b0164de9c4437da78024b0ed94cb"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga2a19a811dd0dadfed94695a579997cec">STM32_PCLK2</a> (STM32_HCLK / 1)</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">APB2 frequency. <a href="group___s_t_m32_f103___h_a_l.html#ga2a19a811dd0dadfed94695a579997cec"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga62f559490a97de4746d6963d946e1e37">STM32_ADCCLK</a> (STM32_PCLK2 / 2)</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">ADC frequency. <a href="group___s_t_m32_f103___h_a_l.html#ga62f559490a97de4746d6963d946e1e37"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga8d53f5e948e73dc86013349c17f742f3">STM32_TIMCLK1</a> (STM32_PCLK1 * 1)</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">Timers 2, 3, 4, 5, 6, 7, 12, 13, 14 clock. <a href="group___s_t_m32_f103___h_a_l.html#ga8d53f5e948e73dc86013349c17f742f3"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#gacacec831f4aa8037c710ab56c7a73686">STM32_TIMCLK2</a> (STM32_PCLK2 * 1)</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">Timers 1, 8, 9, 10 and 11 clock. <a href="group___s_t_m32_f103___h_a_l.html#gacacec831f4aa8037c710ab56c7a73686"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_t_m32_f103___h_a_l.html#ga59b3885d4e2a3f63cfeb9ae58b6da563">STM32_FLASHBITS</a> 0x00000010</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">Flash settings. <a href="group___s_t_m32_f103___h_a_l.html#ga59b3885d4e2a3f63cfeb9ae58b6da563"></a><br/></td></tr>
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</table>
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<hr/><a name="_details"></a><h2>Detailed Description</h2>
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<p>STM32F103 HAL subsystem low level driver header. </p>
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<p>Definition in file <a class="el" href="hal__lld__f103_8h_source.html">hal_lld_f103.h</a>.</p>
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</div>
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<hr size="1"><address style="text-align: right;"><small>
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Generated on Sun Nov 28 2010 14:09:50 for ChibiOS/RT by <a href="http://www.doxygen.org/index.html"><img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.7.1</small></address>
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</body>
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</html>
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