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<title>ChibiOS/RT: pal_lld.h File Reference</title>
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<td style="width: 80px;"><img alt="ChibiOS/RT Logo" src="logo_small.png"></td>
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<td><big><big>ChibiOS/RT</big></big><br><br>Architecture - Reference Manual - Guides</td>
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<a href="#nested-classes">Data Structures</a> |
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<a href="#typedef-members">Typedefs</a> </div>
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<div class="headertitle">
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<h1>pal_lld.h File Reference</h1> </div>
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</div>
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<div class="contents">
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<p>PAL subsystem low level driver header template.
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<a href="#_details">More...</a></p>
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<p><a href="templates_2pal__lld_8h_source.html">Go to the source code of this file.</a></p>
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<table class="memberdecls">
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<tr><td colspan="2"><h2><a name="nested-classes"></a>
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Data Structures</h2></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">struct </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_generic_config.html">GenericConfig</a></td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">Generic I/O ports static initializer. <a href="struct_generic_config.html#_details">More...</a><br/></td></tr>
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<tr><td colspan="2"><h2><a name="define-members"></a>
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Defines</h2></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___p_a_l___l_l_d.html#ga20ffc1985d583352e179f5f2c3fa700e">PAL_IOPORTS_WIDTH</a> 32</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">Width, in bits, of an I/O port. <a href="group___p_a_l___l_l_d.html#ga20ffc1985d583352e179f5f2c3fa700e"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___p_a_l___l_l_d.html#ga713ecb1a9d4fcc2fa53c7a91b8832600">PAL_WHOLE_PORT</a> ((<a class="el" href="group___p_a_l___l_l_d.html#ga6115967a8db28246105e03741ff5eb18">ioportmask_t</a>)0xFFFFFFFF)</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">Whole port mask. <a href="group___p_a_l___l_l_d.html#ga713ecb1a9d4fcc2fa53c7a91b8832600"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___p_a_l___l_l_d.html#gaef5823310b8302e832ae22ab895ddde1">IOPORT1</a> 0</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">First I/O port identifier. <a href="group___p_a_l___l_l_d.html#gaef5823310b8302e832ae22ab895ddde1"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___p_a_l___l_l_d.html#ga94461ae7e12014a0a71319df5d48fb1a">pal_lld_init</a>(config)</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">Low level PAL subsystem initialization. <a href="group___p_a_l___l_l_d.html#ga94461ae7e12014a0a71319df5d48fb1a"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___p_a_l___l_l_d.html#ga9cf4c7dec4e8ce455857cd1be2c60d59">pal_lld_readport</a>(port)</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">Reads the physical I/O port states. <a href="group___p_a_l___l_l_d.html#ga9cf4c7dec4e8ce455857cd1be2c60d59"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___p_a_l___l_l_d.html#gae1158b9ebac440d69c81765bbaa7931d">pal_lld_readlatch</a>(port)</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">Reads the output latch. <a href="group___p_a_l___l_l_d.html#gae1158b9ebac440d69c81765bbaa7931d"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___p_a_l___l_l_d.html#gab927bfab9c894975177705c314feed62">pal_lld_writeport</a>(port, bits)</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">Writes a bits mask on a I/O port. <a href="group___p_a_l___l_l_d.html#gab927bfab9c894975177705c314feed62"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___p_a_l___l_l_d.html#ga3bdaa97aee564600e297faa34a6aa041">pal_lld_setport</a>(port, bits)</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">Sets a bits mask on a I/O port. <a href="group___p_a_l___l_l_d.html#ga3bdaa97aee564600e297faa34a6aa041"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___p_a_l___l_l_d.html#ga313da00085ab6f5ba2761eb269090961">pal_lld_clearport</a>(port, bits)</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">Clears a bits mask on a I/O port. <a href="group___p_a_l___l_l_d.html#ga313da00085ab6f5ba2761eb269090961"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___p_a_l___l_l_d.html#ga89c47569615c994b56ccc2caa582e38b">pal_lld_toggleport</a>(port, bits)</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">Toggles a bits mask on a I/O port. <a href="group___p_a_l___l_l_d.html#ga89c47569615c994b56ccc2caa582e38b"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___p_a_l___l_l_d.html#ga232943013bbee9d09b09ffa90da7bd0b">pal_lld_readgroup</a>(port, mask, offset)</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">Reads a group of bits. <a href="group___p_a_l___l_l_d.html#ga232943013bbee9d09b09ffa90da7bd0b"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___p_a_l___l_l_d.html#gaf7896552442b80d846a5bc55a97c7808">pal_lld_writegroup</a>(port, mask, offset, bits)</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">Writes a group of bits. <a href="group___p_a_l___l_l_d.html#gaf7896552442b80d846a5bc55a97c7808"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___p_a_l___l_l_d.html#ga4787de055e5ef29a5d386bcd5e7e2011">pal_lld_setgroupmode</a>(port, mask, mode)</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">Pads group mode setup. <a href="group___p_a_l___l_l_d.html#ga4787de055e5ef29a5d386bcd5e7e2011"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___p_a_l___l_l_d.html#ga95f6c65f8f4166d329e857e01125046e">pal_lld_readpad</a>(port, pad)</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">Reads a logical state from an I/O pad. <a href="group___p_a_l___l_l_d.html#ga95f6c65f8f4166d329e857e01125046e"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___p_a_l___l_l_d.html#ga80d21355227550d52741e04a4882a7b4">pal_lld_writepad</a>(port, pad, bit)</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">Writes a logical state on an output pad. <a href="group___p_a_l___l_l_d.html#ga80d21355227550d52741e04a4882a7b4"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___p_a_l___l_l_d.html#gac0b779928f669896d70b9700485102b3">pal_lld_setpad</a>(port, pad)</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">Sets a pad logical state to <code>PAL_HIGH</code>. <a href="group___p_a_l___l_l_d.html#gac0b779928f669896d70b9700485102b3"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___p_a_l___l_l_d.html#ga78ec89ccd1150520d6edf7af93b31b4f">pal_lld_clearpad</a>(port, pad)</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">Clears a pad logical state to <code>PAL_LOW</code>. <a href="group___p_a_l___l_l_d.html#ga78ec89ccd1150520d6edf7af93b31b4f"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___p_a_l___l_l_d.html#gaff32956e06caaf121a48262c6f2fba53">pal_lld_togglepad</a>(port, pad)</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">Toggles a pad logical state. <a href="group___p_a_l___l_l_d.html#gaff32956e06caaf121a48262c6f2fba53"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___p_a_l___l_l_d.html#ga34f944d44e7e129d1c458514b833b240">pal_lld_setpadmode</a>(port, pad, mode)</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">Pad mode setup. <a href="group___p_a_l___l_l_d.html#ga34f944d44e7e129d1c458514b833b240"></a><br/></td></tr>
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<tr><td colspan="2"><h2><a name="typedef-members"></a>
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Typedefs</h2></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">typedef <a class="el" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___p_a_l___l_l_d.html#ga6115967a8db28246105e03741ff5eb18">ioportmask_t</a></td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">Digital I/O port sized unsigned type. <a href="group___p_a_l___l_l_d.html#ga6115967a8db28246105e03741ff5eb18"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">typedef <a class="el" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___p_a_l___l_l_d.html#ga4a3294068a07606c952cefda0866761a">ioportid_t</a></td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">Port Identifier. <a href="group___p_a_l___l_l_d.html#ga4a3294068a07606c952cefda0866761a"></a><br/></td></tr>
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</table>
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<hr/><a name="_details"></a><h2>Detailed Description</h2>
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<p>PAL subsystem low level driver header template. </p>
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<p>Definition in file <a class="el" href="templates_2pal__lld_8h_source.html">templates/pal_lld.h</a>.</p>
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</div>
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<hr size="1"><address style="text-align: right;"><small>
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Generated on Sun Nov 28 2010 14:09:50 for ChibiOS/RT by <a href="http://www.doxygen.org/index.html"><img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.7.1</small></address>
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