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hw: foboot-bitstream: use 12-bit reset counter

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It doesn't need to be 13 bits, and it saves us a few LCs.

Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
Sean Cross 2019-07-21 17:10:05 +08:00
parent a0a9a416f1
commit 1b0bb2543b
1 changed files with 1 additions and 1 deletions
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hw/foboot-bitstream.py
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@ -172,7 +172,7 @@ class _CRG(Module):
clk48_raw = platform.request("clk48")
clk12 = Signal()
reset_delay = Signal(13, reset=8191)
reset_delay = Signal(12, reset=4095)
self.clock_domains.cd_por = ClockDomain()
self.reset = Signal()