hw: add some vexriscv experiments

We're trying to improve performance and reduce core size.

This uses a newer version of the vexriscv core.  It has a shorter
pipeline, with better exception handling.  It also properly initializes
registers.

Signed-off-by: Sean Cross <sean@xobs.io>

hw/2-stage-1024-cache.yaml

@@ -1,4 +0,0 @@
-iBus: !!vexriscv.BusReport
-  flushInstructions: [16399, 19, 19, 19]
-  info: !!vexriscv.CacheReport {bytePerLine: 32, size: 1024}
-  kind: cached

hw/foboot-bitstream.py

@@ -195,7 +195,7 @@ class _CRG(Module):
             # POR reset logic- POR generated from sys clk, POR logic feeds sys clk
             # reset.
             self.clock_domains.cd_por = ClockDomain()
-            reset_delay = Signal(14, reset=4095)
+            reset_delay = Signal(10, reset=1023)
             self.comb += [
                 self.cd_por.clk.eq(self.cd_sys.clk),
                 self.cd_sys.rst.eq(reset_delay != 0),
@@ -546,7 +546,7 @@ class PicoRVSpi(Module, AutoCSR):
             i_cfgreg_di = cfg,
 	        o_cfgreg_do = cfg_out,
         )
-        platform.add_source("spimemio.v")
+        platform.add_source("rtl/spimemio.v")
 
 class BBSpi(Module, AutoCSR):
     def __init__(self, platform, pads):
@@ -617,10 +617,13 @@ class BaseSoC(SoCCore):
 
     def __init__(self, platform, boot_source="rand",
                  debug=None, bios_file=None, use_pll=True,
-                 use_dsp=False, placer=None, **kwargs):
+                 use_dsp=False, placer=None, output_dir="build",
+                 **kwargs):
         # Disable integrated RAM as we'll add it later
         self.integrated_sram_size = 0
 
+        self.output_dir = output_dir
+
         clk_freq = int(12e6)
         self.submodules.crg = _CRG(platform, use_pll=use_pll)
 
@@ -635,11 +638,14 @@ class BaseSoC(SoCCore):
             elif debug == "usb":
                 usb_debug = True
             if hasattr(self, "cpu"):
-                self.cpu.use_external_variant("2-stage-1024-cache-debug.v")
+                self.cpu.use_external_variant("rtl/2-stage-1024-cache-debug.v")
+                self.copy_memory_file("2-stage-1024-cache-debug.v_toplevel_RegFilePlugin_regFile.bin")
+                os.path.join(output_dir, "gateware")
                 self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu.debug_bus, 0x10)
         else:
             if hasattr(self, "cpu"):
-                self.cpu.use_external_variant("2-stage-1024-cache.v")
+                self.cpu.use_external_variant("rtl/2-stage-1024-cache.v")
+                self.copy_memory_file("2-stage-1024-cache.v_toplevel_RegFilePlugin_regFile.bin")
 
         # SPRAM- UP5K has single port RAM, might as well use it as SRAM to
         # free up scarce block RAM.
@@ -721,6 +727,15 @@ class BaseSoC(SoCCore):
         if placer is not None:
             platform.toolchain.nextpnr_build_template[1] += " --placer {}".format(placer)
 
+    def copy_memory_file(self, src):
+        import os
+        from shutil import copyfile
+        if not os.path.exists(self.output_dir):
+            os.mkdir(self.output_dir)
+        if not os.path.exists(os.path.join(self.output_dir, "gateware")):
+            os.mkdir(os.path.join(self.output_dir, "gateware"))
+        copyfile(os.path.join("rtl", src), os.path.join(self.output_dir, "gateware", src))
+
 def make_multiboot_header(filename, boot_offsets=[160]):
     """
     ICE40 allows you to program the SB_WARMBOOT state machine by adding the following
@@ -846,7 +861,8 @@ def main():
     soc = BaseSoC(platform, cpu_type=cpu_type, cpu_variant=cpu_variant,
                             debug=args.with_debug, boot_source=args.boot_source,
                             bios_file=args.bios, use_pll=not args.no_pll,
-                            use_dsp=args.with_dsp, placer=args.placer)
+                            use_dsp=args.with_dsp, placer=args.placer,
+                            output_dir=output_dir)
     builder = Builder(soc, output_dir=output_dir, csr_csv="test/csr.csv", compile_software=compile_software)
     if compile_software:
         builder.software_packages = [

hw/rtl/2-stage-1024-cache-debug.yaml

@@ -1,5 +1,5 @@
 debug: !!vexriscv.DebugReport {hardwareBreakpointCount: 4}
 iBus: !!vexriscv.BusReport
-  flushInstructions: [16399, 19, 19, 19]
+  flushInstructions: [4111, 19, 19, 19]
   info: !!vexriscv.CacheReport {bytePerLine: 32, size: 1024}
   kind: cached

hw/rtl/2-stage-1024-cache.yaml

@@ -0,0 +1,4 @@
+iBus: !!vexriscv.BusReport
+  flushInstructions: [4111, 19, 19, 19]
+  info: !!vexriscv.CacheReport {bytePerLine: 32, size: 2048}
+  kind: cached

hw/rtl/2-stage-2048-cache-debug.yaml

@@ -0,0 +1,5 @@
+debug: !!vexriscv.DebugReport {hardwareBreakpointCount: 4}
+iBus: !!vexriscv.BusReport
+  flushInstructions: [4111, 19, 19, 19]
+  info: !!vexriscv.CacheReport {bytePerLine: 32, size: 2048}
+  kind: cached

hw/rtl/2-stage-2048-cache.yaml

@@ -0,0 +1,4 @@
+iBus: !!vexriscv.BusReport
+  flushInstructions: [4111, 19, 19, 19]
+  info: !!vexriscv.CacheReport {bytePerLine: 32, size: 2048}
+  kind: cached

hw/rtl/2-stage-512-cache-debug.v

@@ -1,5 +1,5 @@
 // Generator : SpinalHDL v1.3.2    git head : 41815ceafff4e72c2e3a3e1ff7e9ada5202a0d26
-// Date      : 26/03/2019, 08:02:43
+// Date      : 11/04/2019, 06:14:01
 // Component : VexRiscv
 
 
@@ -92,19 +92,19 @@ module InstructionCache (
       input   io_mem_rsp_payload_error,
       input   clk,
       input   reset);
-  reg [23:0] _zz_12_;
+  reg [24:0] _zz_12_;
   reg [31:0] _zz_13_;
   wire  _zz_14_;
   wire [0:0] _zz_15_;
   wire [0:0] _zz_16_;
-  wire [23:0] _zz_17_;
+  wire [24:0] _zz_17_;
   reg  _zz_1_;
   reg  _zz_2_;
   reg  lineLoader_fire;
   reg  lineLoader_valid;
   reg [31:0] lineLoader_address;
   reg  lineLoader_hadError;
-  reg [5:0] lineLoader_flushCounter;
+  reg [4:0] lineLoader_flushCounter;
   reg  _zz_3_;
   reg  lineLoader_flushFromInterface;
   wire  _zz_4_;
@@ -116,21 +116,21 @@ module InstructionCache (
   wire  lineLoader_wayToAllocate_willOverflow;
   reg [2:0] lineLoader_wordIndex;
   wire  lineLoader_write_tag_0_valid;
-  wire [4:0] lineLoader_write_tag_0_payload_address;
+  wire [3:0] lineLoader_write_tag_0_payload_address;
   wire  lineLoader_write_tag_0_payload_data_valid;
   wire  lineLoader_write_tag_0_payload_data_error;
-  wire [21:0] lineLoader_write_tag_0_payload_data_address;
+  wire [22:0] lineLoader_write_tag_0_payload_data_address;
   wire  lineLoader_write_data_0_valid;
-  wire [7:0] lineLoader_write_data_0_payload_address;
+  wire [6:0] lineLoader_write_data_0_payload_address;
   wire [31:0] lineLoader_write_data_0_payload_data;
   wire  _zz_5_;
-  wire [4:0] _zz_6_;
+  wire [3:0] _zz_6_;
   wire  _zz_7_;
   wire  fetchStage_read_waysValues_0_tag_valid;
   wire  fetchStage_read_waysValues_0_tag_error;
-  wire [21:0] fetchStage_read_waysValues_0_tag_address;
-  wire [23:0] _zz_8_;
-  wire [7:0] _zz_9_;
+  wire [22:0] fetchStage_read_waysValues_0_tag_address;
+  wire [24:0] _zz_8_;
+  wire [6:0] _zz_9_;
   wire  _zz_10_;
   wire [31:0] fetchStage_read_waysValues_0_data;
   reg [31:0] decodeStage_mmuRsp_physicalAddress;
@@ -143,7 +143,7 @@ module InstructionCache (
   reg  decodeStage_mmuRsp_hit;
   reg  decodeStage_hit_tags_0_valid;
   reg  decodeStage_hit_tags_0_error;
-  reg [21:0] decodeStage_hit_tags_0_address;
+  reg [22:0] decodeStage_hit_tags_0_address;
   wire  decodeStage_hit_hits_0;
   wire  decodeStage_hit_valid;
   wire  decodeStage_hit_error;
@@ -152,9 +152,9 @@ module InstructionCache (
   reg [31:0] decodeStage_hit_word;
   reg  io_cpu_fetch_dataBypassValid_regNextWhen;
   reg [31:0] io_cpu_fetch_dataBypass_regNextWhen;
-  reg [23:0] ways_0_tags [0:31];
-  reg [31:0] ways_0_datas [0:255];
-  assign _zz_14_ = (! lineLoader_flushCounter[5]);
+  reg [24:0] ways_0_tags [0:15];
+  reg [31:0] ways_0_datas [0:127];
+  assign _zz_14_ = (! lineLoader_flushCounter[4]);
   assign _zz_15_ = _zz_8_[0 : 0];
   assign _zz_16_ = _zz_8_[1 : 1];
   assign _zz_17_ = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}};
@@ -222,7 +222,7 @@ module InstructionCache (
   end
 
   assign io_flush_cmd_ready = (! (lineLoader_valid || io_cpu_fetch_isValid));
-  assign _zz_4_ = lineLoader_flushCounter[5];
+  assign _zz_4_ = lineLoader_flushCounter[4];
   assign io_flush_rsp = ((_zz_4_ && (! _zz_4__regNext)) && lineLoader_flushFromInterface);
   assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent));
   assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],(5'b00000)};
@@ -238,21 +238,21 @@ module InstructionCache (
   assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1;
   assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement);
   assign _zz_5_ = 1'b1;
-  assign lineLoader_write_tag_0_valid = ((_zz_5_ && lineLoader_fire) || (! lineLoader_flushCounter[5]));
-  assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[5] ? lineLoader_address[9 : 5] : lineLoader_flushCounter[4 : 0]);
-  assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[5];
+  assign lineLoader_write_tag_0_valid = ((_zz_5_ && lineLoader_fire) || (! lineLoader_flushCounter[4]));
+  assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[4] ? lineLoader_address[8 : 5] : lineLoader_flushCounter[3 : 0]);
+  assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[4];
   assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error);
-  assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 10];
+  assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 9];
   assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && _zz_5_);
-  assign lineLoader_write_data_0_payload_address = {lineLoader_address[9 : 5],lineLoader_wordIndex};
+  assign lineLoader_write_data_0_payload_address = {lineLoader_address[8 : 5],lineLoader_wordIndex};
   assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data;
-  assign _zz_6_ = io_cpu_prefetch_pc[9 : 5];
+  assign _zz_6_ = io_cpu_prefetch_pc[8 : 5];
   assign _zz_7_ = (! io_cpu_fetch_isStuck);
   assign _zz_8_ = _zz_12_;
   assign fetchStage_read_waysValues_0_tag_valid = _zz_15_[0];
   assign fetchStage_read_waysValues_0_tag_error = _zz_16_[0];
-  assign fetchStage_read_waysValues_0_tag_address = _zz_8_[23 : 2];
-  assign _zz_9_ = io_cpu_prefetch_pc[9 : 2];
+  assign fetchStage_read_waysValues_0_tag_address = _zz_8_[24 : 2];
+  assign _zz_9_ = io_cpu_prefetch_pc[8 : 2];
   assign _zz_10_ = (! io_cpu_fetch_isStuck);
   assign fetchStage_read_waysValues_0_data = _zz_13_;
   assign io_cpu_fetch_data = (io_cpu_fetch_dataBypassValid ? io_cpu_fetch_dataBypass : fetchStage_read_waysValues_0_data[31 : 0]);
@@ -261,7 +261,7 @@ module InstructionCache (
   assign io_cpu_fetch_mmuBus_cmd_bypassTranslation = 1'b0;
   assign io_cpu_fetch_mmuBus_end = ((! io_cpu_fetch_isStuck) || io_cpu_fetch_isRemoved);
   assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuBus_rsp_physicalAddress;
-  assign decodeStage_hit_hits_0 = (decodeStage_hit_tags_0_valid && (decodeStage_hit_tags_0_address == decodeStage_mmuRsp_physicalAddress[31 : 10]));
+  assign decodeStage_hit_hits_0 = (decodeStage_hit_tags_0_valid && (decodeStage_hit_tags_0_address == decodeStage_mmuRsp_physicalAddress[31 : 9]));
   assign decodeStage_hit_valid = (decodeStage_hit_hits_0 != (1'b0));
   assign decodeStage_hit_error = decodeStage_hit_tags_0_error;
   assign decodeStage_hit_data = _zz_11_;
@@ -282,7 +282,7 @@ module InstructionCache (
     if(reset) begin
       lineLoader_valid <= 1'b0;
       lineLoader_hadError <= 1'b0;
-      lineLoader_flushCounter <= (6'b000000);
+      lineLoader_flushCounter <= (5'b00000);
       lineLoader_flushFromInterface <= 1'b0;
       lineLoader_cmdSent <= 1'b0;
       lineLoader_wordIndex <= (3'b000);
@@ -297,11 +297,11 @@ module InstructionCache (
         lineLoader_valid <= 1'b1;
       end
       if(_zz_14_)begin
-        lineLoader_flushCounter <= (lineLoader_flushCounter + (6'b000001));
+        lineLoader_flushCounter <= (lineLoader_flushCounter + (5'b00001));
       end
       if(io_flush_cmd_valid)begin
         if(io_flush_cmd_ready)begin
-          lineLoader_flushCounter <= (6'b000000);
+          lineLoader_flushCounter <= (5'b00000);
           lineLoader_flushFromInterface <= 1'b1;
         end
       end
@@ -324,7 +324,7 @@ module InstructionCache (
     if(io_cpu_fill_valid)begin
       lineLoader_address <= io_cpu_fill_payload;
     end
-    _zz_3_ <= lineLoader_flushCounter[5];
+    _zz_3_ <= lineLoader_flushCounter[4];
     _zz_4__regNext <= _zz_4_;
     if((! io_cpu_decode_isStuck))begin
       decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuBus_rsp_physicalAddress;

hw/rtl/2-stage-512-cache-debug.yaml

@@ -0,0 +1,5 @@
+debug: !!vexriscv.DebugReport {hardwareBreakpointCount: 4}
+iBus: !!vexriscv.BusReport
+  flushInstructions: [16399, 19, 19, 19]
+  info: !!vexriscv.CacheReport {bytePerLine: 32, size: 512}
+  kind: cached