Sean Cross
acb766e058
rtl: sbwarmboot: use upstream litex soc doc
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lxsocdoc is no longer maintained.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-03-11 21:24:52 +08:00
Sean Cross
a67d13e925
rtl: add fomucaptouch
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This is an untested block that will replace fomutouch.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-01-29 10:32:25 +08:00
Sean Cross
d10fdd580f
hw: version: use 8 characters for git revision
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By deafult, git only shows 7 characters. Increase this to 8.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-11-28 16:33:49 +08:00
Sean Cross
c79f831b63
rtl: version: always include git revision
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Even when building a tagged release, include the git revision. This
prevents the git revision from being reported as `00000000`.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-11-28 13:07:08 +08:00
Sean Cross
77632b0c9f
rtl: sbled: fix pin mapping for EVT
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The blue and green channels were swapped.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-11-27 13:24:59 +08:00
Sean Cross
24a9d7e4c7
hw: define C macros indicating hardware revision
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These macros can be used by the bios to indicate hardware revision.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-11-25 09:34:00 +08:00
Sean Cross
45e3b5b617
rtl: break foboot modules into their own files
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These are all independent modules, so break each one out into its own
file.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-11-23 10:03:56 +08:00
Sean Cross
58f99aebf2
eptri: wip commit
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This commit includes the spibone support we're using to debug eptri.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-11-01 17:07:27 +08:00
Sean Cross
25bf6c4335
rtl: add mcycle and minstret CSRs to vexriscv
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-10-07 12:08:33 +08:00
Sean Cross
1840a63420
hw: update rtl and documentation flags
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-20 21:56:18 +08:00
Sean Cross
d3dd349848
Revert "hw: rtl: use only one hw breakpoint"
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With an older litex build, we have enough space for four breakpoints
in the vexriscv core.
This reverts commit 2464b510fa
2019-07-22 08:51:18 +08:00
Sean Cross
2464b510fa
hw: rtl: use only one hw breakpoint
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We were running out of LUTs, so reduce the number of breakpoints
from 4 to 1.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-21 13:47:11 +08:00
Sean Cross
39b3fb6507
hw: rtl: use latest release version of vexriscv
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This doesn't appear to work yet, but is the latest upstream release
version of vexriscv.
Need to investigate more into why it's failing.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-04-26 09:53:51 +08:00
Sean Cross
ba310ab8e2
hw: rtl: add missing files
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-04-25 23:35:51 +08:00
Sean Cross
d147af1e6a
hw: add some vexriscv experiments
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We're trying to improve performance and reduce core size.
This uses a newer version of the vexriscv core. It has a shorter
pipeline, with better exception handling. It also properly initializes
registers.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-04-25 23:23:54 +08:00
