Sean Cross
b0b87addae
hw: deps: use experimental lxsocsupport up5kspram block
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-21 13:48:26 +08:00
Sean Cross
2464b510fa
hw: rtl: use only one hw breakpoint
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We were running out of LUTs, so reduce the number of breakpoints
from 4 to 1.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-21 13:47:11 +08:00
Sean Cross
6f7ce8a1ae
hw: foboot-bitstream: use -dffe_min_ce_use 5
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This is required to get it to fit for now.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-21 13:46:43 +08:00
Sean Cross
49a7197f7c
sw: generated: add latest csr.h file
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-21 13:01:37 +08:00
Sean Cross
eefa76706b
hw: foboot-bitstream: remove bbspi
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It isn't used anymore, and is just making the file bigger.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-21 12:34:54 +08:00
Sean Cross
a363e25b76
sw: time: rename SYSTEM_CLOCK_FREQUENCY to CONFIG_CLOCK_FREQUENCY
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This changed in litex.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-21 12:29:20 +08:00
Sean Cross
2b9f9612d8
hw: deps: use latest litex
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This will enable us to have spiflash working later on.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-21 12:27:03 +08:00
Sean Cross
425787484d
hw: deps: fix metastability with new valentyusb
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The new valentyusb fixes metastability in the tx and rx path.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-21 12:26:34 +08:00
Sean Cross
4156f6c376
Merge branch 'timing-fixup'
2019-07-21 12:22:04 +08:00
Sean Cross
c72a987a5d
hw: foboot-bitstream: set min_ce_use to 4
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This matches the comment, and shouldn't have any effect on the
resulting output.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-21 12:20:30 +08:00
Sean Cross
e7b55338be
hw: foboot-bitstream: hardcode memory map
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Rather than relying on the memory map from litex, hardcode the
memory offsets.
This is required because sometimes the litex memory map changes,
and we want to have a consistent offset across builds.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-21 12:19:13 +08:00
Sean Cross
bd08f0bb06
hw: foboot-bitstream: correct spi pin mappings for "dq"
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The "dq" mappings for SPI were wrong, and wouldn't work with the
SPI flash in dual/quad mode. Correct these mappings for all platforms.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-21 12:17:19 +08:00
Sean Cross
1e34d27f47
hw: foboot-bitstream: don't hardcode sram offset
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Use the values from the memory map instead of hardcoding the offset.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-21 12:15:13 +08:00
Sean Cross
a45b6be459
hw: foboot-bitstream: use buffered output from pll
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The PLL has two outputs: buffered and unbuffered. Take the clock
signal from the buffered output.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-21 12:13:30 +08:00
Sean Cross
ee30de7946
hw: foboot-bitstream: use all 13 bits of the clock reset
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There are 13 bits on the clock reset line, but right now we only use
12 of them. Set the counter to 8191 so we take advantage of
all 13 bits.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-21 12:12:41 +08:00
Sean Cross
8c84afa4d9
hw: bitstream: add dummyusb if no cpu is present
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This will allow us to still access the wishbone bus without a CPU.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-20 16:29:48 +08:00
Sean Cross
e1a1b60821
hw: foboot-bitstream: use GENCLK_HALF from PLL
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This removes a double-flop that we were using to get a 12 MHz clock,
which we were then multiplying back up to 48 MHz.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-20 16:15:02 +08:00
Sean Cross
541c765198
hw: foboot-bitstream: fix --no-cpu flag
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If there is no CPU, then don't adjust the CPU reset vector.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-20 16:14:35 +08:00
Sean Cross
7452fe05eb
releases: release v1.8.6
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-09 13:42:45 +08:00
Sean Cross
eed9897cfc
litex: pull latest spi flash changes
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-08 14:14:14 +08:00
Sean Cross
a4a3dad324
hw: fix led ordering on hacker board and add id to "version"
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Fix the ordering of the LEDs on the "hacker" board.
Add a "model id" to the "version" block.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-08 12:14:39 +08:00
Sean Cross
10454fa0be
sbled: fix mapping of r,g,b and add bit-bang mode
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Fix the mapping of red, green, and blue. Now the LEDDPWRR, LEDDPWRG,
and LEDDPWRB map to their correct values.
Additionally, a bit-banged mode for the LED has been added to enable
fine-grained control in a simpler manner.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-08 10:13:09 +08:00
Sean Cross
c622551300
Merge pull request #15 from TomKeddie/tomk_20190701_flashaddr
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Flash mapping address fixes
2019-07-07 09:20:57 +08:00
Sean Cross
a60b909b88
releases: add bios for v1.8.5
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-06 17:26:32 +08:00
Sean Cross
c7aafa3865
releases: add v1.8.5
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-06 17:25:38 +08:00
Sean Cross
5468cb914a
sw: spi: remove lots of dual/quad/qpi code
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This is an effort to fix boards that go into RO mode on their own.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-05 15:23:04 +08:00
Sean Cross
f070b2ab7c
release: add v1.8.4
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-04 16:50:38 +08:00
Sean Cross
d1cd68c232
hw: set debug bridge memory size to 0x100
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Hardware breakpoints live at offset 0x40 from the start of this region,
so increase the size from 0x10 to 0x100.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-04 16:39:28 +08:00
Sean Cross
c5b45a4314
Merge branch 'master' of github.com:im-tomu/foboot
2019-07-03 18:13:09 +08:00
Sean Cross
6e0f255b7e
releases: add v1.8.3
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This has been tested on machines that were failing with v1.8.1, and is
reliable.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-03 18:12:36 +08:00
Sean Cross
a40dc8a570
Merge pull request #14 from TomKeddie/master
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Create FLASHLAYOUT.md
2019-07-03 18:09:44 +08:00
Tom Keddie
1c8c1f3bc1
Flash mapping address fixes
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- too many bits were allocated causing problems addressing 128Mbit devices
- the shift operator in python generates a signed shift in verilog which potentilly trashes the upper address bit, switch to padding
2019-07-03 02:59:20 -07:00
Sean Cross
be187f10d1
fix u16 name size from previous patch
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Since it's a u16, we must remove two bytes not one.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-03 17:58:50 +08:00
Tom Keddie
841627d02f
Create FLASHLAYOUT.md
2019-07-03 02:54:19 -07:00
Sean Cross
f3f4971e09
sw: usb_desc: don't count trailing NULL in string len
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-03 17:36:24 +08:00
Tim Ansell
1033016932
Merge pull request #13 from TomKeddie/tomk_20190630_warnings
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sw: Fix warnings in dfu.h and usb-dev.c
2019-06-30 19:27:02 -07:00
Tom Keddie
9be328ead9
sw : fix warning in dfu.h and usb-dev.c
2019-06-30 18:28:05 -07:00
Sean Cross
520de140f7
README: correct documentation on "dfu-util -e"
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It's no longer required.
This addresses #11 .
Signed-off-by: Sean Cross <sean@xobs.io>
2019-06-25 09:14:25 -07:00
Sean Cross
0c8a8ba08e
releases: add hacker installable file
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-06-23 13:44:33 -07:00
Sean Cross
a60ed055fe
examples: usb-cdcacm: correct arch
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Use the correct architecture (no -m).
Signed-off-by: Sean Cross <sean@xobs.io>
2019-06-19 14:28:20 -07:00
Sean Cross
6b612211f4
examples: riscv-blink: fix cpu model and remove mul/div
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mul/div aren't needed, since we include stdlib now. Additionally, now
that we have the CPU model specified correctly, the correct files are
linked in as necessary.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-06-19 14:26:58 -07:00
Sean Cross
79fc2f6f5b
examples: usb-cdcacm: update usb id and csr.h
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Use the latest IDs and csr.h file for the cdcacm example.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-06-19 14:10:52 -07:00
Sean Cross
a758882e05
examples: riscv-blink: sync csr.h file
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This file has been updated. There shouldn't be functional changes, but
as an example project it's important to have the latest version.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-06-19 14:08:31 -07:00
Sean Cross
b41f4930cf
csr: include generated macro for bitstream sync
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The ICE40 bitstream sync byte is now available as a macro in csr.h.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-06-19 14:06:32 -07:00
Sean Cross
b051784a2c
examples: riscv-blink: fix building on rpi
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Make sure we look for the correct compiler.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-06-19 14:06:01 -07:00
Sean Cross
f2084ea817
hw: foboot-bitstream: tab -> spaces
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I wonder how that got in there...
Signed-off-by: Sean Cross <sean@xobs.io>
2019-06-19 14:05:29 -07:00
Sean Cross
61d912b9fc
valentyusb: update to include dummyusb fixes
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-06-19 12:38:47 -07:00
Sean Cross
5fe9a814ea
sw: support riscv64 on raspberry pi
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The name of the compiler has changed on raspberry pi, so support the
previous name as well as the new one.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-06-19 08:20:43 -07:00
Sean Cross
62efe31608
gitattributes: add c and header files
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-06-18 19:45:27 -07:00
Sean Cross
4d40bb5f18
sw: update csr.h to release version
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-06-18 19:45:04 -07:00