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d147af1e6a
We're trying to improve performance and reduce core size. This uses a newer version of the vexriscv core. It has a shorter pipeline, with better exception handling. It also properly initializes registers. Signed-off-by: Sean Cross <sean@xobs.io>
6 lines
202 B
YAML
6 lines
202 B
YAML
debug: !!vexriscv.DebugReport {hardwareBreakpointCount: 4}
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iBus: !!vexriscv.BusReport
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flushInstructions: [4111, 19, 19, 19]
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info: !!vexriscv.CacheReport {bytePerLine: 32, size: 2048}
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kind: cached
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