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History

umarcor ed9c146652 mixed-hdl: remove '-q' from yosys call Co-authored-by: T. Meissner <programming@goodcleanfun.de>		2020-10-13 21:29:30 +02:00
..
blink.v	add mixed-hdl/blink	2020-10-12 19:58:46 +02:00
blink.vhd	mixed-hdl: keyword 'component' is not required when instantiating	2020-10-13 21:27:21 +02:00
clkgen.v	add mixed-hdl/blink	2020-10-12 19:58:46 +02:00
clkgen.vhd	add mixed-hdl/blink	2020-10-12 19:58:46 +02:00
Makefile	mixed-hdl: remove '-q' from yosys call	2020-10-13 21:29:30 +02:00
README.md	add mixed-hdl/blink	2020-10-12 19:58:46 +02:00

README.md

Minimal Mixed HDL Example (VHDL and Verilog)

A minimal mixed HDL example which simply blinks the RGB LEDs at different frequencies.

This example contains equivalent sources in VHDL and Verilog, which can be combined freely:

blink.vhd + clkgen.v
blink.v + clkgen.vhdl
blink.vhd + clkgen.vhdl
blink.v + clkgen.v

All four cases produce exactly the same result, because the same design is described regardless of the HDL language used. In the makefile, the first case is built by default.

Using

Type make to build the DFU image. Type make load to load the DFU image onto the Fomu board. Type make clean to remove all the generated files.