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<h1>hal_lld_f103.h</h1> </div>
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<a href="hal__lld__f103_8h.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/*</span>
2010-08-10 03:11:02 +00:00
<a name="l00002"></a>00002 <span class="comment"> ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.</span>
<a name="l00003"></a>00003 <span class="comment"></span>
<a name="l00004"></a>00004 <span class="comment"> This file is part of ChibiOS/RT.</span>
<a name="l00005"></a>00005 <span class="comment"></span>
<a name="l00006"></a>00006 <span class="comment"> ChibiOS/RT is free software; you can redistribute it and/or modify</span>
<a name="l00007"></a>00007 <span class="comment"> it under the terms of the GNU General Public License as published by</span>
<a name="l00008"></a>00008 <span class="comment"> the Free Software Foundation; either version 3 of the License, or</span>
<a name="l00009"></a>00009 <span class="comment"> (at your option) any later version.</span>
<a name="l00010"></a>00010 <span class="comment"></span>
<a name="l00011"></a>00011 <span class="comment"> ChibiOS/RT is distributed in the hope that it will be useful,</span>
<a name="l00012"></a>00012 <span class="comment"> but WITHOUT ANY WARRANTY; without even the implied warranty of</span>
<a name="l00013"></a>00013 <span class="comment"> MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span>
<a name="l00014"></a>00014 <span class="comment"> GNU General Public License for more details.</span>
<a name="l00015"></a>00015 <span class="comment"></span>
<a name="l00016"></a>00016 <span class="comment"> You should have received a copy of the GNU General Public License</span>
<a name="l00017"></a>00017 <span class="comment"> along with this program. If not, see &lt;http://www.gnu.org/licenses/&gt;.</span>
<a name="l00018"></a>00018 <span class="comment"></span>
<a name="l00019"></a>00019 <span class="comment"> ---</span>
<a name="l00020"></a>00020 <span class="comment"></span>
<a name="l00021"></a>00021 <span class="comment"> A special exception to the GPL can be applied should you wish to distribute</span>
<a name="l00022"></a>00022 <span class="comment"> a combined work that includes ChibiOS/RT, without being obliged to provide</span>
<a name="l00023"></a>00023 <span class="comment"> the source code for any proprietary components. See the file exception.txt</span>
<a name="l00024"></a>00024 <span class="comment"> for full details of how and when the exception can be applied.</span>
<a name="l00025"></a>00025 <span class="comment">*/</span>
<a name="l00026"></a>00026 <span class="comment"></span>
<a name="l00027"></a>00027 <span class="comment">/**</span>
<a name="l00028"></a>00028 <span class="comment"> * @file STM32/hal_lld_f103.h</span>
<a name="l00029"></a>00029 <span class="comment"> * @brief STM32F103 HAL subsystem low level driver header.</span>
<a name="l00030"></a>00030 <span class="comment"> *</span>
<a name="l00031"></a>00031 <span class="comment"> * @addtogroup STM32F103_HAL</span>
<a name="l00032"></a>00032 <span class="comment"> * @{</span>
<a name="l00033"></a>00033 <span class="comment"> */</span>
<a name="l00034"></a>00034
<a name="l00035"></a>00035 <span class="preprocessor">#ifndef _HAL_LLD_F103_H_</span>
<a name="l00036"></a>00036 <span class="preprocessor"></span><span class="preprocessor">#define _HAL_LLD_F103_H_</span>
<a name="l00037"></a>00037 <span class="preprocessor"></span>
<a name="l00038"></a>00038 <span class="comment">/*===========================================================================*/</span>
<a name="l00039"></a>00039 <span class="comment">/* Driver constants. */</span>
<a name="l00040"></a>00040 <span class="comment">/*===========================================================================*/</span>
<a name="l00041"></a>00041
<a name="l00042"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga65c12bc7160ab579eaeee40ec2915110">00042</a> <span class="preprocessor">#define STM32_HSICLK 8000000 </span><span class="comment">/**&lt; High speed internal clock. */</span>
<a name="l00043"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga90421650b988332462db9a08815efb6f">00043</a> <span class="preprocessor">#define STM32_LSICLK 40000 </span><span class="comment">/**&lt; Low speed internal clock. */</span>
<a name="l00044"></a>00044
<a name="l00045"></a>00045 <span class="comment">/* RCC_CFGR register bits definitions.*/</span>
<a name="l00046"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga6a49bf4388f3acf15661252b3bb7547b">00046</a> <span class="preprocessor">#define STM32_SW_HSI (0 &lt;&lt; 0) </span><span class="comment">/**&lt; SYSCLK source is HSI. */</span>
<a name="l00047"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gab5b581bd1ff4fd48fc8c5f093ca776ca">00047</a> <span class="preprocessor">#define STM32_SW_HSE (1 &lt;&lt; 0) </span><span class="comment">/**&lt; SYSCLK source is HSE. */</span>
<a name="l00048"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga8bc74f08245bf796555d33a86afd9fc4">00048</a> <span class="preprocessor">#define STM32_SW_PLL (2 &lt;&lt; 0) </span><span class="comment">/**&lt; SYSCLK source is PLL. */</span>
<a name="l00049"></a>00049
<a name="l00050"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gabf2bcd341b2140b7a82ff24b92f6af68">00050</a> <span class="preprocessor">#define STM32_HPRE_DIV1 (0 &lt;&lt; 4) </span><span class="comment">/**&lt; SYSCLK divided by 1. */</span>
<a name="l00051"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga6dfcd5149eb88f1681b4defc77f4d8b2">00051</a> <span class="preprocessor">#define STM32_HPRE_DIV2 (8 &lt;&lt; 4) </span><span class="comment">/**&lt; SYSCLK divided by 2. */</span>
<a name="l00052"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gaeb5f7cce4d1b6646f7e48d2784aade1c">00052</a> <span class="preprocessor">#define STM32_HPRE_DIV4 (9 &lt;&lt; 4) </span><span class="comment">/**&lt; SYSCLK divided by 4. */</span>
<a name="l00053"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gaaa6b23363a848239b048cde5b565e2d5">00053</a> <span class="preprocessor">#define STM32_HPRE_DIV8 (10 &lt;&lt; 4) </span><span class="comment">/**&lt; SYSCLK divided by 8. */</span>
<a name="l00054"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gaab6772439c76981e1c1d23bf97ec3910">00054</a> <span class="preprocessor">#define STM32_HPRE_DIV16 (11 &lt;&lt; 4) </span><span class="comment">/**&lt; SYSCLK divided by 16. */</span>
<a name="l00055"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga152f3c2eabcc96019194c85bb2f7f2af">00055</a> <span class="preprocessor">#define STM32_HPRE_DIV64 (12 &lt;&lt; 4) </span><span class="comment">/**&lt; SYSCLK divided by 64. */</span>
<a name="l00056"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga6ea1e82317d266fa344d6787f485e991">00056</a> <span class="preprocessor">#define STM32_HPRE_DIV128 (13 &lt;&lt; 4) </span><span class="comment">/**&lt; SYSCLK divided by 128. */</span>
<a name="l00057"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga7099ae3ddeb74537f4a34f1e36730dbe">00057</a> <span class="preprocessor">#define STM32_HPRE_DIV256 (14 &lt;&lt; 4) </span><span class="comment">/**&lt; SYSCLK divided by 256. */</span>
<a name="l00058"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gaac6d223ccd51614bd3c8f354b16e4671">00058</a> <span class="preprocessor">#define STM32_HPRE_DIV512 (15 &lt;&lt; 4) </span><span class="comment">/**&lt; SYSCLK divided by 512. */</span>
<a name="l00059"></a>00059
<a name="l00060"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga3c9ece8fc206039d5723f8016adb789d">00060</a> <span class="preprocessor">#define STM32_PPRE1_DIV1 (0 &lt;&lt; 8) </span><span class="comment">/**&lt; HCLK divided by 1. */</span>
<a name="l00061"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gae205bae3cec6b45723d687bc2b7a4e38">00061</a> <span class="preprocessor">#define STM32_PPRE1_DIV2 (4 &lt;&lt; 8) </span><span class="comment">/**&lt; HCLK divided by 2. */</span>
<a name="l00062"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga18b34bc52ebebd209fffb01002b2bc98">00062</a> <span class="preprocessor">#define STM32_PPRE1_DIV4 (5 &lt;&lt; 8) </span><span class="comment">/**&lt; HCLK divided by 4. */</span>
<a name="l00063"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gab7b100956dae0246dd9faa0a54010b17">00063</a> <span class="preprocessor">#define STM32_PPRE1_DIV8 (6 &lt;&lt; 8) </span><span class="comment">/**&lt; HCLK divided by 8. */</span>
<a name="l00064"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga750b0ba24dbebb1fac1a3b2330666350">00064</a> <span class="preprocessor">#define STM32_PPRE1_DIV16 (7 &lt;&lt; 8) </span><span class="comment">/**&lt; HCLK divided by 16. */</span>
<a name="l00065"></a>00065
<a name="l00066"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga9883bc736b03534d09789f13a6026c31">00066</a> <span class="preprocessor">#define STM32_PPRE2_DIV1 (0 &lt;&lt; 11) </span><span class="comment">/**&lt; HCLK divided by 1. */</span>
<a name="l00067"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga55e0199e60c0551b8fae6b8eb49d6364">00067</a> <span class="preprocessor">#define STM32_PPRE2_DIV2 (4 &lt;&lt; 11) </span><span class="comment">/**&lt; HCLK divided by 2. */</span>
<a name="l00068"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gaa85c01042fcee21da997473f4f42ba78">00068</a> <span class="preprocessor">#define STM32_PPRE2_DIV4 (5 &lt;&lt; 11) </span><span class="comment">/**&lt; HCLK divided by 4. */</span>
<a name="l00069"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga0db040c759cc09cee6261301a952d862">00069</a> <span class="preprocessor">#define STM32_PPRE2_DIV8 (6 &lt;&lt; 11) </span><span class="comment">/**&lt; HCLK divided by 8. */</span>
<a name="l00070"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gaf986782e091335aeaf0235635d20353d">00070</a> <span class="preprocessor">#define STM32_PPRE2_DIV16 (7 &lt;&lt; 11) </span><span class="comment">/**&lt; HCLK divided by 16. */</span>
<a name="l00071"></a>00071
<a name="l00072"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gaedf6c315cac4eed84eefb906f11909d5">00072</a> <span class="preprocessor">#define STM32_ADCPRE_DIV2 (0 &lt;&lt; 14) </span><span class="comment">/**&lt; HCLK divided by 2. */</span>
<a name="l00073"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gac85f817c97ee65cef48408aae15a4275">00073</a> <span class="preprocessor">#define STM32_ADCPRE_DIV4 (1 &lt;&lt; 14) </span><span class="comment">/**&lt; HCLK divided by 4. */</span>
<a name="l00074"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gad628210302793a5ffdd7a92515c2d3a1">00074</a> <span class="preprocessor">#define STM32_ADCPRE_DIV6 (2 &lt;&lt; 14) </span><span class="comment">/**&lt; HCLK divided by 6. */</span>
<a name="l00075"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gacc4296ec001b1f54da48a503c68af27a">00075</a> <span class="preprocessor">#define STM32_ADCPRE_DIV8 (3 &lt;&lt; 14) </span><span class="comment">/**&lt; HCLK divided by 8. */</span>
<a name="l00076"></a>00076
<a name="l00077"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gac8438d5c9b3c6bfd0346e1026b8055fc">00077</a> <span class="preprocessor">#define STM32_PLLSRC_HSI (0 &lt;&lt; 16) </span><span class="comment">/**&lt; PLL clock source is HSI. */</span>
<a name="l00078"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga64328eed4cc2c355aab176e0beb31b63">00078</a> <span class="preprocessor">#define STM32_PLLSRC_HSE (1 &lt;&lt; 16) </span><span class="comment">/**&lt; PLL clock source is HSE. */</span>
<a name="l00079"></a>00079
<a name="l00080"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga70455e18b40c7dc6fd0a2a2dc32df2b2">00080</a> <span class="preprocessor">#define STM32_PLLXTPRE_DIV1 (0 &lt;&lt; 17) </span><span class="comment">/**&lt; HSE divided by 1. */</span>
<a name="l00081"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga1e7e686a70079862ff8e7e14d9d85124">00081</a> <span class="preprocessor">#define STM32_PLLXTPRE_DIV2 (1 &lt;&lt; 17) </span><span class="comment">/**&lt; HSE divided by 2. */</span>
<a name="l00082"></a>00082
<a name="l00083"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga89cb88c836f543f0133cb923d24b8ac2">00083</a> <span class="preprocessor">#define STM32_MCO_NOCLOCK (0 &lt;&lt; 24) </span><span class="comment">/**&lt; No clock on MCO pin. */</span>
<a name="l00084"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga88dd4d9fea9a7de30ff26dfc73b2dca7">00084</a> <span class="preprocessor">#define STM32_MCO_SYSCLK (4 &lt;&lt; 24) </span><span class="comment">/**&lt; SYSCLK on MCO pin. */</span>
<a name="l00085"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gaa208624a69b4a031b7ce4b9bf41a0dac">00085</a> <span class="preprocessor">#define STM32_MCO_HSI (5 &lt;&lt; 24) </span><span class="comment">/**&lt; HSI clock on MCO pin. */</span>
<a name="l00086"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga881bbb9fb274aaa98a69c6fcc64a92ab">00086</a> <span class="preprocessor">#define STM32_MCO_HSE (6 &lt;&lt; 24) </span><span class="comment">/**&lt; HSE clock on MCO pin. */</span>
<a name="l00087"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga1c0494e40e6a7a032b259209fb69a802">00087</a> <span class="preprocessor">#define STM32_MCO_PLLDIV2 (7 &lt;&lt; 24) </span><span class="comment">/**&lt; PLL/2 clock on MCO pin. */</span>
<a name="l00088"></a>00088
<a name="l00089"></a>00089 <span class="comment">/*===========================================================================*/</span>
<a name="l00090"></a>00090 <span class="comment">/* Platform specific friendly IRQ names. */</span>
<a name="l00091"></a>00091 <span class="comment">/*===========================================================================*/</span>
<a name="l00092"></a>00092
<a name="l00093"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gad4c8a013e3354da6d132cdb91a481c3c">00093</a> <span class="preprocessor">#define WWDG_IRQHandler Vector40 </span><span class="comment">/**&lt; Window Watchdog. */</span>
<a name="l00094"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga045476dfaec8c84f5e16b06b937c0c18">00094</a> <span class="preprocessor">#define PVD_IRQHandler Vector44 </span><span class="comment">/**&lt; PVD through EXTI Line</span>
<a name="l00095"></a>00095 <span class="comment"> detect. */</span>
<a name="l00096"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga3668bf2c1d66bea024e3ff1cc7f9952c">00096</a> <span class="preprocessor">#define TAMPER_IRQHandler Vector48 </span><span class="comment">/**&lt; Tamper. */</span>
<a name="l00097"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gaeadad366a84e3b496a18ef919a28342b">00097</a> <span class="preprocessor">#define RTC_IRQHandler Vector4C </span><span class="comment">/**&lt; RTC. */</span>
<a name="l00098"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga3cca2eaebb146655fb72e09adee7839d">00098</a> <span class="preprocessor">#define FLASH_IRQHandler Vector50 </span><span class="comment">/**&lt; Flash. */</span>
<a name="l00099"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga5a6d083fa78461da86a717b28973e009">00099</a> <span class="preprocessor">#define RCC_IRQHandler Vector54 </span><span class="comment">/**&lt; RCC. */</span>
<a name="l00100"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gac468127e2887086eeafd0fc5044c8c1f">00100</a> <span class="preprocessor">#define EXTI0_IRQHandler Vector58 </span><span class="comment">/**&lt; EXTI Line 0. */</span>
<a name="l00101"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga0580c4052329cca57bede85ffff29de5">00101</a> <span class="preprocessor">#define EXTI1_IRQHandler Vector5C </span><span class="comment">/**&lt; EXTI Line 1. */</span>
<a name="l00102"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gae39f987c5ace4c480d23ea000ed53f6e">00102</a> <span class="preprocessor">#define EXTI2_IRQHandler Vector60 </span><span class="comment">/**&lt; EXTI Line 2. */</span>
<a name="l00103"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga6227b0b9333e766db47c3e86d57b8a4f">00103</a> <span class="preprocessor">#define EXTI3_IRQHandler Vector64 </span><span class="comment">/**&lt; EXTI Line 3. */</span>
<a name="l00104"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gab7dcb33a5cf9254fd25f8619c6c92ab8">00104</a> <span class="preprocessor">#define EXTI4_IRQHandler Vector68 </span><span class="comment">/**&lt; EXTI Line 4. */</span>
<a name="l00105"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga3f7debe9fc2548ab6640825967110101">00105</a> <span class="preprocessor">#define DMA1_Ch1_IRQHandler Vector6C </span><span class="comment">/**&lt; DMA1 Channel 1. */</span>
<a name="l00106"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga37d95c99d84753e4efe4909bbaae4fa1">00106</a> <span class="preprocessor">#define DMA1_Ch2_IRQHandler Vector70 </span><span class="comment">/**&lt; DMA1 Channel 2. */</span>
<a name="l00107"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gaa3a67d36319fc3c153999ebbb0e0cd49">00107</a> <span class="preprocessor">#define DMA1_Ch3_IRQHandler Vector74 </span><span class="comment">/**&lt; DMA1 Channel 3. */</span>
<a name="l00108"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga76bb91040587d17a396ccb31395aa0e5">00108</a> <span class="preprocessor">#define DMA1_Ch4_IRQHandler Vector78 </span><span class="comment">/**&lt; DMA1 Channel 4. */</span>
<a name="l00109"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gadbe5dfd4aed18b04f864d5fbed32f438">00109</a> <span class="preprocessor">#define DMA1_Ch5_IRQHandler Vector7C </span><span class="comment">/**&lt; DMA1 Channel 5. */</span>
<a name="l00110"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga39b427886b2c2d2c7ce3be9537c1f6a2">00110</a> <span class="preprocessor">#define DMA1_Ch6_IRQHandler Vector80 </span><span class="comment">/**&lt; DMA1 Channel 6. */</span>
<a name="l00111"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gaecfa962ef95ba5a06ad60ac57e8a54ec">00111</a> <span class="preprocessor">#define DMA1_Ch7_IRQHandler Vector84 </span><span class="comment">/**&lt; DMA1 Channel 7. */</span>
<a name="l00112"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gabc7315be5ac997b8f347fe1e22f58adf">00112</a> <span class="preprocessor">#define ADC1_2_IRQHandler Vector88 </span><span class="comment">/**&lt; ADC1_2. */</span>
2010-11-22 05:53:37 +00:00
<a name="l00113"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga4fdbecfed2cdeadfec6210f7ec510fbc">00113</a> <span class="preprocessor">#define CAN1_TX_IRQHandler Vector8C </span><span class="comment">/**&lt; CAN1 TX. */</span>
<a name="l00114"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gab62271824915d04d5350da852b32cd5e">00114</a> <span class="preprocessor">#define USB_HP_IRQHandler Vector8C </span><span class="comment">/**&lt; USB High Priority, CAN1 TX.*/</span>
<a name="l00115"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga40873fbdcb268642576f45babaad5c2e">00115</a> <span class="preprocessor">#define CAN1_RX0_IRQHandler Vector90 </span><span class="comment">/**&lt; CAN1 RX0. */</span>
<a name="l00116"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gab5032057a517201938fc126d12690f4e">00116</a> <span class="preprocessor">#define USB_LP_IRQHandler Vector90 </span><span class="comment">/**&lt; USB Low Priority, CAN1 RX0.*/</span>
<a name="l00117"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga8550c9680a59f697a018b283878b0648">00117</a> <span class="preprocessor">#define CAN1_RX1_IRQHandler Vector94 </span><span class="comment">/**&lt; CAN1 RX1. */</span>
<a name="l00118"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gab6a0b35d117d66c63172d56a59ce2e20">00118</a> <span class="preprocessor">#define CAN1_SCE_IRQHandler Vector98 </span><span class="comment">/**&lt; CAN1 SCE. */</span>
<a name="l00119"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gab2efac0867c3c975ea4ea586013b10ce">00119</a> <span class="preprocessor">#define EXTI9_5_IRQHandler Vector9C </span><span class="comment">/**&lt; EXTI Line 9..5. */</span>
<a name="l00120"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga2f33687cec484ac054656b3a9daca2c1">00120</a> <span class="preprocessor">#define TIM1_BRK_IRQHandler VectorA0 </span><span class="comment">/**&lt; TIM1 Break. */</span>
<a name="l00121"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga578b4afc3dd6695f66e1b7a116c33d41">00121</a> <span class="preprocessor">#define TIM1_UP_IRQHandler VectorA4 </span><span class="comment">/**&lt; TIM1 Update. */</span>
<a name="l00122"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga029af7575a43b2c3c6b50c62571ed21c">00122</a> <span class="preprocessor">#define TIM1_TRG_COM_IRQHandler VectorA8 </span><span class="comment">/**&lt; TIM1 Trigger and</span>
<a name="l00123"></a>00123 <span class="comment"> Commutation. */</span>
<a name="l00124"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga3f167d3dabac4824347885babe86926f">00124</a> <span class="preprocessor">#define TIM1_CC_IRQHandler VectorAC </span><span class="comment">/**&lt; TIM1 Capture Compare. */</span>
<a name="l00125"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga499bdce3f1172d391e9565e9f9d07a76">00125</a> <span class="preprocessor">#define TIM2_IRQHandler VectorB0 </span><span class="comment">/**&lt; TIM2. */</span>
<a name="l00126"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga8e5c20e41d6d555efd718fc29037cc26">00126</a> <span class="preprocessor">#define TIM3_IRQHandler VectorB4 </span><span class="comment">/**&lt; TIM3. */</span>
<a name="l00127"></a>00127 <span class="preprocessor">#if defined(STM32F10X_MD) || defined(STM32F10X_HD) || defined(__DOXYGEN__)</span>
<a name="l00128"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga582fbd8d35d9280347b55cd12f65c213">00128</a> <span class="preprocessor"></span><span class="preprocessor">#define TIM4_IRQHandler VectorB8 </span><span class="comment">/**&lt; TIM4. */</span>
<a name="l00129"></a>00129 <span class="preprocessor">#endif</span>
<a name="l00130"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga83e61d3d4eb31c12a4369f6b1d9fa742">00130</a> <span class="preprocessor"></span><span class="preprocessor">#define I2C1_EV_IRQHandler VectorBC </span><span class="comment">/**&lt; I2C1 Event. */</span>
<a name="l00131"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gad8e382b9ce2bb267c7414c7185637654">00131</a> <span class="preprocessor">#define I2C1_ER_IRQHandler VectorC0 </span><span class="comment">/**&lt; I2C1 Error. */</span>
<a name="l00132"></a>00132 <span class="preprocessor">#if defined(STM32F10X_MD) || defined(STM32F10X_HD) || defined(__DOXYGEN__)</span>
<a name="l00133"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga0b8dacb7ac76cfc954fd0db2d5e53025">00133</a> <span class="preprocessor"></span><span class="preprocessor">#define I2C2_EV_IRQHandler VectorC4 </span><span class="comment">/**&lt; I2C2 Event. */</span>
<a name="l00134"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga1a98d05b127fa293a1210397bda82007">00134</a> <span class="preprocessor">#define I2C2_ER_IRQHandler VectorC8 </span><span class="comment">/**&lt; I2C2 Error. */</span>
<a name="l00135"></a>00135 <span class="preprocessor">#endif</span>
<a name="l00136"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gadc38983c3ec1357840b21472ff1a2147">00136</a> <span class="preprocessor"></span><span class="preprocessor">#define SPI1_IRQHandler VectorCC </span><span class="comment">/**&lt; SPI1. */</span>
<a name="l00137"></a>00137 <span class="preprocessor">#if defined(STM32F10X_MD) || defined(STM32F10X_HD) || defined(__DOXYGEN__)</span>
<a name="l00138"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gaaace6fa425ba2038de9ce01755070057">00138</a> <span class="preprocessor"></span><span class="preprocessor">#define SPI2_IRQHandler VectorD0 </span><span class="comment">/**&lt; SPI2. */</span>
<a name="l00139"></a>00139 <span class="preprocessor">#endif</span>
<a name="l00140"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga23182c2feafd217668e6b37c126512a1">00140</a> <span class="preprocessor"></span><span class="preprocessor">#define USART1_IRQHandler VectorD4 </span><span class="comment">/**&lt; USART1. */</span>
<a name="l00141"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga484cf268e20400bfa2cf159fd86b98be">00141</a> <span class="preprocessor">#define USART2_IRQHandler VectorD8 </span><span class="comment">/**&lt; USART2. */</span>
<a name="l00142"></a>00142 <span class="preprocessor">#if defined(STM32F10X_MD) || defined(STM32F10X_HD) || defined(__DOXYGEN__)</span>
<a name="l00143"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga8a246e61ab1022b289c251e48f7094aa">00143</a> <span class="preprocessor"></span><span class="preprocessor">#define USART3_IRQHandler VectorDC </span><span class="comment">/**&lt; USART3. */</span>
<a name="l00144"></a>00144 <span class="preprocessor">#endif</span>
<a name="l00145"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga94d705608b3377724d368a6ce381c735">00145</a> <span class="preprocessor"></span><span class="preprocessor">#define EXTI15_10_IRQHandler VectorE0 </span><span class="comment">/**&lt; EXTI Line 15..10. */</span>
<a name="l00146"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga649ba5a31ccb8936b7bb9be165160be4">00146</a> <span class="preprocessor">#define RTCAlarm_IRQHandler VectorE4 </span><span class="comment">/**&lt; RTC Alarm through EXTI. */</span>
<a name="l00147"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga6b2574837ab61eb470ef0ed1974c2b06">00147</a> <span class="preprocessor">#define USBWakeUp_IRQHandler VectorE8 </span><span class="comment">/**&lt; USB Wakeup from suspend. */</span>
<a name="l00148"></a>00148 <span class="preprocessor">#if defined(STM32F10X_HD) || defined(__DOXYGEN__)</span>
<a name="l00149"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gac635c00a20e7eabe13729819a1da315c">00149</a> <span class="preprocessor"></span><span class="preprocessor">#define TIM8_BRK_IRQHandler VectorEC </span><span class="comment">/**&lt; TIM8 Break. */</span>
<a name="l00150"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga382f5f6851ef86ec4307b5ec06980e12">00150</a> <span class="preprocessor">#define TIM8_UP_IRQHandler VectorF0 </span><span class="comment">/**&lt; TIM8 Update. */</span>
<a name="l00151"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gacf84e2e666ecbfd5efef8805e8870f8e">00151</a> <span class="preprocessor">#define TIM8_TRG_COM_IRQHandler VectorF4 </span><span class="comment">/**&lt; TIM8 Trigger and</span>
<a name="l00152"></a>00152 <span class="comment"> Commutation. */</span>
<a name="l00153"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gaa757dea287f3017dd4829db7357aaf4c">00153</a> <span class="preprocessor">#define TIM8_CC_IRQHandler VectorF8 </span><span class="comment">/**&lt; TIM8 Capture Compare. */</span>
<a name="l00154"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gaeaaf5d1330ebfa99dc1baf2ebaadccaf">00154</a> <span class="preprocessor">#define ADC3_IRQHandler VectorFC </span><span class="comment">/**&lt; ADC3. */</span>
<a name="l00155"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga5b49d338a67aae8ff880596f373a1d58">00155</a> <span class="preprocessor">#define FSMC_IRQHandler Vector100 </span><span class="comment">/**&lt; FSMC. */</span>
<a name="l00156"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga44b56def4842b9f9ba6ce93e4dfe6361">00156</a> <span class="preprocessor">#define SDIO_IRQHandler Vector104 </span><span class="comment">/**&lt; SDIO. */</span>
<a name="l00157"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gab9fe80492ed4e0fa1fd6faf58bd58e4b">00157</a> <span class="preprocessor">#define TIM5_IRQHandler Vector108 </span><span class="comment">/**&lt; TIM5. */</span>
<a name="l00158"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gad9e1203f13593d969234331ceb55d7d2">00158</a> <span class="preprocessor">#define SPI3_IRQHandler Vector10C </span><span class="comment">/**&lt; SPI3. */</span>
<a name="l00159"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gac4b19b89f21dd7c2510cf3ad18f30550">00159</a> <span class="preprocessor">#define UART4_IRQHandler Vector110 </span><span class="comment">/**&lt; UART4. */</span>
<a name="l00160"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga3b377c7a7064b3dad2e2ef423f786786">00160</a> <span class="preprocessor">#define UART5_IRQHandler Vector114 </span><span class="comment">/**&lt; UART5. */</span>
<a name="l00161"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gae30e35a563a952a284f3f54d7f164ccd">00161</a> <span class="preprocessor">#define TIM6_IRQHandler Vector118 </span><span class="comment">/**&lt; TIM6. */</span>
<a name="l00162"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gaf58f7701209700015c8090b7904e5e3e">00162</a> <span class="preprocessor">#define TIM7_IRQHandler Vector11C </span><span class="comment">/**&lt; TIM7. */</span>
<a name="l00163"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga59e42b422ce23eb466d067abbd0098ea">00163</a> <span class="preprocessor">#define DMA2_Ch1_IRQHandler Vector120 </span><span class="comment">/**&lt; DMA2 Channel1. */</span>
<a name="l00164"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gae86b2cc4ca778cf1922b28e0fa0957d8">00164</a> <span class="preprocessor">#define DMA2_Ch2_IRQHandler Vector124 </span><span class="comment">/**&lt; DMA2 Channel2. */</span>
<a name="l00165"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gad3cdd76c6987693a2aeeb7ceb0c470dc">00165</a> <span class="preprocessor">#define DMA2_Ch3_IRQHandler Vector128 </span><span class="comment">/**&lt; DMA2 Channel3. */</span>
<a name="l00166"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gaf4dbbedea451647a29ff2d31903b5388">00166</a> <span class="preprocessor">#define DMA2_Ch4_5_IRQHandler Vector12C </span><span class="comment">/**&lt; DMA2 Channel4 &amp; Channel5. */</span>
<a name="l00167"></a>00167 <span class="preprocessor">#endif</span>
<a name="l00168"></a>00168 <span class="preprocessor"></span>
2010-08-10 03:11:02 +00:00
<a name="l00169"></a>00169 <span class="comment">/*===========================================================================*/</span>
2010-11-22 05:53:37 +00:00
<a name="l00170"></a>00170 <span class="comment">/* Driver pre-compile time settings. */</span>
<a name="l00171"></a>00171 <span class="comment">/*===========================================================================*/</span>
<a name="l00172"></a>00172 <span class="comment"></span>
<a name="l00173"></a>00173 <span class="comment">/**</span>
<a name="l00174"></a>00174 <span class="comment"> * @brief Main clock source selection.</span>
<a name="l00175"></a>00175 <span class="comment"> * @note If the selected clock source is not the PLL then the PLL is not</span>
<a name="l00176"></a>00176 <span class="comment"> * initialized and started.</span>
<a name="l00177"></a>00177 <span class="comment"> * @note The default value is calculated for a 72MHz system clock from</span>
<a name="l00178"></a>00178 <span class="comment"> * a 8MHz crystal using the PLL.</span>
<a name="l00179"></a>00179 <span class="comment"> */</span>
<a name="l00180"></a>00180 <span class="preprocessor">#if !defined(STM32_SW) || defined(__DOXYGEN__)</span>
<a name="l00181"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga29204b81c265dd6e124fbcf12a2c8d6f">00181</a> <span class="preprocessor"></span><span class="preprocessor">#define STM32_SW STM32_SW_PLL</span>
<a name="l00182"></a>00182 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
<a name="l00183"></a>00183 <span class="preprocessor"></span><span class="comment"></span>
<a name="l00184"></a>00184 <span class="comment">/**</span>
<a name="l00185"></a>00185 <span class="comment"> * @brief Clock source for the PLL.</span>
<a name="l00186"></a>00186 <span class="comment"> * @note This setting has only effect if the PLL is selected as the</span>
<a name="l00187"></a>00187 <span class="comment"> * system clock source.</span>
<a name="l00188"></a>00188 <span class="comment"> * @note The default value is calculated for a 72MHz system clock from</span>
<a name="l00189"></a>00189 <span class="comment"> * a 8MHz crystal using the PLL.</span>
<a name="l00190"></a>00190 <span class="comment"> */</span>
<a name="l00191"></a>00191 <span class="preprocessor">#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)</span>
<a name="l00192"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga811cfbd049f0ab00976def9593849d32">00192</a> <span class="preprocessor"></span><span class="preprocessor">#define STM32_PLLSRC STM32_PLLSRC_HSE</span>
<a name="l00193"></a>00193 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
<a name="l00194"></a>00194 <span class="preprocessor"></span><span class="comment"></span>
<a name="l00195"></a>00195 <span class="comment">/**</span>
<a name="l00196"></a>00196 <span class="comment"> * @brief Crystal PLL pre-divider.</span>
<a name="l00197"></a>00197 <span class="comment"> * @note This setting has only effect if the PLL is selected as the</span>
<a name="l00198"></a>00198 <span class="comment"> * system clock source.</span>
<a name="l00199"></a>00199 <span class="comment"> * @note The default value is calculated for a 72MHz system clock from</span>
<a name="l00200"></a>00200 <span class="comment"> * a 8MHz crystal using the PLL.</span>
<a name="l00201"></a>00201 <span class="comment"> */</span>
<a name="l00202"></a>00202 <span class="preprocessor">#if !defined(STM32_PLLXTPRE) || defined(__DOXYGEN__)</span>
<a name="l00203"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gad7443fb89c1569f264a218209fbe8ddd">00203</a> <span class="preprocessor"></span><span class="preprocessor">#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1</span>
<a name="l00204"></a>00204 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
<a name="l00205"></a>00205 <span class="preprocessor"></span><span class="comment"></span>
<a name="l00206"></a>00206 <span class="comment">/**</span>
<a name="l00207"></a>00207 <span class="comment"> * @brief PLL multiplier value.</span>
<a name="l00208"></a>00208 <span class="comment"> * @note The allowed range is 2...16.</span>
<a name="l00209"></a>00209 <span class="comment"> * @note The default value is calculated for a 72MHz system clock from</span>
<a name="l00210"></a>00210 <span class="comment"> * a 8MHz crystal using the PLL.</span>
<a name="l00211"></a>00211 <span class="comment"> */</span>
<a name="l00212"></a>00212 <span class="preprocessor">#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)</span>
<a name="l00213"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga0015fc8f73017358a7025ba57a265a11">00213</a> <span class="preprocessor"></span><span class="preprocessor">#define STM32_PLLMUL_VALUE 9</span>
<a name="l00214"></a>00214 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
<a name="l00215"></a>00215 <span class="preprocessor"></span><span class="comment"></span>
<a name="l00216"></a>00216 <span class="comment">/**</span>
<a name="l00217"></a>00217 <span class="comment"> * @brief AHB prescaler value.</span>
<a name="l00218"></a>00218 <span class="comment"> * @note The default value is calculated for a 72MHz system clock from</span>
<a name="l00219"></a>00219 <span class="comment"> * a 8MHz crystal using the PLL.</span>
<a name="l00220"></a>00220 <span class="comment"> */</span>
<a name="l00221"></a>00221 <span class="preprocessor">#if !defined(STM32_HPRE) || defined(__DOXYGEN__)</span>
<a name="l00222"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga035ea0d8259c0f89306c6a7d344705f2">00222</a> <span class="preprocessor"></span><span class="preprocessor">#define STM32_HPRE STM32_HPRE_DIV1</span>
<a name="l00223"></a>00223 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
<a name="l00224"></a>00224 <span class="preprocessor"></span><span class="comment"></span>
<a name="l00225"></a>00225 <span class="comment">/**</span>
<a name="l00226"></a>00226 <span class="comment"> * @brief APB1 prescaler value.</span>
<a name="l00227"></a>00227 <span class="comment"> */</span>
<a name="l00228"></a>00228 <span class="preprocessor">#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)</span>
<a name="l00229"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga5f9c3734d5d06c9ccd5214af5c78c4f8">00229</a> <span class="preprocessor"></span><span class="preprocessor">#define STM32_PPRE1 STM32_PPRE1_DIV2</span>
<a name="l00230"></a>00230 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
<a name="l00231"></a>00231 <span class="preprocessor"></span><span class="comment"></span>
<a name="l00232"></a>00232 <span class="comment">/**</span>
<a name="l00233"></a>00233 <span class="comment"> * @brief APB2 prescaler value.</span>
<a name="l00234"></a>00234 <span class="comment"> */</span>
<a name="l00235"></a>00235 <span class="preprocessor">#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)</span>
<a name="l00236"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga3670f3886d02bb3010016bbf0db0db83">00236</a> <span class="preprocessor"></span><span class="preprocessor">#define STM32_PPRE2 STM32_PPRE2_DIV2</span>
<a name="l00237"></a>00237 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
<a name="l00238"></a>00238 <span class="preprocessor"></span><span class="comment"></span>
<a name="l00239"></a>00239 <span class="comment">/**</span>
<a name="l00240"></a>00240 <span class="comment"> * @brief ADC prescaler value.</span>
<a name="l00241"></a>00241 <span class="comment"> */</span>
<a name="l00242"></a>00242 <span class="preprocessor">#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__)</span>
<a name="l00243"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga671b452f988ee9b64e128fad72f656e6">00243</a> <span class="preprocessor"></span><span class="preprocessor">#define STM32_ADCPRE STM32_ADCPRE_DIV4</span>
<a name="l00244"></a>00244 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
<a name="l00245"></a>00245 <span class="preprocessor"></span><span class="comment"></span>
<a name="l00246"></a>00246 <span class="comment">/**</span>
<a name="l00247"></a>00247 <span class="comment"> * @brief MCO pin setting.</span>
<a name="l00248"></a>00248 <span class="comment"> */</span>
<a name="l00249"></a>00249 <span class="preprocessor">#if !defined(STM32_MCO) || defined(__DOXYGEN__)</span>
<a name="l00250"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga5b24026a48ef156dcb642b6e55a68e02">00250</a> <span class="preprocessor"></span><span class="preprocessor">#define STM32_MCO STM32_MCO_NOCLOCK</span>
<a name="l00251"></a>00251 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
<a name="l00252"></a>00252 <span class="preprocessor"></span>
2010-08-10 03:11:02 +00:00
<a name="l00253"></a>00253 <span class="comment">/*===========================================================================*/</span>
2010-11-22 05:53:37 +00:00
<a name="l00254"></a>00254 <span class="comment">/* Derived constants and error checks. */</span>
<a name="l00255"></a>00255 <span class="comment">/*===========================================================================*/</span>
<a name="l00256"></a>00256
<a name="l00257"></a>00257 <span class="comment">/* HSE prescaler setting check.*/</span>
<a name="l00258"></a>00258 <span class="preprocessor">#if (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV1) &amp;&amp; \</span>
<a name="l00259"></a>00259 <span class="preprocessor"> (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV2)</span>
<a name="l00260"></a>00260 <span class="preprocessor"></span><span class="preprocessor">#error &quot;invalid STM32_PLLXTPRE value specified&quot;</span>
<a name="l00261"></a>00261 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
<a name="l00262"></a>00262 <span class="preprocessor"></span><span class="comment">/**</span>
<a name="l00263"></a>00263 <span class="comment"> * @brief PLLMUL field.</span>
<a name="l00264"></a>00264 <span class="comment"> */</span>
<a name="l00265"></a>00265 <span class="preprocessor">#if ((STM32_PLLMUL_VALUE &gt;= 2) &amp;&amp; (STM32_PLLMUL_VALUE &lt;= 16)) || \</span>
<a name="l00266"></a>00266 <span class="preprocessor"> defined(__DOXYGEN__)</span>
<a name="l00267"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga9889ca83d58a738f5758b4c300433f2a">00267</a> <span class="preprocessor"></span><span class="preprocessor">#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) &lt;&lt; 18)</span>
<a name="l00268"></a>00268 <span class="preprocessor"></span><span class="preprocessor">#else</span>
<a name="l00269"></a>00269 <span class="preprocessor"></span><span class="preprocessor">#error &quot;invalid STM32_PLLMUL_VALUE value specified&quot;</span>
<a name="l00270"></a>00270 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
<a name="l00271"></a>00271 <span class="preprocessor"></span><span class="comment"></span>
<a name="l00272"></a>00272 <span class="comment">/**</span>
<a name="l00273"></a>00273 <span class="comment"> * @brief PLL input clock frequency.</span>
<a name="l00274"></a>00274 <span class="comment"> */</span>
<a name="l00275"></a>00275 <span class="preprocessor">#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)</span>
<a name="l00276"></a>00276 <span class="preprocessor"></span><span class="preprocessor">#if STM32_PLLXTPRE == STM32_PLLXTPRE_DIV1</span>
<a name="l00277"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga0b32be6543b6d55b0505288f268ddbe1">00277</a> <span class="preprocessor"></span><span class="preprocessor">#define STM32_PLLCLKIN (STM32_HSECLK / 1)</span>
<a name="l00278"></a>00278 <span class="preprocessor"></span><span class="preprocessor">#else</span>
<a name="l00279"></a>00279 <span class="preprocessor"></span><span class="preprocessor">#define STM32_PLLCLKIN (STM32_HSECLK / 2)</span>
<a name="l00280"></a>00280 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
<a name="l00281"></a>00281 <span class="preprocessor"></span><span class="preprocessor">#elif STM32_PLLSRC == STM32_PLLSRC_HSI</span>
<a name="l00282"></a>00282 <span class="preprocessor"></span><span class="preprocessor">#define STM32_PLLCLKIN (STM32_HSICLK / 2)</span>
<a name="l00283"></a>00283 <span class="preprocessor"></span><span class="preprocessor">#else</span>
<a name="l00284"></a>00284 <span class="preprocessor"></span><span class="preprocessor">#error &quot;invalid STM32_PLLSRC value specified&quot;</span>
<a name="l00285"></a>00285 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
<a name="l00286"></a>00286 <span class="preprocessor"></span>
<a name="l00287"></a>00287 <span class="comment">/* PLL input frequency range check.*/</span>
<a name="l00288"></a>00288 <span class="preprocessor">#if (STM32_PLLCLKIN &lt; 3000000) || (STM32_PLLCLKIN &gt; 12000000)</span>
<a name="l00289"></a>00289 <span class="preprocessor"></span><span class="preprocessor">#error &quot;STM32_PLLCLKIN outside acceptable range (3...12MHz)&quot;</span>
<a name="l00290"></a>00290 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
<a name="l00291"></a>00291 <span class="preprocessor"></span><span class="comment"></span>
<a name="l00292"></a>00292 <span class="comment">/**</span>
<a name="l00293"></a>00293 <span class="comment"> * @brief PLL output clock frequency.</span>
<a name="l00294"></a>00294 <span class="comment"> */</span>
<a name="l00295"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga551b4e93d2b76245c4b912ebfc54f9f3">00295</a> <span class="preprocessor">#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)</span>
<a name="l00296"></a>00296 <span class="preprocessor"></span>
<a name="l00297"></a>00297 <span class="comment">/* PLL output frequency range check.*/</span>
<a name="l00298"></a>00298 <span class="preprocessor">#if (STM32_PLLCLKOUT &lt; 16000000) || (STM32_PLLCLKOUT &gt; 72000000)</span>
<a name="l00299"></a>00299 <span class="preprocessor"></span><span class="preprocessor">#error &quot;STM32_PLLCLKOUT outside acceptable range (16...72MHz)&quot;</span>
<a name="l00300"></a>00300 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
<a name="l00301"></a>00301 <span class="preprocessor"></span><span class="comment"></span>
<a name="l00302"></a>00302 <span class="comment">/**</span>
<a name="l00303"></a>00303 <span class="comment"> * @brief System clock source.</span>
<a name="l00304"></a>00304 <span class="comment"> */</span>
<a name="l00305"></a>00305 <span class="preprocessor">#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__)</span>
<a name="l00306"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga81594f71c9bc1c1fde4e5207e5133777">00306</a> <span class="preprocessor"></span><span class="preprocessor">#define STM32_SYSCLK STM32_PLLCLKOUT</span>
<a name="l00307"></a>00307 <span class="preprocessor"></span><span class="preprocessor">#elif (STM32_SW == STM32_SW_HSI)</span>
<a name="l00308"></a>00308 <span class="preprocessor"></span><span class="preprocessor">#define STM32_SYSCLK STM32_HSICLK</span>
<a name="l00309"></a>00309 <span class="preprocessor"></span><span class="preprocessor">#elif (STM32_SW == STM32_SW_HSE)</span>
<a name="l00310"></a>00310 <span class="preprocessor"></span><span class="preprocessor">#define STM32_SYSCLK STM32_HSECLK</span>
<a name="l00311"></a>00311 <span class="preprocessor"></span><span class="preprocessor">#else</span>
<a name="l00312"></a>00312 <span class="preprocessor"></span><span class="preprocessor">#error &quot;invalid STM32_SYSCLK_SW value specified&quot;</span>
<a name="l00313"></a>00313 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
<a name="l00314"></a>00314 <span class="preprocessor"></span>
<a name="l00315"></a>00315 <span class="comment">/* Check on the system clock.*/</span>
<a name="l00316"></a>00316 <span class="preprocessor">#if STM32_SYSCLK &gt; 72000000</span>
<a name="l00317"></a>00317 <span class="preprocessor"></span><span class="preprocessor">#error &quot;STM32_SYSCLK above maximum rated frequency (72MHz)&quot;</span>
<a name="l00318"></a>00318 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
<a name="l00319"></a>00319 <span class="preprocessor"></span><span class="comment"></span>
<a name="l00320"></a>00320 <span class="comment">/**</span>
<a name="l00321"></a>00321 <span class="comment"> * @brief AHB frequency.</span>
<a name="l00322"></a>00322 <span class="comment"> */</span>
<a name="l00323"></a>00323 <span class="preprocessor">#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)</span>
<a name="l00324"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga918128f20df10ac68bd73605007bccf1">00324</a> <span class="preprocessor"></span><span class="preprocessor">#define STM32_HCLK (STM32_SYSCLK / 1)</span>
<a name="l00325"></a>00325 <span class="preprocessor"></span><span class="preprocessor">#elif STM32_HPRE == STM32_HPRE_DIV2</span>
<a name="l00326"></a>00326 <span class="preprocessor"></span><span class="preprocessor">#define STM32_HCLK (STM32_SYSCLK / 2)</span>
<a name="l00327"></a>00327 <span class="preprocessor"></span><span class="preprocessor">#elif STM32_HPRE == STM32_HPRE_DIV4</span>
<a name="l00328"></a>00328 <span class="preprocessor"></span><span class="preprocessor">#define STM32_HCLK (STM32_SYSCLK / 4)</span>
<a name="l00329"></a>00329 <span class="preprocessor"></span><span class="preprocessor">#elif STM32_HPRE == STM32_HPRE_DIV8</span>
<a name="l00330"></a>00330 <span class="preprocessor"></span><span class="preprocessor">#define STM32_HCLK (STM32_SYSCLK / 8)</span>
<a name="l00331"></a>00331 <span class="preprocessor"></span><span class="preprocessor">#elif STM32_HPRE == STM32_HPRE_DIV16</span>
<a name="l00332"></a>00332 <span class="preprocessor"></span><span class="preprocessor">#define STM32_HCLK (STM32_SYSCLK / 16)</span>
<a name="l00333"></a>00333 <span class="preprocessor"></span><span class="preprocessor">#elif STM32_HPRE == STM32_HPRE_DIV64</span>
<a name="l00334"></a>00334 <span class="preprocessor"></span><span class="preprocessor">#define STM32_HCLK (STM32_SYSCLK / 64)</span>
<a name="l00335"></a>00335 <span class="preprocessor"></span><span class="preprocessor">#elif STM32_HPRE == STM32_HPRE_DIV128</span>
<a name="l00336"></a>00336 <span class="preprocessor"></span><span class="preprocessor">#define STM32_HCLK (STM32_SYSCLK / 128)</span>
<a name="l00337"></a>00337 <span class="preprocessor"></span><span class="preprocessor">#elif STM32_HPRE == STM32_HPRE_DIV256</span>
<a name="l00338"></a>00338 <span class="preprocessor"></span><span class="preprocessor">#define STM32_HCLK (STM32_SYSCLK / 256)</span>
<a name="l00339"></a>00339 <span class="preprocessor"></span><span class="preprocessor">#elif STM32_HPRE == STM32_HPRE_DIV512</span>
<a name="l00340"></a>00340 <span class="preprocessor"></span><span class="preprocessor">#define STM32_HCLK (STM32_SYSCLK / 512)</span>
<a name="l00341"></a>00341 <span class="preprocessor"></span><span class="preprocessor">#else</span>
<a name="l00342"></a>00342 <span class="preprocessor"></span><span class="preprocessor">#error &quot;invalid STM32_HPRE value specified&quot;</span>
<a name="l00343"></a>00343 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
<a name="l00344"></a>00344 <span class="preprocessor"></span>
<a name="l00345"></a>00345 <span class="comment">/* AHB frequency check.*/</span>
<a name="l00346"></a>00346 <span class="preprocessor">#if STM32_HCLK &gt; 72000000</span>
<a name="l00347"></a>00347 <span class="preprocessor"></span><span class="preprocessor">#error &quot;STM32_HCLK exceeding maximum frequency (72MHz)&quot;</span>
<a name="l00348"></a>00348 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
<a name="l00349"></a>00349 <span class="preprocessor"></span><span class="comment"></span>
<a name="l00350"></a>00350 <span class="comment">/**</span>
<a name="l00351"></a>00351 <span class="comment"> * @brief APB1 frequency.</span>
<a name="l00352"></a>00352 <span class="comment"> */</span>
<a name="l00353"></a>00353 <span class="preprocessor">#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)</span>
<a name="l00354"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga79d8b0164de9c4437da78024b0ed94cb">00354</a> <span class="preprocessor"></span><span class="preprocessor">#define STM32_PCLK1 (STM32_HCLK / 1)</span>
<a name="l00355"></a>00355 <span class="preprocessor"></span><span class="preprocessor">#elif STM32_PPRE1 == STM32_PPRE1_DIV2</span>
<a name="l00356"></a>00356 <span class="preprocessor"></span><span class="preprocessor">#define STM32_PCLK1 (STM32_HCLK / 2)</span>
<a name="l00357"></a>00357 <span class="preprocessor"></span><span class="preprocessor">#elif STM32_PPRE1 == STM32_PPRE1_DIV4</span>
<a name="l00358"></a>00358 <span class="preprocessor"></span><span class="preprocessor">#define STM32_PCLK1 (STM32_HCLK / 4)</span>
<a name="l00359"></a>00359 <span class="preprocessor"></span><span class="preprocessor">#elif STM32_PPRE1 == STM32_PPRE1_DIV8</span>
<a name="l00360"></a>00360 <span class="preprocessor"></span><span class="preprocessor">#define STM32_PCLK1 (STM32_HCLK / 8)</span>
<a name="l00361"></a>00361 <span class="preprocessor"></span><span class="preprocessor">#elif STM32_PPRE1 == STM32_PPRE1_DIV16</span>
<a name="l00362"></a>00362 <span class="preprocessor"></span><span class="preprocessor">#define STM32_PCLK1 (STM32_HCLK / 16)</span>
<a name="l00363"></a>00363 <span class="preprocessor"></span><span class="preprocessor">#else</span>
<a name="l00364"></a>00364 <span class="preprocessor"></span><span class="preprocessor">#error &quot;invalid STM32_PPRE1 value specified&quot;</span>
<a name="l00365"></a>00365 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
<a name="l00366"></a>00366 <span class="preprocessor"></span>
<a name="l00367"></a>00367 <span class="comment">/* APB1 frequency check.*/</span>
<a name="l00368"></a>00368 <span class="preprocessor">#if STM32_PCLK2 &gt; 36000000</span>
<a name="l00369"></a>00369 <span class="preprocessor"></span><span class="preprocessor">#error &quot;STM32_PCLK1 exceeding maximum frequency (36MHz)&quot;</span>
<a name="l00370"></a>00370 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
<a name="l00371"></a>00371 <span class="preprocessor"></span><span class="comment"></span>
<a name="l00372"></a>00372 <span class="comment">/**</span>
<a name="l00373"></a>00373 <span class="comment"> * @brief APB2 frequency.</span>
<a name="l00374"></a>00374 <span class="comment"> */</span>
<a name="l00375"></a>00375 <span class="preprocessor">#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)</span>
<a name="l00376"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga2a19a811dd0dadfed94695a579997cec">00376</a> <span class="preprocessor"></span><span class="preprocessor">#define STM32_PCLK2 (STM32_HCLK / 1)</span>
<a name="l00377"></a>00377 <span class="preprocessor"></span><span class="preprocessor">#elif STM32_PPRE2 == STM32_PPRE2_DIV2</span>
<a name="l00378"></a>00378 <span class="preprocessor"></span><span class="preprocessor">#define STM32_PCLK2 (STM32_HCLK / 2)</span>
<a name="l00379"></a>00379 <span class="preprocessor"></span><span class="preprocessor">#elif STM32_PPRE2 == STM32_PPRE2_DIV4</span>
<a name="l00380"></a>00380 <span class="preprocessor"></span><span class="preprocessor">#define STM32_PCLK2 (STM32_HCLK / 4)</span>
<a name="l00381"></a>00381 <span class="preprocessor"></span><span class="preprocessor">#elif STM32_PPRE2 == STM32_PPRE2_DIV8</span>
<a name="l00382"></a>00382 <span class="preprocessor"></span><span class="preprocessor">#define STM32_PCLK2 (STM32_HCLK / 8)</span>
<a name="l00383"></a>00383 <span class="preprocessor"></span><span class="preprocessor">#elif STM32_PPRE2 == STM32_PPRE2_DIV16</span>
<a name="l00384"></a>00384 <span class="preprocessor"></span><span class="preprocessor">#define STM32_PCLK2 (STM32_HCLK / 16)</span>
<a name="l00385"></a>00385 <span class="preprocessor"></span><span class="preprocessor">#else</span>
<a name="l00386"></a>00386 <span class="preprocessor"></span><span class="preprocessor">#error &quot;invalid STM32_PPRE2 value specified&quot;</span>
<a name="l00387"></a>00387 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
<a name="l00388"></a>00388 <span class="preprocessor"></span>
<a name="l00389"></a>00389 <span class="comment">/* APB2 frequency check.*/</span>
<a name="l00390"></a>00390 <span class="preprocessor">#if STM32_PCLK2 &gt; 72000000</span>
<a name="l00391"></a>00391 <span class="preprocessor"></span><span class="preprocessor">#error &quot;STM32_PCLK2 exceeding maximum frequency (72MHz)&quot;</span>
<a name="l00392"></a>00392 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
<a name="l00393"></a>00393 <span class="preprocessor"></span><span class="comment"></span>
<a name="l00394"></a>00394 <span class="comment">/**</span>
<a name="l00395"></a>00395 <span class="comment"> * @brief ADC frequency.</span>
<a name="l00396"></a>00396 <span class="comment"> */</span>
<a name="l00397"></a>00397 <span class="preprocessor">#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__)</span>
<a name="l00398"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga62f559490a97de4746d6963d946e1e37">00398</a> <span class="preprocessor"></span><span class="preprocessor">#define STM32_ADCCLK (STM32_PCLK2 / 2)</span>
<a name="l00399"></a>00399 <span class="preprocessor"></span><span class="preprocessor">#elif STM32_ADCPRE == STM32_ADCPRE_DIV4</span>
<a name="l00400"></a>00400 <span class="preprocessor"></span><span class="preprocessor">#define STM32_ADCCLK (STM32_PCLK2 / 4)</span>
<a name="l00401"></a>00401 <span class="preprocessor"></span><span class="preprocessor">#elif STM32_ADCPRE == STM32_ADCPRE_DIV6</span>
<a name="l00402"></a>00402 <span class="preprocessor"></span><span class="preprocessor">#define STM32_ADCCLK (STM32_PCLK2 / 6)</span>
<a name="l00403"></a>00403 <span class="preprocessor"></span><span class="preprocessor">#elif STM32_ADCPRE == STM32_ADCPRE_DIV8</span>
<a name="l00404"></a>00404 <span class="preprocessor"></span><span class="preprocessor">#define STM32_ADCCLK (STM32_PCLK2 / 8)</span>
<a name="l00405"></a>00405 <span class="preprocessor"></span><span class="preprocessor">#else</span>
<a name="l00406"></a>00406 <span class="preprocessor"></span><span class="preprocessor">#error &quot;invalid STM32_ADCPRE value specified&quot;</span>
<a name="l00407"></a>00407 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
<a name="l00408"></a>00408 <span class="preprocessor"></span>
<a name="l00409"></a>00409 <span class="comment">/* ADC frequency check.*/</span>
<a name="l00410"></a>00410 <span class="preprocessor">#if STM32_ADCCLK &gt; 14000000</span>
<a name="l00411"></a>00411 <span class="preprocessor"></span><span class="preprocessor">#error &quot;STM32_ADCCLK exceeding maximum frequency (14MHz)&quot;</span>
<a name="l00412"></a>00412 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
<a name="l00413"></a>00413 <span class="preprocessor"></span><span class="comment"></span>
<a name="l00414"></a>00414 <span class="comment">/**</span>
<a name="l00415"></a>00415 <span class="comment"> * @brief Timers 2, 3, 4, 5, 6, 7, 12, 13, 14 clock.</span>
<a name="l00416"></a>00416 <span class="comment"> */</span>
<a name="l00417"></a>00417 <span class="preprocessor">#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)</span>
<a name="l00418"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga8d53f5e948e73dc86013349c17f742f3">00418</a> <span class="preprocessor"></span><span class="preprocessor">#define STM32_TIMCLK1 (STM32_PCLK1 * 1)</span>
<a name="l00419"></a>00419 <span class="preprocessor"></span><span class="preprocessor">#else</span>
<a name="l00420"></a>00420 <span class="preprocessor"></span><span class="preprocessor">#define STM32_TIMCLK1 (STM32_PCLK1 * 2)</span>
<a name="l00421"></a>00421 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
<a name="l00422"></a>00422 <span class="preprocessor"></span><span class="comment"></span>
<a name="l00423"></a>00423 <span class="comment">/**</span>
<a name="l00424"></a>00424 <span class="comment"> * @brief Timers 1, 8, 9, 10 and 11 clock.</span>
<a name="l00425"></a>00425 <span class="comment"> */</span>
<a name="l00426"></a>00426 <span class="preprocessor">#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)</span>
<a name="l00427"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#gacacec831f4aa8037c710ab56c7a73686">00427</a> <span class="preprocessor"></span><span class="preprocessor">#define STM32_TIMCLK2 (STM32_PCLK2 * 1)</span>
<a name="l00428"></a>00428 <span class="preprocessor"></span><span class="preprocessor">#else</span>
<a name="l00429"></a>00429 <span class="preprocessor"></span><span class="preprocessor">#define STM32_TIMCLK2 (STM32_PCLK2 * 2)</span>
<a name="l00430"></a>00430 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
<a name="l00431"></a>00431 <span class="preprocessor"></span><span class="comment"></span>
<a name="l00432"></a>00432 <span class="comment">/**</span>
<a name="l00433"></a>00433 <span class="comment"> * @brief Flash settings.</span>
<a name="l00434"></a>00434 <span class="comment"> */</span>
<a name="l00435"></a>00435 <span class="preprocessor">#if (STM32_HCLK &lt;= 24000000) || defined(__DOXYGEN__)</span>
<a name="l00436"></a><a class="code" href="group___s_t_m32_f103___h_a_l.html#ga59b3885d4e2a3f63cfeb9ae58b6da563">00436</a> <span class="preprocessor"></span><span class="preprocessor">#define STM32_FLASHBITS 0x00000010</span>
<a name="l00437"></a>00437 <span class="preprocessor"></span><span class="preprocessor">#elif STM32_HCLK &lt;= 48000000</span>
<a name="l00438"></a>00438 <span class="preprocessor"></span><span class="preprocessor">#define STM32_FLASHBITS 0x00000011</span>
<a name="l00439"></a>00439 <span class="preprocessor"></span><span class="preprocessor">#else</span>
<a name="l00440"></a>00440 <span class="preprocessor"></span><span class="preprocessor">#define STM32_FLASHBITS 0x00000012</span>
<a name="l00441"></a>00441 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
<a name="l00442"></a>00442 <span class="preprocessor"></span>
<a name="l00443"></a>00443 <span class="preprocessor">#endif </span><span class="comment">/* _HAL_LLD_F103_H_ */</span>
<a name="l00444"></a>00444 <span class="comment"></span>
<a name="l00445"></a>00445 <span class="comment">/** @} */</span>
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