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222 Commits

Author SHA1 Message Date
Sean Cross
a0a9a416f1 hw: foboot-bitstream: -dffe_min_ce_use of 4 is better 
With a value of 5, we run out of LCs.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-21 14:08:13 +08:00
Sean Cross
b0b87addae hw: deps: use experimental lxsocsupport up5kspram block 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-21 13:48:26 +08:00
Sean Cross
2464b510fa hw: rtl: use only one hw breakpoint 
We were running out of LUTs, so reduce the number of breakpoints
from 4 to 1.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-21 13:47:11 +08:00
Sean Cross
6f7ce8a1ae hw: foboot-bitstream: use -dffe_min_ce_use 5 
This is required to get it to fit for now.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-21 13:46:43 +08:00
Sean Cross
eefa76706b hw: foboot-bitstream: remove bbspi 
It isn't used anymore, and is just making the file bigger.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-21 12:34:54 +08:00
Sean Cross
2b9f9612d8 hw: deps: use latest litex 
This will enable us to have spiflash working later on.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-21 12:27:03 +08:00
Sean Cross
425787484d hw: deps: fix metastability with new valentyusb 
The new valentyusb fixes metastability in the tx and rx path.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-21 12:26:34 +08:00
Sean Cross
4156f6c376 Merge branch 'timing-fixup' 2019-07-21 12:22:04 +08:00
Sean Cross
c72a987a5d hw: foboot-bitstream: set min_ce_use to 4 
This matches the comment, and shouldn't have any effect on the
resulting output.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-21 12:20:30 +08:00
Sean Cross
e7b55338be hw: foboot-bitstream: hardcode memory map 
Rather than relying on the memory map from litex, hardcode the
memory offsets.

This is required because sometimes the litex memory map changes,
and we want to have a consistent offset across builds.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-21 12:19:13 +08:00
Sean Cross
bd08f0bb06 hw: foboot-bitstream: correct spi pin mappings for "dq" 
The "dq" mappings for SPI were wrong, and wouldn't work with the
SPI flash in dual/quad mode.  Correct these mappings for all platforms.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-21 12:17:19 +08:00
Sean Cross
1e34d27f47 hw: foboot-bitstream: don't hardcode sram offset 
Use the values from the memory map instead of hardcoding the offset.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-21 12:15:13 +08:00
Sean Cross
a45b6be459 hw: foboot-bitstream: use buffered output from pll 
The PLL has two outputs: buffered and unbuffered.  Take the clock
signal from the buffered output.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-21 12:13:30 +08:00
Sean Cross
ee30de7946 hw: foboot-bitstream: use all 13 bits of the clock reset 
There are 13 bits on the clock reset line, but right now we only use
12 of them.  Set the counter to 8191 so we take advantage of
all 13 bits.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-21 12:12:41 +08:00
Sean Cross
8c84afa4d9 hw: bitstream: add dummyusb if no cpu is present 
This will allow us to still access the wishbone bus without a CPU.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-20 16:29:48 +08:00
Sean Cross
e1a1b60821 hw: foboot-bitstream: use GENCLK_HALF from PLL 
This removes a double-flop that we were using to get a 12 MHz clock,
which we were then multiplying back up to 48 MHz.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-20 16:15:02 +08:00
Sean Cross
541c765198 hw: foboot-bitstream: fix --no-cpu flag 
If there is no CPU, then don't adjust the CPU reset vector.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-20 16:14:35 +08:00
Sean Cross
eed9897cfc litex: pull latest spi flash changes 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-08 14:14:14 +08:00
Sean Cross
a4a3dad324 hw: fix led ordering on hacker board and add id to "version" 
Fix the ordering of the LEDs on the "hacker" board.

Add a "model id" to the "version" block.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-08 12:14:39 +08:00
Sean Cross
10454fa0be sbled: fix mapping of r,g,b and add bit-bang mode 
Fix the mapping of red, green, and blue.  Now the LEDDPWRR, LEDDPWRG,
and LEDDPWRB map to their correct values.

Additionally, a bit-banged mode for the LED has been added to enable
fine-grained control in a simpler manner.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-08 10:13:09 +08:00
Sean Cross
c622551300
Merge pull request #15 from TomKeddie/tomk_20190701_flashaddr 
Flash mapping address fixes
 2019-07-07 09:20:57 +08:00
Sean Cross
d1cd68c232 hw: set debug bridge memory size to 0x100 
Hardware breakpoints live at offset 0x40 from the start of this region,
so increase the size from 0x10 to 0x100.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-04 16:39:28 +08:00
Tom Keddie
1c8c1f3bc1 Flash mapping address fixes 
- too many bits were allocated causing problems addressing 128Mbit devices
- the shift operator in python generates a signed shift in verilog which potentilly trashes the upper address bit, switch to padding
 2019-07-03 02:59:20 -07:00
Sean Cross
f2084ea817 hw: foboot-bitstream: tab -> spaces 
I wonder how that got in there...

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-06-19 14:05:29 -07:00
Sean Cross
61d912b9fc valentyusb: update to include dummyusb fixes 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-06-19 12:38:47 -07:00
Sean Cross
8354617950 Merge branch 'master' of github.com:im-tomu/foboot 2019-06-17 15:33:49 -07:00
Sean Cross
ccdf910ec1 hw: add --seed argument 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-06-17 15:02:04 -07:00
Sean Cross
8a0df08507 foboot-bitstream: ce 5 again 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-06-17 14:49:06 -07:00
Sean Cross
ce1f5c932a hw: foboot-bitstream: add an entry for the initial boot image 
Add an entry for boot image 0.  Previously this was getting implied, but
due to the way Python arrays work, it was getting added to the end of
the list instead of the beginning.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-06-17 11:11:57 -07:00
Tom Keddie
341db19f70 Move bitstream sync constants to CONFIG entries 2019-06-13 20:20:24 -07:00
Sean Cross
c2d334e89c foboot-bitstream: move multiboot image 4 to 32768 
Move the multiboot image #4 from 4096 bytes to 32768 bytes.

This helps to future-proof against larger disks which have bigger FATs.
Otherwise, the boot image could be located within the FAT, which would
cause problems.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-06-07 12:47:57 +08:00
Sean Cross
afdd649616 Merge branch 'master' of github.com:im-tomu/foboot 2019-05-26 15:57:41 +08:00
Sean Cross
f57e9b23ea foboot-bitstream: add "pvt" to list of values 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-05-26 15:44:02 +08:00
Sean Cross
f1f0f14d71 foboot-bitstream: use ce of 4 
A ce of 5 resulted in a bitstream that didn't work.  Hmm...

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-05-23 22:11:54 +08:00
Sean Cross
b84a24a853 foboot-bitstream: use modern method of indicating debug 
The litex core has changed how debug is indicated, instead preferring to
add suffixes to configurations.

Follow this convention when instantiating the main CPU.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-05-23 21:54:33 +08:00
Sean Cross
f968c20d17 lxbuildenv: update paths for bin files 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-05-22 11:21:19 +08:00
Sean Cross
14e46296e5 litex: use upstream version with fixed debug packet 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-05-22 08:41:01 +08:00
Sean Cross
58fba5b90e hw: use ce 5 
This lets us meet timing.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-05-20 13:17:58 +08:00
Sean Cross
47cbc614a1 hw: deps: use valentyusb v0.3.3 
This version removes retry from the usb wishbone bridge.  It was
discovered that this causes crc errors.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-05-20 13:01:36 +08:00
Sean Cross
ab16cc0119 foboot-bitstream: add "version" block 
This block describes the various git version parameters.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-05-20 10:55:56 +08:00
Sean Cross
1913767ca7 tests: add simple program to test tx/rx 
This program generates random data and makes sure it is received.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-05-14 19:28:29 +08:00
Sean Cross
7f025eac5c valentyusb: fix debug with multiple endpoints 
Now we properly inhibit other endpoints, and prevent the buffer from
draining when there's a debug packet.

This also prevents an early return from DEBUG READ.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-05-14 15:33:00 +08:00
Sean Cross
bbfd68ed72 foboot-bitstream: use 5 ce lines 
This doesn't change much, but it prevents nextpnr from getting into an
infinite loop.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-05-14 10:24:37 +08:00
Sean Cross
0f5267122b valentyusb: use generic IO blocks 
There's no need to use ICE40-specific IO blocks.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-05-14 10:23:49 +08:00
Sean Cross
8d6c3dc5fc deps: valentyusb: use new usb pipeline 
This pipeline removes the timing violations we had, and improves the
debug bridge by quite a lot.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-05-12 21:47:11 +08:00
Sean Cross
c5eb487951 deps: valentyusb: add fixes from usbalex 
These fix the timing of the USB connection.

These fixes also fix issues with USB debugging.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-05-10 22:11:17 +08:00
Sean Cross
5b71eeea7d foboot-bitstream: tristate pulldown on evt board 
The EVT board has a pulldown, in case we want to do USB LS.  This causes
issues on some hubs, because they end up with weak pullups, which throws
off enumeration.

Set it to a tristate input, which fixes this behavior.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-05-05 17:40:07 -07:00
Sean Cross
3a6ae4679a deps: valentyusb: fix "STALL" error on debug packets 
We weren't properly ACKing debug packets.  This fixes that.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-05-01 14:21:54 -07:00
Sean Cross
21be05f8ab hw: foboot-bitstream: simplify duplicate CRG code 
Much of the clock resource generator was duplicated for the two options:
PLL and adder.  Remove this artifical distinction and reuse much of the
CRG code.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-29 16:37:51 -07:00
Sean Cross
6caffc1eb6 hw: deps: have valentyusb reset itself on error 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-28 16:43:12 +08:00
Sean Cross
39b3fb6507 hw: rtl: use latest release version of vexriscv 
This doesn't appear to work yet, but is the latest upstream release
version of vexriscv.

Need to investigate more into why it's failing.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-26 09:53:51 +08:00
Sean Cross
ba310ab8e2 hw: rtl: add missing files 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-25 23:35:51 +08:00
Sean Cross
d147af1e6a hw: add some vexriscv experiments 
We're trying to improve performance and reduce core size.

This uses a newer version of the vexriscv core.  It has a shorter
pipeline, with better exception handling.  It also properly initializes
registers.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-25 23:23:54 +08:00
Sean Cross
ee640fdb57 hw: foboot-bitstream: fix csr offsets 
These offsets can shift.  Ensure they stay the same during subsequent
rebuilds.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-25 17:40:37 +08:00
Sean Cross
bee41ec891 hw: valentyusb: better buffer draining on reset 
Pull in improved support for draining the buffers when going into reset.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-25 13:27:55 +08:00
Sean Cross
ace0d2c22f hw: valentyusb: sync wishbone ep1 fixes 
This fixes EP1+ so that interleved accesses work.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-23 17:25:06 +08:00
Sean Cross
f94da96db4 hw: foboot-bitstream: properly hook up cpu reset override 
It turns out that just assigning a value isn't enough in Python to
assign the signal.  You need to override the dictionary entry.

With this patch, it is now possible to dynamically adjust the CPU reset
entrypoint, which is handy for debugging.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-23 17:21:16 +08:00
Sean Cross
1a5867c5e5 hw: foboot-bitstream: invert logic on pll selection 
The pll is necessary to get consistent performance, but disabling it can
sometimes help meet synthesis timing.  Ensure the pll is enabled, unless
explicitly disabled with this switch.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-22 15:09:48 +08:00
Sean Cross
722aee37d9 hw: foboot-bitstream: don't reuse touchpad for WP on hacker 
We needed to pick a random, unused pin for "wp" on the Hacker board.
Unfortunately, I picked a pin that's used by the touchpads.  Pick a
different unused pin.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-22 10:03:48 +08:00
Sean Cross
4e5c75a0df deps: valentyusb: use debug port fix 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-21 21:50:52 +08:00
Sean Cross
698ea6c2f7 deps: litex: sync upstream for litex_server changes 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-21 21:49:31 +08:00
Sean Cross
c0690187b4 Merge branch 'wishbone-debug' 2019-04-21 21:48:33 +08:00
Sean Cross
eb6fa89452 merge debug 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-21 21:48:16 +08:00
Sean Cross
78d861d14a hw: foboot-bitstream: add gpios for touch pads 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-21 21:46:29 +08:00
Sean Cross
0fce77fb21 examples: add usb-cdcacm example 
This tests that multiple endpoints work as we expect.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-21 21:44:37 +08:00
Sean Cross
aef5043db0 deps: litex: use latest upstream branch 
This contains the usb patches, as well as vexriscv reset patch.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-20 08:55:24 +08:00
Sean Cross
4b16e24c9a hw: add csr for cpu reset address, and add full endpoint suite 
Add all endpoints so we can have either a serial port or a mass storage
device.

Also add a CSR to allow us to set the reset address of the CPU.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-20 00:06:10 +08:00
Sean Cross
91a205fe2c Merge branch 'master' of github.com:im-tomu/foboot into wishbone-debug 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-18 21:35:20 +08:00
Sean Cross
f8f2ec638f hw: foboot-bitstream: add usb to debug options 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-18 21:32:50 +08:00
Sean Cross
4b34dced9d Merge branch 'riscv-dfu-boot' of github.com:im-tomu/foboot into riscv-dfu-boot 2019-04-18 21:31:37 +08:00
Sean Cross
7eaad24d50 deps: valentyusb: use wishbone-debug branch 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-18 21:30:45 +08:00
Sean Cross
faf431dd58 hw: fix tests line endings 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-11 15:54:06 +08:00
Sean Cross
3b809e70f7 hw: minor text cleanup on foboot-bitstream 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-11 15:48:24 +08:00
Sean Cross
ddff12cd02 hw: fix spi so code execution works 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-11 13:23:44 +08:00
Sean Cross
9e8bcc3350 lxbuildenv: convert to unix line endings 
This should have been done a while ago.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-11 10:34:35 +08:00
Sean Cross
9cb4e4a8ce WIP: riscv boot 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-11 09:40:28 +08:00
Sean Cross
cf574019a0 hw: remove obsolete call to icemulti 
We make our images from scratch.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-11 09:38:44 +08:00
Sean Cross
acb4b998da hw: add another boot image 
Still trying to decide on the image order.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-11 09:38:09 +08:00
Sean Cross
3a51f55ee7 hw: foboot-bitstream: replace bbspi with picorvspi 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-10 16:44:05 +08:00
Sean Cross
7774fdd7e7 hw: fomu_flash: add spi controller from picorv32 
This controller supports many features, including bit-bang mode and
memory-mapped access.  It should replace the previous module
entirely.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-10 16:42:59 +08:00
Sean Cross
63f5dc75de hw: foboot-bitstream: add an option to build with no cpu 
Building with no CPU is faster, and can be very handy for debugging
various hardware blocks when using litex_server.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-10 16:41:17 +08:00
Sean Cross
d89eea3934 usb: refactor state machine to work with xhci devices 
Due to some subtle quirks, as well as a poorly-implemented state machine,
foboot was not compatible with many Desktop devices.

This should fix the implementation so that it is more compatible.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-08 17:19:54 +08:00
Sean Cross
20c0fb2b2b valentyusb: revert shorter-pipeline patch 
It didn't seem to fix anything, and may have made things worse.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-07 22:57:05 +08:00
Sean Cross
5f7cd9d2ab foboot-bitstream: disable pll by default, add -with-dsp option 
Disable building the PLL by default.  While we're at it, add
an argument to attempt to infer the DSP.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-07 06:27:13 +01:00
Sean Cross
c0df98f66e hw: correct crystal pin for Hacker board 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-06 17:08:01 +08:00
Sean Cross
6d9028f505 hw: foboot-bitstream: create multiboot image after build 
This fixes an issue where the directory wasn't created first.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-06 16:19:30 +08:00
Sean Cross
7ee97214e6 foboot-bitstream: generate multiboot and print helpful message 
Generate a multiboot version of the bitstream image.  While we're at it,
print a helpful message indicating what each output image is.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-06 11:07:39 +08:00
Sean Cross
2a7e431947 hw: foboot-bitstream: support building bios 
Now that the failsafe bios has stabilized, support building it as part
of the ROM.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-06 09:42:29 +08:00
Sean Cross
6435aec3db foboot-bitstream: add hacker revision 
Untested commit -- this should add support for the Hacker version of the
PCB.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-05 18:58:19 +08:00
Sean Cross
db65ccc199 hw: document warmboot some more 
Realized that there are 5 images and not 4.  With this, everything
works as it should.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-05 17:34:10 +08:00
Sean Cross
4c3f0f2402 valentyusb: use experimental shorter pipeline 
This helps to improve timing.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-03 22:11:02 +08:00
Sean Cross
1660681d38 hw: add 2-stage-1024-cache 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-03 21:57:53 +08:00
Sean Cross
c33d86adb9 foboot-bitstream: fix warmboot and add rgb block 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-02 18:11:58 +08:00
Sean Cross
8599ec7007 hw: bitstream: simplify command line argument parsing 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-02 13:03:47 +08:00
Sean Cross
0e720d5acc README: add information about sw and hw and building 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-01 10:10:13 +08:00
Sean Cross
2fd01b8303 foboot-bitstream: more help description, add dvt support 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-01 10:09:20 +08:00
Sean Cross
6595eb1ef1 valentyusb: increase incoming buffer to 128 bytes 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-03-28 11:12:32 +08:00
Sean Cross
7191c12490 wip: just need to get WARMBOOT working 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-03-28 11:11:36 +08:00
Sean Cross
3d6acaf51e sw: wip commit -- getting dfu working 
Now that we have SPI and USB both working, we can start to close the
loop and get DFU working.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-03-25 17:39:06 +08:00
Sean Cross
23b9962067 hw: foboot-bitstream: remove pmod debug comments 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-03-20 13:12:53 +08:00
Sean Cross
fa690d63ed hw: foboot-bitstream: clean up debug generation 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-03-20 13:12:29 +08:00
Sean Cross
4f0507fc77 hw: foboot-bitstream: remove "generating firmware" message 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-03-20 13:12:08 +08:00
Sean Cross
f3d779787b hw: foboot-bitstream: add reset to usb_48 
This is required to meet timing.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-03-20 13:11:45 +08:00
Sean Cross
b09333f023 hw: add spi and new vexriscv to foboot 
This is the beginning of having SPI.

Also add a new two-stage pipeline.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-03-20 11:25:09 +08:00
Sean Cross
c7632ae8bd deps: litex: sync with latest version 
This pulls in several fixes, including custom vexriscv modules.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-03-17 17:33:31 +01:00
Sean Cross
4aa3861c03 hw: deps: update to first feature-complete valentyusb 
This is the first version of `valentyusb` that successfully enumerates
without any errors.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-03-11 11:52:03 +08:00
Sean Cross
5bcd6c44fb deps: update valentyusb to working rev 
This revision works, although more tuning needs to be done.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-03-10 22:43:28 +08:00
Sean Cross
2d7c7794f5 hw: foboot-bitstream: remove debug pins, use epfifo 
Remove the debug pins to let timing close.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-03-10 21:06:37 +08:00
Sean Cross
0c6e444789 hw: foboot-bitstream: add -relut and friends to nextpnr 
Shrink the resulting gate count by adding -relut and adjusting the
number of luts that a CE signal can use.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-03-10 21:05:51 +08:00
Sean Cross
8aed600cd6 hw: foboot-bitstream: specify additional clock domain constraints 
Specify all the clock domain constraints for every possible signal, to
work around the fact that nextpnr currently will pick one and ignore the
rest.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-03-10 21:05:12 +08:00
Sean Cross
6638801886 hw: foboot-bitstream: remove clk48_in signal 
It's unused.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-03-10 21:04:19 +08:00
Sean Cross
8fb6b5977b hw: foboot-bitstream: remove unused clk48 net 
We only use the raw and usb48 nets.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-03-10 20:53:58 +08:00
Sean Cross
13360015db Merge branch 'master' of github.com:xobs/foboot 2019-03-08 20:49:13 +08:00
Sean Cross
d603113b6f foboot-bitstream: send clk48 through shifter, then through pll 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-03-08 20:47:42 +08:00
Sean Cross
44ee19c8b4 valentyusb: use latest fix for metastable transmissions 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-03-06 14:06:17 +08:00
Sean Cross
f34601df98 hw: lxbuildenv: fix uninitialized repo issue 
We would get stuck in a loop.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-03-05 22:08:11 +08:00
Sean Cross
3df59a866d metastable fix: wip 
Trying to figure out what's causing this problem.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-03-05 20:28:54 +08:00
Sean Cross
73176b65de hw: lxbuildenv: fix detection of .git directory 
It was giving an incorrect path, which would cause it to refresh
submodules during every build.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-03-05 13:20:54 +08:00
Sean Cross
350497924e README: add simple readme file 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-03-05 09:17:20 +08:00
Sean Cross
74ec6be245 hw: remove gitignore 
It's stored in the root now

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-03-05 09:16:52 +08:00
Sean Cross
1c8634e954 gitmodules: add hw deps 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-03-05 09:16:36 +08:00
Sean Cross
8fe27d9371 Add 'hw/' from commit 'd812378c4d61f7c957ac4bcba15a8344fb7fb458' 
git-subtree-dir: hw
git-subtree-mainline: e4af98b4aa
git-subtree-split: d812378c4d
 2019-03-05 09:05:50 +08:00