Fix the mapping of red, green, and blue. Now the LEDDPWRR, LEDDPWRG,
and LEDDPWRB map to their correct values.
Additionally, a bit-banged mode for the LED has been added to enable
fine-grained control in a simpler manner.
Signed-off-by: Sean Cross <sean@xobs.io>
Hardware breakpoints live at offset 0x40 from the start of this region,
so increase the size from 0x10 to 0x100.
Signed-off-by: Sean Cross <sean@xobs.io>
- too many bits were allocated causing problems addressing 128Mbit devices
- the shift operator in python generates a signed shift in verilog which potentilly trashes the upper address bit, switch to padding
Add an entry for boot image 0. Previously this was getting implied, but
due to the way Python arrays work, it was getting added to the end of
the list instead of the beginning.
Signed-off-by: Sean Cross <sean@xobs.io>
Move the multiboot image #4 from 4096 bytes to 32768 bytes.
This helps to future-proof against larger disks which have bigger FATs.
Otherwise, the boot image could be located within the FAT, which would
cause problems.
Signed-off-by: Sean Cross <sean@xobs.io>
The litex core has changed how debug is indicated, instead preferring to
add suffixes to configurations.
Follow this convention when instantiating the main CPU.
Signed-off-by: Sean Cross <sean@xobs.io>
The EVT board has a pulldown, in case we want to do USB LS. This causes
issues on some hubs, because they end up with weak pullups, which throws
off enumeration.
Set it to a tristate input, which fixes this behavior.
Signed-off-by: Sean Cross <sean@xobs.io>
Much of the clock resource generator was duplicated for the two options:
PLL and adder. Remove this artifical distinction and reuse much of the
CRG code.
Signed-off-by: Sean Cross <sean@xobs.io>
We're trying to improve performance and reduce core size.
This uses a newer version of the vexriscv core. It has a shorter
pipeline, with better exception handling. It also properly initializes
registers.
Signed-off-by: Sean Cross <sean@xobs.io>
It turns out that just assigning a value isn't enough in Python to
assign the signal. You need to override the dictionary entry.
With this patch, it is now possible to dynamically adjust the CPU reset
entrypoint, which is handy for debugging.
Signed-off-by: Sean Cross <sean@xobs.io>
The pll is necessary to get consistent performance, but disabling it can
sometimes help meet synthesis timing. Ensure the pll is enabled, unless
explicitly disabled with this switch.
Signed-off-by: Sean Cross <sean@xobs.io>
We needed to pick a random, unused pin for "wp" on the Hacker board.
Unfortunately, I picked a pin that's used by the touchpads. Pick a
different unused pin.
Signed-off-by: Sean Cross <sean@xobs.io>
Add all endpoints so we can have either a serial port or a mass storage
device.
Also add a CSR to allow us to set the reset address of the CPU.
Signed-off-by: Sean Cross <sean@xobs.io>
This controller supports many features, including bit-bang mode and
memory-mapped access. It should replace the previous module
entirely.
Signed-off-by: Sean Cross <sean@xobs.io>
Building with no CPU is faster, and can be very handy for debugging
various hardware blocks when using litex_server.
Signed-off-by: Sean Cross <sean@xobs.io>
Due to some subtle quirks, as well as a poorly-implemented state machine,
foboot was not compatible with many Desktop devices.
This should fix the implementation so that it is more compatible.
Signed-off-by: Sean Cross <sean@xobs.io>
Generate a multiboot version of the bitstream image. While we're at it,
print a helpful message indicating what each output image is.
Signed-off-by: Sean Cross <sean@xobs.io>
