Sean Cross
d3dd349848
Revert "hw: rtl: use only one hw breakpoint"
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With an older litex build, we have enough space for four breakpoints
in the vexriscv core.
This reverts commit 2464b510fa
.
2019-07-22 08:51:18 +08:00
Sean Cross
40a572f1ba
hw: foboot-bitstream: go back to dff of 5
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It saves a few gates, but those few gates actually let it route.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-21 20:59:15 +08:00
Sean Cross
1b0bb2543b
hw: foboot-bitstream: use 12-bit reset counter
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It doesn't need to be 13 bits, and it saves us a few LCs.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-21 17:10:05 +08:00
Sean Cross
a0a9a416f1
hw: foboot-bitstream: -dffe_min_ce_use of 4 is better
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With a value of 5, we run out of LCs.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-21 14:08:13 +08:00
Sean Cross
b0b87addae
hw: deps: use experimental lxsocsupport up5kspram block
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-21 13:48:26 +08:00
Sean Cross
2464b510fa
hw: rtl: use only one hw breakpoint
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We were running out of LUTs, so reduce the number of breakpoints
from 4 to 1.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-21 13:47:11 +08:00
Sean Cross
6f7ce8a1ae
hw: foboot-bitstream: use -dffe_min_ce_use 5
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This is required to get it to fit for now.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-21 13:46:43 +08:00
Sean Cross
eefa76706b
hw: foboot-bitstream: remove bbspi
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It isn't used anymore, and is just making the file bigger.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-21 12:34:54 +08:00
Sean Cross
2b9f9612d8
hw: deps: use latest litex
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This will enable us to have spiflash working later on.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-21 12:27:03 +08:00
Sean Cross
425787484d
hw: deps: fix metastability with new valentyusb
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The new valentyusb fixes metastability in the tx and rx path.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-21 12:26:34 +08:00
Sean Cross
4156f6c376
Merge branch 'timing-fixup'
2019-07-21 12:22:04 +08:00
Sean Cross
c72a987a5d
hw: foboot-bitstream: set min_ce_use to 4
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This matches the comment, and shouldn't have any effect on the
resulting output.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-21 12:20:30 +08:00
Sean Cross
e7b55338be
hw: foboot-bitstream: hardcode memory map
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Rather than relying on the memory map from litex, hardcode the
memory offsets.
This is required because sometimes the litex memory map changes,
and we want to have a consistent offset across builds.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-21 12:19:13 +08:00
Sean Cross
bd08f0bb06
hw: foboot-bitstream: correct spi pin mappings for "dq"
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The "dq" mappings for SPI were wrong, and wouldn't work with the
SPI flash in dual/quad mode. Correct these mappings for all platforms.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-21 12:17:19 +08:00
Sean Cross
1e34d27f47
hw: foboot-bitstream: don't hardcode sram offset
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Use the values from the memory map instead of hardcoding the offset.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-21 12:15:13 +08:00
Sean Cross
a45b6be459
hw: foboot-bitstream: use buffered output from pll
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The PLL has two outputs: buffered and unbuffered. Take the clock
signal from the buffered output.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-21 12:13:30 +08:00
Sean Cross
ee30de7946
hw: foboot-bitstream: use all 13 bits of the clock reset
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There are 13 bits on the clock reset line, but right now we only use
12 of them. Set the counter to 8191 so we take advantage of
all 13 bits.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-21 12:12:41 +08:00
Sean Cross
8c84afa4d9
hw: bitstream: add dummyusb if no cpu is present
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This will allow us to still access the wishbone bus without a CPU.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-20 16:29:48 +08:00
Sean Cross
e1a1b60821
hw: foboot-bitstream: use GENCLK_HALF from PLL
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This removes a double-flop that we were using to get a 12 MHz clock,
which we were then multiplying back up to 48 MHz.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-20 16:15:02 +08:00
Sean Cross
541c765198
hw: foboot-bitstream: fix --no-cpu flag
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If there is no CPU, then don't adjust the CPU reset vector.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-20 16:14:35 +08:00
Sean Cross
eed9897cfc
litex: pull latest spi flash changes
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-08 14:14:14 +08:00
Sean Cross
a4a3dad324
hw: fix led ordering on hacker board and add id to "version"
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Fix the ordering of the LEDs on the "hacker" board.
Add a "model id" to the "version" block.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-08 12:14:39 +08:00
Sean Cross
10454fa0be
sbled: fix mapping of r,g,b and add bit-bang mode
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Fix the mapping of red, green, and blue. Now the LEDDPWRR, LEDDPWRG,
and LEDDPWRB map to their correct values.
Additionally, a bit-banged mode for the LED has been added to enable
fine-grained control in a simpler manner.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-08 10:13:09 +08:00
Sean Cross
c622551300
Merge pull request #15 from TomKeddie/tomk_20190701_flashaddr
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Flash mapping address fixes
2019-07-07 09:20:57 +08:00
Sean Cross
d1cd68c232
hw: set debug bridge memory size to 0x100
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Hardware breakpoints live at offset 0x40 from the start of this region,
so increase the size from 0x10 to 0x100.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-04 16:39:28 +08:00
Tom Keddie
1c8c1f3bc1
Flash mapping address fixes
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- too many bits were allocated causing problems addressing 128Mbit devices
- the shift operator in python generates a signed shift in verilog which potentilly trashes the upper address bit, switch to padding
2019-07-03 02:59:20 -07:00
Sean Cross
f2084ea817
hw: foboot-bitstream: tab -> spaces
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I wonder how that got in there...
Signed-off-by: Sean Cross <sean@xobs.io>
2019-06-19 14:05:29 -07:00
Sean Cross
61d912b9fc
valentyusb: update to include dummyusb fixes
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-06-19 12:38:47 -07:00
Sean Cross
8354617950
Merge branch 'master' of github.com:im-tomu/foboot
2019-06-17 15:33:49 -07:00
Sean Cross
ccdf910ec1
hw: add --seed argument
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-06-17 15:02:04 -07:00
Sean Cross
8a0df08507
foboot-bitstream: ce 5 again
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-06-17 14:49:06 -07:00
Sean Cross
ce1f5c932a
hw: foboot-bitstream: add an entry for the initial boot image
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Add an entry for boot image 0. Previously this was getting implied, but
due to the way Python arrays work, it was getting added to the end of
the list instead of the beginning.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-06-17 11:11:57 -07:00
Tom Keddie
341db19f70
Move bitstream sync constants to CONFIG entries
2019-06-13 20:20:24 -07:00
Sean Cross
c2d334e89c
foboot-bitstream: move multiboot image 4 to 32768
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Move the multiboot image #4 from 4096 bytes to 32768 bytes.
This helps to future-proof against larger disks which have bigger FATs.
Otherwise, the boot image could be located within the FAT, which would
cause problems.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-06-07 12:47:57 +08:00
Sean Cross
afdd649616
Merge branch 'master' of github.com:im-tomu/foboot
2019-05-26 15:57:41 +08:00
Sean Cross
f57e9b23ea
foboot-bitstream: add "pvt" to list of values
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-05-26 15:44:02 +08:00
Sean Cross
f1f0f14d71
foboot-bitstream: use ce of 4
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A ce of 5 resulted in a bitstream that didn't work. Hmm...
Signed-off-by: Sean Cross <sean@xobs.io>
2019-05-23 22:11:54 +08:00
Sean Cross
b84a24a853
foboot-bitstream: use modern method of indicating debug
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The litex core has changed how debug is indicated, instead preferring to
add suffixes to configurations.
Follow this convention when instantiating the main CPU.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-05-23 21:54:33 +08:00
Sean Cross
f968c20d17
lxbuildenv: update paths for bin files
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-05-22 11:21:19 +08:00
Sean Cross
14e46296e5
litex: use upstream version with fixed debug packet
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-05-22 08:41:01 +08:00
Sean Cross
58fba5b90e
hw: use ce 5
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This lets us meet timing.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-05-20 13:17:58 +08:00
Sean Cross
47cbc614a1
hw: deps: use valentyusb v0.3.3
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This version removes retry from the usb wishbone bridge. It was
discovered that this causes crc errors.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-05-20 13:01:36 +08:00
Sean Cross
ab16cc0119
foboot-bitstream: add "version" block
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This block describes the various git version parameters.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-05-20 10:55:56 +08:00
Sean Cross
1913767ca7
tests: add simple program to test tx/rx
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This program generates random data and makes sure it is received.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-05-14 19:28:29 +08:00
Sean Cross
7f025eac5c
valentyusb: fix debug with multiple endpoints
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Now we properly inhibit other endpoints, and prevent the buffer from
draining when there's a debug packet.
This also prevents an early return from DEBUG READ.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-05-14 15:33:00 +08:00
Sean Cross
bbfd68ed72
foboot-bitstream: use 5 ce lines
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This doesn't change much, but it prevents nextpnr from getting into an
infinite loop.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-05-14 10:24:37 +08:00
Sean Cross
0f5267122b
valentyusb: use generic IO blocks
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There's no need to use ICE40-specific IO blocks.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-05-14 10:23:49 +08:00
Sean Cross
8d6c3dc5fc
deps: valentyusb: use new usb pipeline
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This pipeline removes the timing violations we had, and improves the
debug bridge by quite a lot.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-05-12 21:47:11 +08:00
Sean Cross
c5eb487951
deps: valentyusb: add fixes from usbalex
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These fix the timing of the USB connection.
These fixes also fix issues with USB debugging.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-05-10 22:11:17 +08:00
Sean Cross
5b71eeea7d
foboot-bitstream: tristate pulldown on evt board
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The EVT board has a pulldown, in case we want to do USB LS. This causes
issues on some hubs, because they end up with weak pullups, which throws
off enumeration.
Set it to a tristate input, which fixes this behavior.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-05-05 17:40:07 -07:00