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Author SHA1 Message Date
Sean Cross
1664f3533c sw: apply nerve pinch to bootloader update 
Use the same FBM nerve pinch to prevent entering the updater.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-26 10:31:57 +08:00
Sean Cross
a9f0945822 booster: don't wait for debugger 
Just go when the program starts up.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-26 10:30:00 +08:00
Sean Cross
3a39368cd6 booster: do one last final image verification 
Before we erase the bootloader, verify the image is good.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-26 10:29:21 +08:00
Sean Cross
4be2950d7f fobooster: remove project 
It's now simply called "booster"

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-26 09:55:53 +08:00
Sean Cross
a80dc72399 booster: add usb support to booster 
This will make debugging easier.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-25 23:03:55 +08:00
Sean Cross
3e2febb464 sw: initial addition of bootloader updater 
Add the ability to boot from a bootloader if the right hook is found.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-24 20:58:45 +08:00
Sean Cross
da52534fe3 booster: WIP: use new bitstream as part of the updater 
Rework Booster so that it uses the bitstream that it is installing
in order to validate that the new image will actually work.

This removes any sort of binary ABI compatibility issues, and
prevents us from installing an image onto a device that it doesn't
support.

Additionally, this installer should be resistant to bricking, though
that has yet to be tested.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-24 20:52:44 +08:00
Sean Cross
c40446fb93 releases: add v1.8.7 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-22 10:39:43 +08:00
Sean Cross
63d73db50f hw: foboot-bitstream: once again, update dff 
Now that we're not so constrained, we can correct this again.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-22 08:56:14 +08:00
Sean Cross
6c1f63344c litex: move to earlier version 
This earlier version of litex should behave the same, but saves
~400 LCs and allows us to have four HW breakpoints.

Will investigate what changed later on.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-22 08:55:26 +08:00
Sean Cross
d3dd349848 Revert "hw: rtl: use only one hw breakpoint" 
With an older litex build, we have enough space for four breakpoints
in the vexriscv core.

This reverts commit 2464b510fa.
 2019-07-22 08:51:18 +08:00
Sean Cross
40a572f1ba hw: foboot-bitstream: go back to dff of 5 
It saves a few gates, but those few gates actually let it route.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-21 20:59:15 +08:00
Sean Cross
1b0bb2543b hw: foboot-bitstream: use 12-bit reset counter 
It doesn't need to be 13 bits, and it saves us a few LCs.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-21 17:10:05 +08:00
Sean Cross
a0a9a416f1 hw: foboot-bitstream: -dffe_min_ce_use of 4 is better 
With a value of 5, we run out of LCs.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-21 14:08:13 +08:00
Sean Cross
b0b87addae hw: deps: use experimental lxsocsupport up5kspram block 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-21 13:48:26 +08:00
Sean Cross
2464b510fa hw: rtl: use only one hw breakpoint 
We were running out of LUTs, so reduce the number of breakpoints
from 4 to 1.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-21 13:47:11 +08:00
Sean Cross
6f7ce8a1ae hw: foboot-bitstream: use -dffe_min_ce_use 5 
This is required to get it to fit for now.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-21 13:46:43 +08:00
Sean Cross
49a7197f7c sw: generated: add latest csr.h file 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-21 13:01:37 +08:00
Sean Cross
eefa76706b hw: foboot-bitstream: remove bbspi 
It isn't used anymore, and is just making the file bigger.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-21 12:34:54 +08:00
Sean Cross
a363e25b76 sw: time: rename SYSTEM_CLOCK_FREQUENCY to CONFIG_CLOCK_FREQUENCY 
This changed in litex.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-21 12:29:20 +08:00
Sean Cross
2b9f9612d8 hw: deps: use latest litex 
This will enable us to have spiflash working later on.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-21 12:27:03 +08:00
Sean Cross
425787484d hw: deps: fix metastability with new valentyusb 
The new valentyusb fixes metastability in the tx and rx path.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-21 12:26:34 +08:00
Sean Cross
4156f6c376 Merge branch 'timing-fixup' 2019-07-21 12:22:04 +08:00
Sean Cross
c72a987a5d hw: foboot-bitstream: set min_ce_use to 4 
This matches the comment, and shouldn't have any effect on the
resulting output.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-21 12:20:30 +08:00
Sean Cross
e7b55338be hw: foboot-bitstream: hardcode memory map 
Rather than relying on the memory map from litex, hardcode the
memory offsets.

This is required because sometimes the litex memory map changes,
and we want to have a consistent offset across builds.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-21 12:19:13 +08:00
Sean Cross
bd08f0bb06 hw: foboot-bitstream: correct spi pin mappings for "dq" 
The "dq" mappings for SPI were wrong, and wouldn't work with the
SPI flash in dual/quad mode.  Correct these mappings for all platforms.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-21 12:17:19 +08:00
Sean Cross
1e34d27f47 hw: foboot-bitstream: don't hardcode sram offset 
Use the values from the memory map instead of hardcoding the offset.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-21 12:15:13 +08:00
Sean Cross
a45b6be459 hw: foboot-bitstream: use buffered output from pll 
The PLL has two outputs: buffered and unbuffered.  Take the clock
signal from the buffered output.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-21 12:13:30 +08:00
Sean Cross
ee30de7946 hw: foboot-bitstream: use all 13 bits of the clock reset 
There are 13 bits on the clock reset line, but right now we only use
12 of them.  Set the counter to 8191 so we take advantage of
all 13 bits.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-21 12:12:41 +08:00
Sean Cross
8c84afa4d9 hw: bitstream: add dummyusb if no cpu is present 
This will allow us to still access the wishbone bus without a CPU.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-20 16:29:48 +08:00
Sean Cross
e1a1b60821 hw: foboot-bitstream: use GENCLK_HALF from PLL 
This removes a double-flop that we were using to get a 12 MHz clock,
which we were then multiplying back up to 48 MHz.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-20 16:15:02 +08:00
Sean Cross
541c765198 hw: foboot-bitstream: fix --no-cpu flag 
If there is no CPU, then don't adjust the CPU reset vector.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-20 16:14:35 +08:00
Sean Cross
7452fe05eb releases: release v1.8.6 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-09 13:42:45 +08:00
Sean Cross
eed9897cfc litex: pull latest spi flash changes 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-08 14:14:14 +08:00
Sean Cross
a4a3dad324 hw: fix led ordering on hacker board and add id to "version" 
Fix the ordering of the LEDs on the "hacker" board.

Add a "model id" to the "version" block.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-08 12:14:39 +08:00
Sean Cross
10454fa0be sbled: fix mapping of r,g,b and add bit-bang mode 
Fix the mapping of red, green, and blue.  Now the LEDDPWRR, LEDDPWRG,
and LEDDPWRB map to their correct values.

Additionally, a bit-banged mode for the LED has been added to enable
fine-grained control in a simpler manner.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-08 10:13:09 +08:00
Sean Cross
c622551300
Merge pull request #15 from TomKeddie/tomk_20190701_flashaddr 
Flash mapping address fixes
 2019-07-07 09:20:57 +08:00
Sean Cross
a60b909b88 releases: add bios for v1.8.5 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-06 17:26:32 +08:00
Sean Cross
c7aafa3865 releases: add v1.8.5 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-06 17:25:38 +08:00
Sean Cross
5468cb914a sw: spi: remove lots of dual/quad/qpi code 
This is an effort to fix boards that go into RO mode on their own.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-05 15:23:04 +08:00
Sean Cross
f070b2ab7c release: add v1.8.4 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-04 16:50:38 +08:00
Sean Cross
d1cd68c232 hw: set debug bridge memory size to 0x100 
Hardware breakpoints live at offset 0x40 from the start of this region,
so increase the size from 0x10 to 0x100.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-04 16:39:28 +08:00
Sean Cross
c5b45a4314 Merge branch 'master' of github.com:im-tomu/foboot 2019-07-03 18:13:09 +08:00
Sean Cross
6e0f255b7e releases: add v1.8.3 
This has been tested on machines that were failing with v1.8.1, and is
reliable.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-03 18:12:36 +08:00
Sean Cross
a40dc8a570
Merge pull request #14 from TomKeddie/master 
Create FLASHLAYOUT.md
 2019-07-03 18:09:44 +08:00
Tom Keddie
1c8c1f3bc1 Flash mapping address fixes 
- too many bits were allocated causing problems addressing 128Mbit devices
- the shift operator in python generates a signed shift in verilog which potentilly trashes the upper address bit, switch to padding
 2019-07-03 02:59:20 -07:00
Sean Cross
be187f10d1 fix u16 name size from previous patch 
Since it's a u16, we must remove two bytes not one.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-03 17:58:50 +08:00
Tom Keddie
841627d02f
Create FLASHLAYOUT.md 2019-07-03 02:54:19 -07:00
Sean Cross
f3f4971e09 sw: usb_desc: don't count trailing NULL in string len 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-07-03 17:36:24 +08:00
Tim Ansell
1033016932
Merge pull request #13 from TomKeddie/tomk_20190630_warnings 
sw: Fix warnings in dfu.h and usb-dev.c
 2019-06-30 19:27:02 -07:00